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regarding the change of names mentioned in the document, such as mitsubishi electric and mitsubishi xx, to renesas technology corp. the semiconductor operations of hitachi and mitsubishi electric were transferred to renesas technology corporation on april 1st 2003. these operations include microcomputer, logic, analog and discrete devices, and memory chips other than drams (flash memory, srams etc.) accordingly, although mitsubishi electric, mitsubishi electric corporation, mitsubishi semiconductors, and other mitsubishi brand names are mentioned in the document, these names have in fact all been changed to renesas technology corp. thank you for your understanding. except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. note : mitsubishi electric will continue the business operations of high frequency & optical devices and power devices. renesas technology corp. customer support dept. april 1, 2003 to all our customers
mitsubishi 16-bit single-chip microcomputer 7700 family / 7700 series 7721 group users manual
keep safety first in your circuit designs ! l mitsubishi electric corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. trouble with semiconductors may lead to personal injury, fire or property damage. remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap. notes regarding these materials l these materials are intended as a reference to assist our customers in the selection of the mitsubishi semiconductor product best suited to the customers application; they do not convey any license under any intellectual property rights, or any other rights, belonging to mitsubishi electric corporation or a third party. l mitsubishi electric corporation assumes no responsibility for any damage, or infringement of any third-partys rights, originating in the use of any product data, diagrams, charts or circuit application examples contained in these materials. l all information contained in these materials, including product data, diagrams and charts, represent information on products at the time of publication of these materials, and are subject to change by mitsubishi electric corporation without notice due to product improvements or other reasons. it is therefore recommended that customers contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor for the latest product information before purchasing a product listed herein. l mitsubishi electric corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. please contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. l the prior written approval of mitsubishi electric corporation is necessary to reprint or reproduce in whole or in part these materials. l if these products or technologies are subject to the japanese export control restrictions, they must be exported under a license from the japanese government and cannot be imported into a country other than the approved destination. any diversion or reexport contrary to the export control laws and regulations of japan and/or the country of destination is prohibited. l please contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor for further details on these materials or the products contained therein.
rev. rev. no. date 1.0 first edition 970926 revision description list 7721 group user?s manual (1/1) revision description
this manual describes the hardware of the mitsubishi cmos 16-bit microcomputers 7721 group. after reading this manual, the user will be able to understand the functions, so that their capabilities can fully be utilized. preface
1 before using this manual 1. constitution this users manual consists of the following chapters. refer to the chapters relevant to the products. l chapter 1. description through chapter 16. application functions which are common to the m37721s1bfp and the m37721s2bfp are explained, using the m37721s2bfp as an example. differences between the m37721s1bfp and the m37721s2bfp are described as notes. l appendix practical information for using the 7721 group is described. 2. remark l product expansion refer to the latest catalog and data book, or contact the appropriate office, as listed in contact addresses for further information on the last page. l electrical characteristics refer to the latest data book. l software refer to 7700 family software manual. l development support tools refer to the latest data book of the development support tools. 3. signal levels in figure as a rule, signal levels in each operation example and timing diagram are as follows. ? signal levels the upper line indicates 1, and the lower line indicates 0. ? input/output levels of pin the upper line indicates h, and the lower line indicates l. for the exception, the level is shown on the left side of a signal.
2 4. register structure below is the structure diagram for all registers: 0 1 0 xxx register (address xx 16 ) b1 b0 b2 b3 b4 b5 b6 b7 0 ] 1 ] 2 ] 3 2 3 ... select bit 0 : ... 1 : ... ... select bit 0 : ... 1 : ... the value is 0 at reading. 0 : ... 1 : ... fix this bit to 0. 4 7 to 5 nothing is assigned. 5 rw wo ro rw rw e 0 0 0 bit bit name this bit is invalid in ... mode. functions at reset rw ... flag undefined undefined ] 1 blank : set to 0 or 1 according to the usage. 0 : set to 0 at writing. 1 : set to 1 at writing. 5 : invalid depending on the mode or state. it may be 0 or 1. : nothing is assigned. ] 2 0 : 0 immediately after reset. 1 : 1 immediately after reset. undefined : undefined immediately after reset. ] 3 rw : it is possible to read the bit state at reading. the writt en value becomes valid. ro : it is possible to read the bit state at reading. the writt en value becomes invalid. accordingly, the written value may be 0 or 1. wo : the written value becomes valid. it is impossible to read the bit state. the value is undefined at reading. however, when [0 at reading] is indicated in the functio n or note column, the bit is always 0 at reading. (see ] 4 above.) ? : it is impossible to read the bit state. the value is undef ined at reading. however, when [0 at reading] is indicated in the functio n or note column, the bit is always 0 at reading. (see ] 4 above.) the written value becomes invalid. accordingly, the written value may be 0 or 1. ] 4
7721 group users manual i table of contents table of contents chapter 1 description 1.1 performance overview .......................................................................................................... 1-2 1.2 pin configuration ................................................................................................................... 1-3 1.3 pin description ...................................................................................................................... 1-4 1.4 block diagram ........................................................................................................................ 1-7 chapter 2 central processing unit (cpu) 2.1 central processing unit ....................................................................................................... 2-2 2.1.1 accumulator (acc) ......................................................................................................... 2-3 2.1.2 index register x (x) ....................................................................................................... 2-3 2.1.3 index register y (y) ....................................................................................................... 2-3 2.1.4 stack pointer (s) ............................................................................................................ 2-4 2.1.5 program counter (pc) ................................................................................................... 2-5 2.1.6 program bank register (pg) ......................................................................................... 2-5 2.1.7 data bank register (dt) ................................................................................................ 2-5 2.1.8 direct page register (dpr) ........................................................................................... 2-6 2.1.9 processor status register (ps) ..................................................................................... 2-7 2.2 bus interface unit ................................................................................................................. 2-9 2.2.1 overview ......................................................................................................................... 2-9 2.2.2 functions of bus interface unit (biu) ........................................................................ 2-11 2.2.3 operation of bus interface unit (biu) ........................................................................ 2-13 2.3 access space ....................................................................................................................... 2-15 2.3.1 banks ............................................................................................................................ 2-16 2.3.2 direct page ................................................................................................................... 2-16 2.4 memory assignment ........................................................................................................... 2-17 2.4.1 memory assignment in internal area ......................................................................... 2-17 2.4.2 external area ................................................................................................................ 2-18 2.5 bus access right ................................................................................................................. 2-23 chapter 3 connection with external devices 3.1 signals required for accessing external devices .......................................................... 3-2 3.1.1 descriptions of signals .................................................................................................. 3-2 3.1.2 operation of bus interface unit (biu) .......................................................................... 3-5 3.2 software wait ......................................................................................................................... 3-8 3.3 ready function .................................................................................................................... 3-10 3.3.1 operation description .................................................................................................. 3-11 3.4 hold function ....................................................................................................................... 3-12 3.4.1 operation description .................................................................................................. 3-12 [precautions for hold function] ............................................................................................ 3-16
7721 group users manual ii table of contents chapter 4 reset 4.1 hardware reset ...................................................................................................................... 4-2 4.1.1 pin state .......................................................................................................................... 4-3 4.1.2 state of cpu, sfr area, and internal ram area ..................................................... 4-4 4.1.3 internal processing sequence after reset ................................................................. 4-11 ______ 4.1.4 time supplying l level to reset pin .................................................................... 4-12 4.2 software reset ...................................................................................................................... 4-13 chapter 5 clock generating circuit 5.1 oscillation circuit examples ............................................................................................... 5-2 5.1.1 connection example using resonator/oscillator .......................................................... 5-2 5.1.2 externally generated clock input example .................................................................. 5-2 5.2 clocks .......................................................................................................................................5-3 5.2.1 clocks generated in clock generating circuit ............................................................. 5-4 5.3 stop mode .............................................................................................................................. 5-5 5.3.1 stop mode ...................................................................................................................... 5-5 [precautions for stop mode] .................................................................................................. 5-8 5.4 wait mode ............................................................................................................................... 5-9 5.4.1 wait mode ...................................................................................................................... 5-9 [precautions for wait mode] ................................................................................................. 5-11 chapter 6 input/output pins 6.1 overview ..................................................................................................................................6-2 6.2 programmable i/o ports ...................................................................................................... 6-2 6.2.1 direction register ............................................................................................................ 6-3 6.2.2 port register .................................................................................................................... 6-4 6.3 examples of handling unused pins .................................................................................. 6-7 chapter 7 interrupts 7.1 overview ..................................................................................................................................7-2 7.2 interrupt sources ................................................................................................................... 7-4 7.3 interrupt control .................................................................................................................... 7-5 7.3.1 interrupt disable flag (i) ................................................................................................ 7-7 7.3.2 interrupt request bit ....................................................................................................... 7-7 7.3.3 interrupt priority level select bits and processor interrupt priority level (ipl) ....... 7-7 7.4 interrupt priority level .......................................................................................................... 7-9 7.5 interrupt priority level detection circuit ........................................................................ 7-10 7.6 interrupt priority level detection time ............................................................................ 7-12 7.7 sequence from acceptance of interrupt request until execution of interrupt routine .................................................................................................................................... 7-13 7.7.1 change in ipl at acceptance of interrupt request .................................................. 7-14 7.7.2 push operation for registers ....................................................................................... 7-15 7.8 return from interrupt routine ........................................................................................... 7-16 7.9 multiple interrupts ............................................................................................................... 7-16 ____ 7.10 external interrupts (inti interrupt) ............................................................................... 7-18 ____ 7.10.1 functions of inti interrupt request bit .................................................................... 7-20 ____ 7.10.2 switching of inti interrupt request occurrence factor .......................................... 7-21 7.11 precautions for interrupts ............................................................................................... 7-22
7721 group users manual iii table of contents chapter 8 timer a 8.1 overview ..................................................................................................................................8-2 8.2 block description .................................................................................................................. 8-3 8.2.1 counter and reload register (timer ai register) ......................................................... 8-4 8.2.2 count start register ........................................................................................................ 8-5 8.2.3 timer ai mode register ................................................................................................. 8-6 8.2.4 timer ai interrupt control register ............................................................................... 8-7 8.2.5 port p5 direction register ............................................................................................. 8-8 8.3 timer mode ............................................................................................................................ 8-9 8.3.1 setting for timer mode ................................................................................................ 8-11 8.3.2 count source ................................................................................................................ 8-13 8.3.3 operation in timer mode ............................................................................................. 8-14 8.3.4 selectable functions .................................................................................................... 8-15 [precautions for timer mode] ................................................................................................ 8-17 8.4 event counter mode ........................................................................................................... 8-18 8.4.1 setting for event counter mode ................................................................................. 8-21 8.4.2 operation in event counter mode .............................................................................. 8-23 8.4.3 switching between countup and countdown ............................................................ 8-24 8.4.4 selectable functions .................................................................................................... 8-25 [precautions for event counter mode] ................................................................................. 8-28 8.5 one-shot pulse mode ......................................................................................................... 8-29 8.5.1 setting for one-shot pulse mode ............................................................................... 8-31 8.5.2 count source ................................................................................................................ 8-33 8.5.3 trigger ........................................................................................................................... 8-34 8.5.4 operation in one-shot pulse mode ............................................................................ 8-35 [precautions for one-shot pulse mode] ............................................................................... 8-37 8.6 pulse width modulation (pwm) mode ............................................................................ 8-38 8.6.1 setting for pwm mode ............................................................................................... 8-40 8.6.2 count source ................................................................................................................ 8-42 8.6.3 trigger ........................................................................................................................... 8-42 8.6.4 operation in pwm mode ............................................................................................ 8-43 [precautions for pwm mode] ............................................................................................... 8-47 chapter 9 timer b 9.1 overview ..................................................................................................................................9-2 9.2 block description .................................................................................................................. 9-2 9.2.1 counter and reload register (timer bi register) ......................................................... 9-3 9.2.2 count start register ........................................................................................................ 9-4 9.2.3 timer bi mode register ................................................................................................. 9-5 9.2.4 timer bi interrupt control register ............................................................................... 9-6 9.2.5 port p5 direction register ............................................................................................. 9-7 9.3 timer mode ............................................................................................................................ 9-8 9.3.1 setting for timer mode ................................................................................................ 9-10 9.3.2 count source ................................................................................................................ 9-11 9.3.3 operation in timer mode ............................................................................................. 9-12 [precautions for timer mode] ................................................................................................ 9-13 9.4 event counter mode ........................................................................................................... 9-14 9.4.1 setting for event counter mode ................................................................................. 9-16 9.4.2 operation in event counter mode .............................................................................. 9-17 [precautions for event coutner mode] ................................................................................. 9-18
7721 group users manual iv table of contents 9.5 pulse period/pulse width measurement mode ............................................................. 9-19 9.5.1 setting for pulse period/pulse width measurement mode ...................................... 9-21 9.5.2 count source ................................................................................................................ 9-22 9.5.3 operation in pulse period/pulse width measurement mode ................................... 9-23 [precautions for pulse period/pulse width measurement mode] ...................................... 9-25 chapter 10 real-time output 10.1 overview ............................................................................................................................. 10-2 10.2 block description .............................................................................................................. 10-4 10.2.1 real-time output control register ............................................................................. 10-4 10.2.2 pulse output data registers 0 and 1 ....................................................................... 10-5 10.2.3 port p6 direction register ......................................................................................... 10-6 10.2.4 timers a0 and a1 ..................................................................................................... 10-6 10.3 setting of real-time output ............................................................................................. 10-7 10.4 real-time output operation ........................................................................................... 10-10 chapter 11 serial i/o 11.1 overview ............................................................................................................................. 11-2 11.2 block description .............................................................................................................. 11-3 11.2.1 uarti transmit/receive mode register .................................................................... 11-4 11.2.2 uarti transmit/receive control register 0 .............................................................. 11-6 11.2.3 uarti transmit/receive control register 1 .............................................................. 11-7 11.2.4 uarti transmit register and uarti transmit buffer register ............................... 11-9 11.2.5 uarti receive register and uarti receive buffer register ................................ 11-11 11.2.6 uarti baud rate register (brgi) .......................................................................... 11-13 11.2.7 uarti transmit interrupt control and uarti receive interrupt control registers ......................... 11-14 11.2.8 port p8 direction register ....................................................................................... 11-15 11.3 clock synchronous serial i/o mode ........................................................................... 11-16 11.3.1 transfer clock (synchronizing clock) .................................................................... 11-17 11.3.2 method of transmission ........................................................................................... 11-18 11.3.3 transmit operation ................................................................................................... 11-21 11.3.4 method of reception ................................................................................................ 11-23 11.3.5 receive operation .................................................................................................... 11-27 11.3.6 processing on detecting overrun error ................................................................. 11-29 [precautions for clock synchronous serial i/o mode] ..................................................... 11-30 11.4 clock asynchronous serial i/o (uart) mode .......................................................... 11-31 11.4.1 transfer rate (frequency of transfer clock) ......................................................... 11-32 11.4.2 transfer data format ............................................................................................... 11-33 11.4.3 method of transmission ........................................................................................... 11-34 11.4.4 transmit operation ................................................................................................... 11-38 11.4.5 method of reception ................................................................................................ 11-41 11.4.6 receive operation .................................................................................................... 11-44 11.4.7 processing on detecting error ................................................................................ 11-46 11.4.8 sleep mode .............................................................................................................. 11-47
7721 group users manual v table of contents chapter 12 a-d converter 12.1 overview ............................................................................................................................. 12-2 12.2 block description .............................................................................................................. 12-3 12.2.1 a-d control register ................................................................................................... 12-4 12.2.2 a-d sweep pin select register ................................................................................. 12-6 12.2.3 a-d register i (i = 0 to 7) ......................................................................................... 12-7 12.2.4 a-d conversion interrupt control register ................................................................ 12-8 12.2.5 port p7 direction register ......................................................................................... 12-9 12.3 a-d conversion method ................................................................................................. 12-10 12.4 absolute accuracy and differential non-linearity error .......................................... 12-12 12.4.1 absolute accuracy ................................................................................................... 12-12 12.4.2 differential non-linearity error ................................................................................. 12-13 12.5 one-shot mode ................................................................................................................ 12-14 12.5.1 settings for one-shot mode .................................................................................... 12-14 12.5.2 one-shot mode operation description ................................................................... 12-16 12.6 repeat mode .................................................................................................................... 12-17 12.6.1 settings for repeat mode ........................................................................................ 12-17 12.6.2 repeat mode operation description ...................................................................... 12-19 12.7 single sweep mode ........................................................................................................ 12-20 12.7.1 settings for single sweep mode ............................................................................ 12-20 12.7.2 single sweep mode operation description ............................................................ 12-22 12.8 repeat sweep mode ....................................................................................................... 12-24 12.8.1 settings for repeat sweep mode ........................................................................... 12-24 12.8.2 repeat sweep mode operation description .......................................................... 12-26 12.9 precautions for a-d converter ..................................................................................... 12-28 chapter 13 dma controller 13.1 overview ............................................................................................................................. 13-2 13.1.1 performance overview ............................................................................................... 13-2 13.1.2 bus use priority levels .............................................................................................. 13-3 13.1.3 modes .......................................................................................................................... 13-3 13.2 block description .............................................................................................................. 13-6 13.2.1 bus access control circuit ........................................................................................ 13-7 13.2.2 dmac control register l ......................................................................................... 13-10 13.2.3 dmac control register h ........................................................................................ 13-11 13.2.4 source address register i (sari) .......................................................................... 13-12 13.2.5 destination address register i (dari) ................................................................... 13-12 13.2.6 transfer counter register i (tcri) ......................................................................... 13-12 13.2.7 incrementer/decrementer ........................................................................................ 13-13 13.2.8 decrementer ............................................................................................................. 13-13 13.2.9 dma latch ................................................................................................................. 13-13 13.2.10 dmai mode register l ........................................................................................... 13-14 13.2.11 dmai mode register h .......................................................................................... 13-15 13.2.12 dmai control register ............................................................................................ 13-16 13.2.13 dmai interrupt control register ............................................................................. 13-17 13.2.14 port p9 direction register ..................................................................................... 13-18 [precautions for dmac] ...................................................................................................... 13-18
7721 group users manual vi table of contents 13.3 control ............................................................................................................................... 13-19 13.3.1 dma enabling ........................................................................................................... 13-19 13.3.2 dma requests .......................................................................................................... 13-20 13.3.3 channel priority levels ............................................................................................ 13-21 13.3.4 processing from dma request until dma transfer execution ............................ 13-23 13.3.5 termination of dma transfer .................................................................................. 13-25 13.3.6 dma transfer restart after termination .................................................................. 13-28 13.4 operation .......................................................................................................................... 13-30 13.4.1 2-bus cycle transfer ................................................................................................. 13-30 [precautions for 2-bus cycle transfer] ............................................................................... 13-37 13.4.2 1-bus cycle transfer ................................................................................................. 13-38 [precautions for 1-bus cycle transfer] ............................................................................... 13-47 13.4.3 burst transfer mode ................................................................................................. 13-48 [precautions for burst transfer mode] ............................................................................... 13-50 13.4.4 cycle-steal transfer mode ....................................................................................... 13-51 [precautions for cycle-steal transfer mode] ...................................................................... 13-52 13.5 single transfer mode ...................................................................................................... 13-54 13.5.1 setting of single transfer mode ............................................................................. 13-56 13.5.2 operation in single transfer mode ......................................................................... 13-59 13.6 repeat transfer mode .................................................................................................... 13-61 13.6.1 setting of repeat transfer mode ............................................................................ 13-63 13.6.2 operation in repeat transfer mode ........................................................................ 13-66 13.7 array chain transfer mode ............................................................................................ 13-68 13.7.1 transfer parameter memory in array chain transfer mode ................................ 13-70 13.7.2 setting of array chain transfer mode .................................................................... 13-72 13.7.3 operation in array chain transfer mode ............................................................... 13-75 [precautions for array chain transfer mode] .................................................................... 13-79 13.8 link array chain transfer mode ................................................................................... 13-80 13.8.1 transfer parameter memory in link array chain transfer mode ......................... 13-82 13.8.2 setting of link array chain transfer mode ............................................................. 13-84 13.8.3 operation in link array chain transfer mode ........................................................ 13-87 [precautions for link array chain transfer mode] ............................................................. 13-97 13.9 dma transfer time ........................................................................................................... 13-98 13.9.1 cycle-steal transfer mode ....................................................................................... 13-98 13.9.2 burst transfer mode ............................................................................................... 13-101 chapter 14 dram controller 14.1 overview ............................................................................................................................. 14-2 14.2 block description .............................................................................................................. 14-2 14.2.1 dram control register ............................................................................................... 14-3 14.2.2 refresh timer .............................................................................................................. 14-5 14.2.3 address comparator .................................................................................................. 14-6 ____ ____ 14.2.4 ras and cas generating circuit ............................................................................. 14-6 14.2.5 address multiplexer ................................................................................................... 14-6 14.3 setting for dramc ........................................................................................................... 14-7 14.4 dramc operation ............................................................................................................. 14-8 14.4.1 waveform example of dram control signals ........................................................ 14-8 14.4.2 refresh request ....................................................................................................... 14-10 14.5 precautions for dramc ................................................................................................ 14-12
7721 group users manual vii table of contents chapter 15 watchdog timer 15.1 block description .............................................................................................................. 15-2 15.1.1 watchdog timer .......................................................................................................... 15-3 15.1.2 watchdog timer frequency select register .............................................................. 15-3 15.2 operation description ...................................................................................................... 15-4 15.2.1 basic operation .......................................................................................................... 15-4 15.2.2 stop period ................................................................................................................. 15-6 15.2.3 operation in stop mode ........................................................................................... 15-6 15.3 precautions for watchdog timer ................................................................................... 15-7 chapter 16 application 16.1 memory connection .......................................................................................................... 16-2 16.1.1 memory connection model ........................................................................................ 16-2 16.1.2 how to calculate timing ............................................................................................ 16-4 16.1.3 example of memory connection ............................................................................ 16-20 16.1.4 example of i/o expansion ...................................................................................... 16-40 16.2 examples of using dma controller ............................................................................. 16-43 16.2.1 example of centronics interface configuration .................................................... 16-43 16.2.2 example of stepping motor control ....................................................................... 16-48 16.2.3 example of dynamic lighting for led ................................................................... 16-53 16.3 comparison of sample program execution rate ...................................................... 16-56 16.3.1 differences depending on data bus width and software wait ........................... 16-56 16.3.2 comparison between software wait (f(x in ) = 20 mhz) and software wait + ready (f(x in ) = 25 mhz) .... 16-58 appendix appendix 1. memory assignment of 7721 group ............................................................... 17-2 appendix 2. memory assignment in sfr area ................................................................... 17-3 appendix 3. control registers ................................................................................................. 17-9 appendix 4. package outline ................................................................................................ 17-40 appendix 5. examples of handling unused pins ............................................................. 17-41 appendix 6. machine instructions ....................................................................................... 17-42 appendix 7. hexadecimal instruction code table ............................................................. 17-56 appendix 8. countermeasure against noise ...................................................................... 17-59 appendix 9. 7721 group q & a ........................................................................................... 17-65 appendix 10. differences between 7721 group and 7720 group ................................. 17-79 appendix 11. electrical characteristics .............................................................................. 17-80 appendix 12. standard characteristics ............................................................................. 17-107 glossary
7721 group users manual viii table of contents memorandum
chapter 1 description 1.1 performance overview 1.2 pin configuration 1.3 pin description 1.4 block diagram
description 7721 group users manual 1C2 1.1 performance overview 1.1 performance overview table 1.1.1 lists the performance overview of the m37721. table 1.1.1 m37721 performance overview rom ram p5Cp10 p4 ta0Cta4 tb0Ctb2 uart0, uart1 m37721s2bfp m37721s1bfp parameters number of basic instructions instruction execution time external clock input frequency f(x in ) memory sizes programmable input/output ports multifunctional timers serial i/o a-d converter watchdog timer dma controller dram controller real-time output interrupts clock generating circuit supply voltage power dissipation port input/output characteristics memory expansion operating temperature range device structure package input/output withstand voltage output current functions 103 160 ns (the minimum instruction at f(x in ) = 25 mhz) 25 mhz (maximum) external 1024 bytes 512 bytes 8 bits 5 6 5 bits 5 1 16 bits 5 5 16 bits 5 3 (uart or clock synchronous serial i/o) 5 2 8-bit successive approximation method 5 1 (8 channels) 12 bits 5 1 4 channels maximum transfer rate : 12.5 mbytes/sec. (at f(x in ) = 25 mhz, 1-bus cycle transfer) maximum transfer rate : 6.25 mbytes/sec. (at f(x in ) = 25 mhz, 2-bus cycle transfer) ____ ____ cas before ras refreshing method 4 bits 5 2 channels or 6 bits 5 1 channel + 2 bits 5 1 channel 3 external, 20 internal (priority levels 0 to 7 can be set for each interrupt with software) built-in (externally connected to a ceramic resonator or a quartz-crystal oscillator) 5 v 10 % 135 mw (at f(x in ) = 25 mhz, typ.) 5 v 5 ma maximum 16 mbytes C20c to 85c cmos high-performance silicon gate process 100-pin plastic molded qfp
description 7721 group users manual 1C3 1.2 pin configuration figure 1.2.1 shows the m37721s2bfp pin configuration. 1.2 pin configuration fig. 1.2.1 m37721s2bfp pin configuration (top view) 34 31 32 33 35 36 37 38 39 40 p6 7 /rtp1 3 p6 6 /rtp1 2 p6 5 /rtp1 1 p6 4 /rtp1 0 p6 3 /rtp0 3 p6 2 /rtp0 2 p6 1 /rtp0 1 p6 0 /rtp0 0 p5 7 /tb1 in p5 6 /tb0 in p5 5 /ta4 in p5 4 /ta4 out p5 3 /ta3 in p5 2 /ta3 out p5 1 /ta2 in p5 0 /ta2 out p10 7 /ma 9 p10 6 /ma 8 p10 5 /ras p10 4 /cas p10 3 /tc p10 2 /int 2 p10 1 /int 1 p10 0 /int 0 p4 7 p4 6 p4 5 p4 4 p4 3 1 p8 7 /t x d 1 p9 0 /dmaack0 p9 1 /dmareq0 p9 2 /dmaack1 p9 3 /dmareq1 p9 4 /dmaack2 p9 5 /dmareq2 p9 6 /dmaack3 p9 7 /dmareq3 a 0 /ma 0 a 1 /ma 1 a 2 /ma 2 a 3 /ma 3 a 4 /ma 4 a 5 /ma 5 a 6 /ma 6 a 7 /ma 7 a 8 /d 8 a 9 /d 9 a 10 /d 10 a 11 /d 11 a 12 /d 12 a 13 /d 13 a 14 /d 14 a 15 /d 15 a 16 /d 0 a 17 /d 1 a 18 /d 2 a 19 /d 3 a 20 /d 4 a 21 /d 5 a 22 /d 6 a 23 /d 7 r/w bhe ble ale st0 st1 v cc v ss e x out x in reset reset out cnv ss byte hold rdy 25 27 26 28 29 30 1 4 3 2 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 80 79 78 77 76 75 74 73 72 71 69 68 67 66 65 70 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 p8 6 /r x d 1 p8 5 /clk 1 p8 4 /cts 1 /rts 1 p8 3 /t x d 0 p8 2 /r x d 0 p8 1 /clk 0 p8 0 /cts 0 /rts 0 v cc av cc v ref av ss v ss p7 7 /an 7 /ad trg p7 6 /an 6 p7 5 /an 5 p7 4 /an 4 p7 3 /an 3 p7 2 /an 2 p7 1 /an 1 p7 0 /an 0 outline 100p6s-a m37721s2bfp
description 7721 group users manual 1C4 1.3 pin description tables 1.3.1 to 1.3.3 list the pin description. table 1.3.1 pin description (1) 1.3 pin description pin vcc, vss cnvss ______ reset ________ reset out x in x out _ e byte st0 st1 avcc avss v ref input/output input input output input output output input output input st1 0 0 1 1 st0 0 1 0 1 bus use state dram refresh hold dma cpu functions supply 5 v 10 % to vcc pin and 0 v to vss pin. connect to vss or vcc pin. the microcomputer is reset when supplying l level to this pin. ______ when input to reset pin is l, this pin outputs l. output from this pin returns h after the release of reset. when writing 1 to the software reset bit, this pin outputs l. these are i/o pins of the internal clock generating circuit. connect a ceramic resonator or quartz-crystal oscillator between pins x in and x out . when using an external clock, the clock source should be input to x in pin and x out pin should be left open. data/instruction code read or data write is performed when output from this pin is l level. input level to this pin determines whether the external data bus has a 16-bit width or an 8-bit width. the width is 16 bits when the level is l, and 8 bits when the level is h. the bus use state is output in 2-bit code. the power supply pin for the a-d converter. connect avcc to vcc pin. connect avss to vss pin. this is a reference voltage input pin for the a-d converter. name power supply cnvss reset input reset output clock input clock output enable output exernal data bus width selection input status signal output analog supply input reference voltage input
description 7721 group users manual 1C5 table 1.3.2 pin description (2) 1.3 pin description functions low-order 8 bits (a 0 Ca 7 ) of the address are output. when the dram is accessed, the row and column addresses are output with the time-sharing. l external data bus width = 8 bits (when the byte pin is h level) middle-order 8 bits (a 8 Ca 15 ) of the address are output. l external data bus width = 16 bits (when the byte pin is l level) data (d 8 Cd 15 ) input/output and output of the middle- order 8 bits (a 8 Ca 15 ) of the address are performed with the time-sharing. data (d 0 Cd 7 ) input/output and output of the high-order 8 bits (a 16 Ca 23 ) of the address are performed with the time-sharing. __ l r/w the read/write signal indicates the data bus state. the state is read while this signal is h level, and write while this signal is l level. ____ l bhe l level is output when an odd-numbered address is accessed. ____ l ble l level is output when an even-numbered address is accessed. l ale this is used to obtain only the address from address and data multiplex signals. the microcomputer is in hold state while l level is _____ input to the hold pin. the microcomputer is in ready state while l level is ____ input to the rdy pin. this is the f 1 output pin. input/output output i/o i/o output input input output name address low-order/ dram address address middle-order / data high-order address high-order / data low-order memory control signal output hold input ready input clock f 1 output pin a 0 /ma 0 C a 7 /ma 7 a 8 /d 8 C a 15 /d 15 a 16 /d 0 C a 23 /d 7 __ r/w, ____ bhe, ____ ble, ale _____ hold ____ rdy f 1
description 7721 group users manual 1C6 1.3 pin description table 1.3.3 pin description (3) pin p4 3 Cp4 7 p5 0 Cp5 7 p6 0 Cp6 7 p7 0 Cp7 7 p8 0 Cp8 7 p9 0 Cp9 7 p10 0 C p10 7 functions port p4 is a 5-bit cmos i/o port. this port has an i/o direction register and each pin can be programmed for input or output. port p5 is an 8-bit i/o port with the same function as p4. these pins can be programmed as i/o pins for timers a2Ca4 and i/o pins for timers b0, b1. port p6 is an 8-bit i/o port with the same function as p4. these pins can be programmed as output pins for the real-time output. port p7 is an 8-bit i/o port with the same function as p4. these pins can be programmed as input pins for a-d converter. port p8 is an 8-bit i/o port with the same function as p4. these pins can be programmed as i/o pins for serial i/o. port p9 is an 8-bit i/o port with the same function as p4. these pins can be programmed as i/o pins for dma controller. port p10 is an 8-bit i/o port with the same function as __ p4. these pins can be programmed as i/o pin for tc and output pins for dram controller. ___ ___ p10 0 Cp10 2 also function as input pins for int 0 Cint 2 . name i/o port p4 i/o port p5 i/o port p6 i/o port p7 i/o port p8 i/o port p9 i/o port p10 input/output i/o i/o i/o i/o i/o i/o i/o
description 7721 group users manual 1C7 1.4 block diagram figure 1.4.1 shows the m37721 block diagram. 1.4 block diagram reset output reset out data buffer db l (8) instruction queue buffer q 2 (8) data bank register dt (8) program counter pc (16) incrementer/decrementer (24) program bank register pg (8) input buffer register ib (16) direct page register dpr (16) stack pointer s (16) index register y (16) index register x (16) arithmetic logic unit (16) accumulator a (16) instruction register (8) data bus (odd) central processing unit (cpu) incrementer (24) program address register pa (24) data address register da (24) address bus bus interface unit (biu) processor status register ps (11) a-d converter (8) uart1 (9) uart0 (9) watchdog timer timer ta4 (16) rom 1024 bytes address/data (16) address/data address (8) p5 (8) p6 (8) p7 (8) input/output port p4 p4 (5) reset input reset (0v) v ss cnvss reference voltage input v ref (0v) av ss av cc v cc external data bus width selection input byt e clock generating circuit clock input x in enable output e dma0 (16) dma1 (16) dma2 (16) dma3 (16) dram controller rdy hold r/w bhe clock 1 output 1 ble ale st0 status signal output memory control signal output st1 note: for the m37721s1bfp, the ram size is 512 bytes. clock output x out accumulator b (16) instruction queue buffer q 1 (8) instruction queue buffer q 0 (8) data buffer db h (8) timer ta3 (16) timer ta2 (16) timer ta1 (16) timer ta0 (16) timer tb2 (16) timer tb1 (16) timer tb0 (16) data bus (even) input/output port p5 input/output port p6 input/output port p7 p8 (8) input/output port p8 input/output port p9 p9 (8) p10 (8) input/output port p10 fig. 1.4.1 m37721 block diagram
description 7721 group users manual 1C8 memorandum 1.4 block diagram
chapter 2 central processing unit (cpu) 2.1 central processing unit 2.2 bus interface unit 2.3 access space 2.4 memory assignment 2.5 bus access right
central processing unit (cpu) 2.1 central processing unit 2C2 7721 group users manual 2.1 central processing unit the cpu (central processing unit) has the ten registers as shown in figure 2.1.1. fig. 2.1.1 cpu registers structure b0 b7 b8 b15 a h a l b0 b7 b8 b15 b h b l b0 b7 b8 b15 x h x l b0 b7 b8 b15 y h y l b0 b7 b8 b15 s h s l b0 b7 b8 b15 b7 b0 b8 b23 b16 b15 b7 b0 pc h pc l pg b0 b7 dt b0 b7 b8 b15 b0 b1 b2 b3 b4 b5 b6 b7 b8 b10 00000 c z i d x m v n ipl accumulator a (a) accumulator b (b) index register x (x) index register y (y) stack pointer (s) data bank register (dt) program counter (pc) program bank register (pg) direct page register (dpr) processor status register (ps) processor interrupt priority level carry flag zero flag interrupt disable flag index register length flag decimal mode flag data length flag overflow flag negative flag dpr l dpr h ps l ps h b15
7721 group users manual 2.1 central processing unit central processing unit (cpu) 2C3 2.1.1 accumulator (acc) accumulators a and b are available. (1) accumulator a (a) accumulator a is the main register of the microcomputer. the transaction of data such as calculation, data transfer, and input/output are performed mainly through accumulator a. it consists of 16 bits, and the low-order 8 bits can also be used separately. the data length flag (m) determines whether the register is used as a 16-bit register or as an 8-bit register. when an 8-bit register is selected, only the low-order 8 bits of accumulator a are used and the contents of the high-order 8 bits is unchanged. (2) accumulator b (b) accumulator b is a 16-bit register with the same function as accumulator a. accumulator b can be used instead of accumulator a. the use of accumulator b, however except for some instructions, requires more instruction bytes and execution cycles than that of accumulator a. accumulator b is also controlled by the data length flag (m) just as in accumulator a. 2.1.2 index register x (x) index register x consists of 16 bits and the low-order 8 bits can also be used separately. the index register length flag (x) determines whether the register is used as a 16-bit register or as an 8-bit register. when an 8-bit register is selected, only the low-order 8 bits of index register x are used and the contents of the high-order 8 bits is unchanged. in an addressing mode in which index register x is used as an index register, the address obtained by adding the contents of this register to the operands contents is accessed. in the mvp or mvn instruction, a block transfer instruction, the contents of index register x indicate the low-order 16 bits of the source address. the third byte of the instruction is the high-order 8 bits of the source address. note: refer to 7700 family software manual for addressing modes. 2.1.3 index register y (y) index register y is a 16-bit register with the same function as index register x. just as in index register x, the index register length flag (x) determines whether this register is used as a 16-bit register or as an 8-bit register. in the mvp or mvn instruction, a block transfer instruction, the contents of index register y indicate the low-order 16 bits of the destination address. the second byte of the instruction is the high-order 8 bits of the destination address.
central processing unit (cpu) 2.1 central processing unit 2C4 7721 group users manual 2.1.4 stack pointer (s) the stack pointer (s) is a 16-bit register. it is used for a subroutine call or an interrupt. it is also used when addressing modes using the stack are executed. the contents of s indicate an address (stack area) for storing registers during subroutine calls and interrupts. stack area is selected by the stack bank select bit described later (bit 7 at address 5e 16 ). the stack area is specified to bank 0 16 when the stack bank select bit is 0, and the stack area is specified to bank ff 16 when it is 1. when an interrupt request is accepted, the microcomputer stores the contents of the program bank register (pg) at the address indicated by the contents of s and decrements the contents of s by 1. then the contents of the program counter (pc) and the processor status register (ps) are stored. the contents of s after accepting an interrupt request is equal to the contents of s decremented by 5 before the accepting of the interrupt request. (refer to figure 2.1.2. ) when completing the process in the interrupt routine and returning to the original routine, the contents of registers stored in the stack area are restored into the original registers in the reverse sequence (ps ? pc ? pg) by executing the rti instruction. the contents of s is returned to the state before accepting an interrupt request. the same operation is performed during a subroutine call, however, the contents of ps is not automatically stored. (the contents of pg may not be stored. this depends on the addressing mode.) the user should store registers other than those described above with software when the user needs them during interrupts or subroutine calls. additionally, initialize s at the beginning of the program because its contents are undefined at reset. the stack area changes when subroutines are nested or when multiple interrupt requests are accepted. therefore, make sure of the subroutines nesting depth not to destroy the necessary data. note: refer to 7700 family software manual for addressing modes. fig. 2.1.2 stored registers of the stack area l ??is the initial address that the stack pointer (s) indicates at accepting an interrupt request. the s? contents become ???after storing the above registers. address s? s? s? s? s stack area s? processor status register? low-order byte (ps l ) processor status register? high-order byte (ps h ) program counter? low-order byte (pc l ) program counter? high-order byte (pc h ) program bank register (pg)
7721 group users manual 2.1 central processing unit central processing unit (cpu) 2C5 2.1.5 program counter (pc) the program counter is a 16-bit counter that indicates the low-order 16 bits of the address (24 bits) at which an instruction to be executed next (in other words, an instruction to be read out from an instruction queue buffer next) is stored. the contents of the high-order program counter (pc h ) become ff 16 , and the low-order program counter (pc l ) becomes fe 16 at reset. the contents of the program counter becomes the contents of the resets vector address (addresses fffe 16 , ffff 16 ) immediately after reset. figure 2.1.3 shows the program counter and the program bank register. fig. 2.1.3 program counter and program bank register 2.1.6 program bank register (pg) the access space is divided in units of 64 kbytes. this unit is called bank. (refer to section 2.3 access space. ) the program bank register is an 8-bit register. this register indicates the high-order 8 bits (bank) of the address (24 bits) at which an instruction to be executed next (in other words, an instruction to be read out from an instruction queue buffer next) is stored. these 8 bits are called bank. when a carry occurs after adding the contents of the program counter or adding the offset value to the contents of the program counter in the branch instruction and others, the contents of the program bank register is automatically incremented by 1. when a borrow occurs after subtracting the contents of the program counter, the contents of the program bank register is automatically decremented by 1. accordingly, there is no need to consider bank boundaries in programming, usually. this register is cleared to 00 16 at reset. 2.1.7 data bank register (dt) the data bank register is an 8-bit register. in the following addressing modes using the data bank register, the contents of this register is used as the high-order 8 bits (bank) of a 24-bit address to be accessed. use the ldt instruction to set a value to this register. this register is cleared to 00 16 at reset. l addressing modes using data bank register ?direct indirect ?direct indexed x indirect ?direct indirect indexed y ?absolute ?absolute bit ?absolute indexed x ?absolute indexed y ?absolute bit relative ?stack pointer relative indirect indexed y pc h pc l b7 b0 b15 b8 b7 b0 (b16) (b23) pg
central processing unit (cpu) 2.1 central processing unit 2C6 7721 group users manual 2.1.8 direct page register (dpr) the direct page register is a 16-bit register. the contents of this register indicate the direct page area which is allocated in bank 0 16 or in the space across banks 0 16 and 1 16 . the following addressing modes use the direct page register. the contents of the direct page register indicate the base address (the lowest address) of the direct page area. the space which extends to 256 bytes above that address is specified as a direct page. the direct page register can contain a value from 0000 16 to ffff 16 . when it contains a value equal to or more than ff01 16 , the direct page area spans the space across banks 0 16 and 1 16 . when the contents of low-order 8 bits of the direct page register is 00 16 , the number of cycles required to generate an address is 1 cycle smaller than the number when its contents are not 00 16 . accordingly, the access efficiency can be enhanced in this case. this register is cleared to 0000 16 at reset. figure 2.1.4 shows a setting example of the direct page area. l addressing modes using direct page register ?direct ?direct bit ?direct indexed x ?direct indexed y ?direct indirect ?direct indexed x indirect ?direct indirect indexed y ?direct indirect long ?direct indirect long indexed y ?direct bit relative notes 1: the number of cycles required to generate an address is 1 cycle smaller when the low-order 8 bits of the dpr are 00 16 . 2: the direct page area spans the space across banks 0 16 and 1 16 when the dpr is ff01 16 or more. fig. 2.1.4 setting example of direct page area bank 0 16 bank 1 16 0 16 ff 16 123 16 222 16 ff10 16 1000f 16 0 16 ffff 16 10000 16 direct page area when dpr = ff10 16 (note 2) direct page area when dpr = 0000 16 direct page area when dpr = 0123 16 (note 1)
7721 group users manual 2.1 central processing unit central processing unit (cpu) 2C7 2.1.9 processor status register (ps) the processor status register is an 11-bit register. figure 2.1.5 shows the structure of the processor status register. processor status register (ps) note: bits 11C15 is always 0 at reading. fig. 2.1.5 processor status register structure (1) bit 0: carry flag (c) it retains a carry or a borrow generated in the arithmetic and logic unit (alu) during an arithmetic operation. this flag is also affected by shift and rotate instructions. when the bcc or bcs instruction is executed, this flags contents determine whether the program causes a branch or not. use the sec or sep instruction to set this flag to 1, and use the clc or clp instruction to clear it to 0. (2) bit 1: zero flag (z) it is set to 1 when a result of an arithmetic operation or data transfer is 0, and cleared to 0 when otherwise. when the bne or beq instruction is executed, this flags contents determine whether the program causes a branch or not. use the sep instruction to set this flag to 1, and use the clp instruction to clear it to 0. note: this flag is invalid in the decimal mode addition (the adc instruction). (3) bit 2: interrupt disable flag (i) it disables all maskable interrupts (interrupts other than watchdog timer, the brk instruction, and zero division). interrupts are disabled when this flag is 1. when an interrupt request is accepted, this flag is automatically set to 1 to avoid multiple interrupts. use the sei or sep instruction to set this flag to 1, and use the cli or clp instruction to clear it to 0. this flag is set to 1 at reset. (4) bit 3: decimal mode flag (d) it determines whether addition and subtraction are performed in binary or decimal. binary arithmetic is performed when this flag is 0. when it is 1, decimal arithmetic is performed with 8 bits treated as two digits decimal (the data length flag (m) = 1) or 16 bits treated as four digits decimal (the data length flag (m) = 0). decimal adjust is automatically performed. decimal operation is possible only with the adc and sbc instructions. use the sep instruction to set this flag to 1, and use the clp instruction to clear it to 0. this flag is cleared to 0 at reset. (5) bit 4: index register length flag (x) it determines whether each of index register x and index register y is used as a 16-bit register or an 8-bit register. that register is used as a 16-bit register when this flag is 0, and as an 8-bit register when it is 1. use the sep instruction to set this flag to 1, and use the clp instruction to clear it to 0. this flag is cleared to 0 at reset. note: when transferring data between registers which are different in bit length, the data is transferred with the length of the destination register, but except for the txa , tya , txb , tyb , and txs instructions. refer to 7700 family software manual for details. b15 b8 b7 b0 b1 b2 b3 b4 b5 b6 b14 b9 b10 b11 b12 b13 0nc z i d x m v 0 ipl 0 0 0
central processing unit (cpu) 2.1 central processing unit 2C8 7721 group users manual (6) bit 5: data length flag (m) it determines whether to use a data as a 16-bit unit or as an 8-bit unit. a data is treated as a 16- bit unit when this flag is 0, and as an 8-bit unit when it is 1. use the sem or sep instruction to set this flag to 1, and use the clm or clp instruction to clear it to 0. this flag is cleared to 0 at reset. note: when transferring data between registers which are different in bit length, the data is transferred with the length of the destination register, but except for the txa , tya , txb , tyb , and txs instructions. refer to 7700 family software manual for details. (7) bit 6: overflow flag (v) it is used when adding or subtracting with a word regarded as signed binary. when the data length flag (m) is 0, the overflow flag is set to 1 when the result of addition or subtraction exceeds the range between C32768 and +32767, and cleared to 0 in all other cases. when the data length flag (m) is 1, the overflow flag is set to 1 when the result of addition or subtraction exceeds the range between C128 and +127, and cleared to 0 in all other cases. the overflow flag is also set to 1 when a result of division exceeds the register length to be stored in a division instruction div . when the bvc or bvs instruction is executed, this flags contents determine whether the program causes a branch or not. use the sep instruction to set this flag to 1, and use the clv or clp instruction to clear it to 0. note: this flag is invalid in the decimal mode. (8) bit 7: negative flag (n) it is set to 1 when a result of arithmetic operation or data transfer is negative. (bit 15 of the result is 1 when the data length flag (m) is 0, or bit 7 of the result is 1 when the data length flag (m) is 1.) it is cleared to 0 in all other cases. when the bpl or bmi instruction is executed, this flag determines whether the program causes a branch or not. use the sep instruction to set this flag to 1, and use the clp instruction to clear it to 0. note: this flag is invalid in the decimal mode. (9) bits 10 to 8: processor interrupt priority level (ipl) these three bits can determine the processor interrupt priority level to one of levels 0 to 7. the interrupt is enabled when the interrupt priority level of a required interrupt, which is set in each interrupt control register, is higher than ipl. when an interrupt request is accepted, ipl is stored in the stack area, and ipl is replaced by the interrupt priority level of the accepted interrupt request. there are no instruction to directly set or clear the bits of ipl. ipl can be changed by storing the new ipl into the stack area and updating the processor status register with the pul or plp instruction. the contents of ipl is cleared to 000 2 at reset.
central processing unit (cpu) 7721 group users manual 2C9 2.2 bus interface unit 2.2 bus interface unit a bus interface unit (biu) is built-in between the central processing unit (cpu) and memory?i/o devices. bius function and operation are described below. when externally connecting devices, refer to chapter 3. connection with external devices. 2.2.1 overview transfer operation between the cpu and memory?i/o devices is always performed via the biu. the biu reads an instruction from the memory before the cpu executes it. when the cpu reads data from the memory?i/o device, the cpu first specifies the address from which data is read to the biu. the biu reads data from the specified address and passes it to the cpu. a when the cpu writes data to the memory?i/o device, the cpu first specifies the address to which data is written to the biu and write data. the biu writes the data to the specified address. ? to perform the above operations to a , the biu inputs and outputs the control signals, and control the bus. figure 2.2.1 shows the bus and bus interface unit (biu).
central processing unit (cpu) 7721 group users manual 2C10 2.2 bus interface unit fig. 2.2.1 bus and bus interface unit (biu) m37721 internal bus d 8 to d 15 central processing unit (cpu) sfr : special function register notes 1: the cpu bus, internal bus, and external bus are independent of one another. 2: refer to chapter 3. connection with external devices about control signals of the external bus. internal bus a 0 to a 23 external device internal control signal cpu bus internal bus internal bus d 0 to d 7 internal memory internal peripheral device (sfr) external bus a 0 to a 7 a 16 /d 0 to a 23 /d 7 control signals bus interface unit (biu) a 8 /d 8 to a 15 /d 15 bus conversion circuit
central processing unit (cpu) 7721 group users manual 2C11 2.2 bus interface unit 2.2.2 functions of bus interface unit (biu) the bus interface unit (biu) consists of four registers shown in figure 2.2.2. table 2.2.1 lists the functions of each register. program address register instruction queue buffer data address register data buffer pa da q 0 q 1 q 2 db h db l b23 b0 b0 b0 b0 b23 b15 b7 table 2.2.1 functions of each register functions indicates the storage address for the instruction which is next taken into the instruction queue buffer. temporarily stores the instruction which has been taken in. indicates the address for the data which is next read from or written to. temporarily stores the data which is read from the memory?i/o device by the biu or which is written to the memory?i/o device by the cpu. name program address register instruction queue buffer data address register data buffer fig. 2.2.2 register structure of bus interface unit (biu)
central processing unit (cpu) 7721 group users manual 2C12 2.2 bus interface unit the cpu and the bus send or receive data via biu because each operates based on different clocks (note) . the biu allows the cpu to operate at high speed without waiting for access to the memory i/o devices that require a long access time. the bius functions are described bellow. note: the cpu operates based on f cpu . the period of f cpu is normally the same as that of f . the internal __ bus operates based on the e signal. the period of the e signal is twice that of f at a minimum. (1) reading out instruction (instruction prefetch) when the cpu does not require to read or write data, that is, when the bus is not in use, the biu reads instructions from the memory and stores them in the instruction queue buffer. this is called instruction prefetch. the cpu reads instructions from the instruction queue buffer and executes them, so that the cpu can operate at high speed without waiting for access to the memory which requires a long access time. when the instruction queue buffer becomes empty or contains only 1 byte of an instruction, the biu performs instruction prefetch. the instruction queue buffer can store instructions up to 3 bytes. the contents of the instruction queue buffer is initialized when a branch or jump instruction is executed, and the biu reads a new instruction from the destination address. when instructions in the instruction queue buffer are insufficient for the cpus needs, the biu extends the pulse duration of clock f cpu in order to keep the cpu waiting until the biu fetches the required number of instructions or more. (2) reading data from memory?i/o device the cpu specifies the storage address of data to be read to the bius data address register, and requires data. the cpu waits until data is ready in the biu. the biu outputs the address received from the cpu onto the address bus, reads contents at the specified address, and takes it into the data buffer. the cpu continues processing, using data in the data buffer. however, if the biu uses the bus for instruction prefetch when the cpu requires to read data, the biu keeps the cpu waiting. (3) writing data to memory?i/o device the cpu specifies the address of data to be written to the bius data address register. then, the cpu writes data into the data buffer. the biu outputs the address received from the cpu onto the address bus and writes data in the data buffer into the specified address. the cpu advances to the next processing without waiting for completion of bius write operation. however, if the biu uses the bus for instruction prefetch when the cpu requires to write data, the biu keeps the cpu waiting. (4) bus control to perform the above operations (1) to (3), the biu inputs and outputs the control signals, and controls the address bus and the data bus. the cycle in which the biu controls the bus and accesses the memory?i/o device is called the bus cycle. refer to chapter 3. connection with external devices about the bus cycle at accessing the external devices. ?
central processing unit (cpu) 7721 group users manual 2C13 2.2 bus interface unit 2.2.3 operation of bus interface unit (biu) figure 2.2.3 shows the basic operating waveforms of the bus interface unit (biu). about signals which are input/output externally when accessing external devices, refer to chapter 3. connection with external devices. (1) when fetching instructions into the instruction queue buffer when the instruction which is next fetched is located at an even address, the biu fetches 2 bytes at a time with the timing of waveform (a). however, when accessing an external device which is connected with the 8-bit external data bus width (byte = h), only 1 byte of the instruction is fetched. when the instruction which is next fetched is located at an odd address, the biu fetches only 1 byte with the timing of waveform (a). the contents at the even address are not taken into the instruction queue buffer. (2) when reading or writing data to and from the memory?i/o device when accessing a 16-bit data which begins at an even address, waveform (a) is applied. the 16 bits of data are accessed at a time. when accessing a 16-bit data which begins at an odd address, waveform (b) is applied. the 16 bits of data are accessed separately in 2 operations, 8 bits at a time. invalid data is not fetched into the data buffer. a when accessing an 8-bit data at an even address, waveform (a) is applied. the data at the odd address is not fetched into the data buffer. ? when accessing an 8-bit data at an odd address, waveform (a) is applied. the data at the even address is not fetched into the data buffer. for instructions that are affected by the data length flag (m) and the index register length flag (x), operation or is applied when flag m or x = 0; operation a or ? is applied when flag m or x = 1.
central processing unit (cpu) 7721 group users manual 2C14 2.2 bus interface unit fig. 2.2.3 basic operating waveforms of bus interface unit (biu) address (a) data (even address) data (odd address) e internal address bus (a 0 to a 23 ) internal data bus (d 0 to d 7 ) internal data bus (d 8 to d 15 ) (b) address (odd address) address (even address) data (even address) data (odd address) invalid data invalid data internal address bus (a 0 to a 23 ) internal data bus (d 0 to d 7 ) internal data bus (d 8 to d 15 ) e
central processing unit (cpu) 7721 group users manual 2C15 2.3 access space 2.3 access space figure 2.3.1 shows the m37721s access space. by combination of the program counter (pc), which is 16 bits of structure, and the program bank register (pg), a 16-mbyte space from addresses 0 16 to ffffff 16 can be accessed. for details about access of an external area, refer to chapter 3. connection with external devices. the memory and i/o devices are assigned in the same access space. accordingly, it is possible to perform transfer and arithmetic operations using the same instructions without discrimination of the memory from i/o devices. fig. 2.3.1 m37721s access space : indicates the memory assignment of the internal areas. : indicates that nothing is assigned. note : memory assignment of internal ram area varies according to the type of microcomputer. this figure shows the case of the m37721s2bfp. refer to figure 2.4.1 for the m37721s1bfp. sfr : special function register 000000 16 000080 16 00ffff 16 010000 16 fe0000 16 ff0000 16 ffffff 16 sfr area internal ram area bank 0 16 sfr area 020000 16 00047f 16 00007f 16 bank 1 16 bank ff 16 bank fe 16 001fc0 16 001fff 16 : : : :
7721 group users manual central processing unit (cpu) 2C16 2.3.1 banks the access space is divided in units of 64 kbytes. this unit is called bank. the high-order 8 bits of address (24 bits) indicate a bank, which is specified by the program bank register (pg) or data bank register (dt). each bank can be accessed efficiently by using an addressing mode that uses the data bank register (dt). if the program counter (pc) overflows at a bank boundary, the contents of the program bank register (pg) is incremented by 1. if a borrow occurs in the program counter (pc) as a result of subtraction, the contents of the program bank register (pg) is decremented by 1. normally, accordingly, the user can program without concern for bank boundaries. sfr (special function register) and internal ram are assigned in bank 0 16 . for details, refer to section 2.4 memory assignment. 2.3.2 direct page a 256-byte space specified by the direct page register (dpr) is called direct page. a direct page is specified by setting the base address (the lowest address) of the area to be specified as a direct page into the direct page register (dpr). by using a direct page addressing mode, a direct page can be accessed with less instruction cycles than otherwise. note: refer also to section 2.1 central processing unit. 2.3 access space
central processing unit (cpu) 7721 group users manual 2C17 2.4 memory assignment 2.4 memory assignment this section describes the internal areas memory assignment. for more information about the external area, refer also to chapter 3. connection with external devices. figure 2.4.1 shows the memory assignment. 2.4.1 memory assignment in internal area sfr (special function register) and internal ram are assigned in the internal area. (1) sfr area the registers for setting internal peripheral devices are assigned at addresses 0 16 to 7f 16 and 1fc0 16 to 1fff 16 . this area is called sfr. figures 2.4.2 and 2.4.3 show the sfr areas memory assignment. for each register in the sfr area, refer to each functional description in this manual. for the state of the sfr area immediately after reset, refer to section 4.1.2 state of cpu, sfr area, and internal ram area. (2) internal ram area the m37721s2bfp ( note 1 ) assigns the 1024-byte static ram at addresses 80 16 to 47f 16 . 512 bytes of that can be selected either it is used as the internal ram or it is used as the external area. (note 2) the internal ram area is used as a stack area (note 3) , as well as an area to store data. accordingly, note that set the nesting depth of a subroutine and multiple interrupts level not to destroy the necessary data. notes 1: the m37721s1bfp assigns the 512-byte static ram at addresses 80 16 to 27f 16 . 2: the internal ram area becomes 512 bytes after reset because the internal ram area select bit is 0. 3: either bank 0 16 or bank ff 16 can be selected as the stack area by the stack bank select bit (bit 7 at address 5e 16 ). figure 2.4.4 shows the structure of the processor mode registers 0, 1.
7721 group users manual central processing unit (cpu) 2C18 2.4.2 external area table 2.4.1 lists the external area. when connecting the external device, follow the procedure described bellow: ?connect the rom to addresses ffce 16 to ffff 16 because they are interrupt vector table. ?stack area can be assigned to bank 0 16 or bank ff 16 . select the stack area by the stack bank select bit (bit 7 at address 5e 16 ). (refer to figure 2.4.4. ) ?when using the dram controller, dram area can be selected from address ffffff 16 toward the low- order address in a unit of 1 mbytes. (refer to chapter 14. dram controller. ) in the case connecting an external device to the area where overlaps the internal area, when reading out the overlapping area, the central processing unit (cpu) take in data of the internal area and do not take in data of the external area. when writing to the overlapping area, data is written to the internal area. the signal is output to the external at the same timing when data is written to the internal area. table 2.4.1 external area 2.4 memory assignment 0 m37721s2bfp type name internal ram area select bit external area m37721s1bfp 0 (fix this bit to 0.) 2 16 C9 16 280 16 C1fbf 16 2000 16 Cffffff 16 1 2 16 C9 16 480 16 C1fbf 16 2000 16 Cffffff 16 internal ram area select bit : bit 1 at address 5f 16
central processing unit (cpu) 7721 group users manual 2C19 2.4 memory assignment fig. 2.4.1 memory assignment aaaaa a aaa a a aaa a a aaa a a aaa a a aaa a a aaa a a aaa a a aaa a a aaa a a aaa a aaaaa notes 1: addresses 2 16 to 9 16 are the external memory area. 2: for the m37721s1bfp, fix the internal ram area select bit to ?. 3: dbc is an interrupt only for debugging; do not use this interrupt. timer a0 l h l h l h l h l h l h l h h l h timer a4 l h l timer a3 h timer a2 l h timer a1 l h l h l h l h l h l h timer b2 l h timer b1 l h timer b0 l h a-d conversion uart1 transmit uart1 receive uart0 transmit uart0 receive int 2 int 1 int 0 watchdog timer dbc (note 3) brk instruction zero divide reset 00ffd6 16 00ffd8 16 00ffda 16 00ffdc 16 00ffde 16 00ffe0 16 00ffe2 16 00ffe8 16 00ffec 16 00ffe4 16 00ffe6 16 00ffea 16 00ffee 16 00fff0 16 00fff2 16 00fff4 16 00fff6 16 00fff8 16 00fffa 16 00fffc 16 00fffe 16 interrupt vector table l 00007f 16 000000 16 000080 16 ffffff 16 sfr area (note 1) aaaaa a aaa a aaaaa 001fc0 16 00047f 16 aa : the internal memory is not assigned. l h l h l h l h dma3 dma2 dma1 dma0 00ffce 16 00ffd0 16 00ffd2 16 00ffd4 16 m37721s2bfp m37721s1bfp 00027f 16 internal ram area (512 bytes) (512 bytes) sfr area 001fff 16 00ffce 16 00ffff 16 aaaa a aa a a aa a a aa a a aa a a aa a a aa a a aa a a aa a a aa a a aa a aaaa sfr area (note 1) aaaa a aa a a aa a a aa a aaaa internal ram area (512 bytes) (note 2) sfr area case of internal ram area select bit = ? case of internal ram area select bit = ? sfr area: refer to ?igure 2.4.2 and ?igure 2.4.3.
7721 group users manual central processing unit (cpu) 2C20 2.4 memory assignment fig. 2.4.2 sfr areas memory map (1) 000000 16 000001 16 000002 16 000003 16 000004 16 000005 16 000006 16 000007 16 000008 16 000009 16 000010 16 000011 16 000012 16 000013 16 000014 16 000015 16 000016 16 000017 16 000018 16 000019 16 00001a 16 00001b 16 00001c 16 00001d 16 00001e 16 00001f 16 000020 16 000021 16 000022 16 000023 16 000024 16 000025 16 000026 16 000027 16 000028 16 000029 16 00002a 16 00002b 16 00002c 16 00002d 16 00002e 16 00002f 16 000030 16 000031 16 000032 16 000033 16 000034 16 000035 16 000036 16 000037 16 000038 16 000039 16 00003a 16 00003b 16 00003c 16 00003d 16 00003e 16 00003f 16 00000b 16 00000c 16 00000d 16 00000e 16 00000f 16 00000a 16 address 000050 16 000051 16 000052 16 000053 16 000054 16 000055 16 000056 16 000057 16 000058 16 000059 16 00005a 16 00005b 16 00005c 16 00005d 16 00005e 16 00005f 16 000060 16 000061 16 000062 16 000063 16 000064 16 000065 16 000066 16 000067 16 000068 16 000069 16 00006a 16 00006b 16 00006c 16 00006d 16 00006e 16 00006f 16 000070 16 000071 16 000072 16 000073 16 000074 16 000075 16 000076 16 000077 16 000078 16 000079 16 00007a 16 00007b 16 00007c 16 00007d 16 00007e 16 00007f 16 address 00004e 16 00004f 16 00004c 16 00004d 16 00004a 16 00004b 16 000048 16 000049 16 000046 16 000047 16 000044 16 000045 16 000042 16 000043 16 000040 16 000041 16 port p8 direction register timer a1 register timer a4 register timer a2 register timer a3 register timer b0 register timer b1 register timer b2 register count start register one-shot start register up-down register timer a0 register timer a0 mode register timer a1 mode register timer a2 mode register timer a3 mode register timer a4 mode register timer b0 mode register timer b1 mode register timer b2 mode register processor mode register 0 watchdog timer register watchdog timer frequency select register a-d conversion interrupt control register uart0 receive interrupt control register uart1 receive interrupt control register timer a0 interrupt control register timer a1 interrupt control register timer a2 interrupt control register timer a3 interrupt control register timer a4 interrupt control register timer b0 interrupt control register timer b1 interrupt control register timer b2 interrupt control register port p4 register port p5 register port p4 direction register port p5 direction register port p6 register port p7 register port p6 direction register port p7 direction register port p8 register a-d control register uart0 transmit/receive mode register uart0 baud rate register (brg0) uart0 transmit/receive control register 0 uart0 transmit/receive control register 1 uart0 transmit buffer register uart1 transmit/receive control register 0 uart1 transmit/receive mode register uart1 baud rate register (brg1) uart1 transmit/receive control register 1 uart0 receive buffer register uart1 transmit buffer register uart1 receive buffer register a-d sweep pin select register a-d register 0 a-d register 1 a-d register 2 a-d register 3 a-d register 4 a-d register 5 uart0 transmit interrupt control register uart1 transmit interrupt control register int 0 interrupt control register int 1 interrupt control register int 2 interrupt control register a-d register 6 a-d register 7 processor mode register 1 port p9 register port p9 direction register port p10 register pulse output data register 0 port p10 direction register pulse output data register 1 real-time output control register dram control register refresh timer dmac control register l dmac control register h dma0 interrupt control register dma1 interrupt control register dma2 interrupt control register dma3 interrupt control register
central processing unit (cpu) 7721 group users manual 2C21 2.4 memory assignment fig. 2.4.3 sfr areas memory map (2) 001fc0 16 001fc1 16 001fc2 16 001fc3 16 001fc4 16 001fc5 16 001fc6 16 001fc7 16 001fc8 16 001fc9 16 001fd0 16 001fd1 16 001fd2 16 001fd3 16 001fd4 16 001fd5 16 001fd6 16 001fd7 16 001fd8 16 001fd9 16 001fda 16 001fdb 16 001fdc 16 001fdd 16 001fde 16 001fdf 16 001fe0 16 001fe1 16 001fe2 16 001fe3 16 001fe4 16 001fe5 16 001fe6 16 001fe7 16 001fe8 16 001fe9 16 001fea 16 001feb 16 001fec 16 001fed 16 001fee 16 001fef 16 001ff0 16 001ff1 16 001ff2 16 001ff3 16 001ff4 16 001ff5 16 001ff6 16 001ff7 16 001ff8 16 001ff9 16 001ffa 16 001ffb 16 001ffc 16 001ffd 16 001ffe 16 001fff 16 001fcb 16 001fcc 16 001fcd 16 001fce 16 001fcf 16 001fca 16 address source address register 0 l m h l m h l m h l m h l m h destination address register 0 transfer counter register 0 dma0 mode register l dma0 mode register h dma0 control register source address register 1 destination address register 1 l m h l m h l m h l m h l m h l m h l m h transfer counter register 1 dma1 mode register l dma1 mode register h dma1 control register source address register 2 destination address register 2 transfer counter register 2 dma2 mode register l dma2 mode register h dma2 control register source address register 3 destination address register 3 transfer counter register 3 dma3 mode register l dma3 mode register h dma3 control register
7721 group users manual central processing unit (cpu) 2C22 2.4 memory assignment bit bit name functions at reset rw 0 1 3 4 5 6 7 fix this bit to 0. software reset bit interrupt priority detection time select bits stack bank select bit 0 0 0 the microcomputer is reset by writing 1 to this bit. the value is 0 at reading. 0 0 : 7 cycles of 0 1 : 4 cycles of 1 0 : 2 cycles of 1 1 : do not select. 0 : bank 0 16 1 : bank ff 16 0 1 b5 b4 processor mode register 0 (address 5e 16 ) b1 b0 b2 b3 b4 b5 b6 b7 0 rw C wo 0 rw 0 rw fix this bit to 0. rw rw 0 nothing is assigned. the value is 1 at reading. 2 0 wait bit rw 0 : software wait is inserted when accessing external area. 1 : no software wait is inserted when accessing external area. b7 b6 b5 b4 b3 b2 b1 b0 processor mode register 1 (address 5f 16 ) bit 7 to 2 1 0 bit name at reset rw functions notes 1: for the m37721s1bfp, fix bit 1 to 0. 2: for the m37721s2bfp, set bit 1 before setting the stack pointer. nothing is assigned. C undefined internal ram area select bit (notes 1, 2) 0 : 512 bytes (addresses 80 16 to 27f 16 ) 1 : 1024 bytes (addresses 80 16 to 47f 16 ) nothing is assigned. rw 0 C undefined : bits 0 to 6 are not used for the memory assignment. fig. 2.4.4 structure of processor mode registers 0, 1
central processing unit (cpu) 7721 group users manual 2C23 2.5 bus access right 2.5 bus access right the m37721s bus is used for dramc, hold function, and dmac besides cpu. when the bus requests of two or more source are detected at the same timing, the high est bus access priority levels get the access right. the bus priority levels are fixed by hardware. additionally the bus use state is output from the status signal output pins st0 and st1. table 2.5.1 lists the bus use prior ity levels and the status signals depending on the bus use state. table 2.5.1 bus use priority levels and status signals depen ding on bus use state status signal st1 0 0 1 1 st0 0 1 0 1 bus use priority levels 1 (highest) 2 3 4 (lowest) bus use state dram refresh hold dmac cpu (including the term that cpu does not use the bus during calculation etc.) for details, refer to section 13.2.1 bus access control circuit and chapter for each peripheral devices.
7721 group users manual central processing unit (cpu) 2C24 2.5 bus access right memorandum
chapter 3 connection with external devices 3.1 signals required for accessing external devices 3.2 software wait 3.3 ready function 3.4 hold function [precautions for hold function]
connection with external devices 3.1 signals required for accessing external devices 7721 group users manual 3C2 3.1 signals required for accessing external devices the functions and operations of the signals which are required for accessing the external devices are described below. when connecting an external device that requires long access time, refer to sections 3.2 software wait, 3.3 ready function, and 3.4 hold function, as well as this section. when the external dram is controlled by using dram controller, refer to chapter 14. dram controller. 3.1.1 descriptions of signals figure 3.1.1 shows the pin configurations when the external data bus width is 16 bits and 8 bits. (1) external buses (a 0 Ca 7 , a 8 /d 8 Ca 15 /d 15 , a 16 /d 0 Ca 23 /d 7 ) the external area is specified by the address (a 0 Ca 23 ) output. the a 8 Ca 23 pins of the external address bus and the d 0 Cd 15 pins of the external data bus are assigned to the same pins. when the byte pin level, described later, is l (external data bus width is 16 bits), the a 8 /d 8 C a 15 /d 15 and a 16 /d 0 Ca 23 /d 7 pins perform address output and data input/output with time-sharing. when the byte pin level is h (external data bus width is 8 bits), the a 16 /d 0 Ca 23 /d 7 pins perform address output and data input/output with time-sharing, and the a 8 Ca 15 pins output the address. (2) external data bus width switching signal (byte pin level) this signal is used to select the external data bus width from 8 bits and 16 bits. the width is 16 bits when the level is l, and 8 bits when the level is h. fix this signal to either h or l level. this signal is valid only for the external area. (when accessing the internal area, the data bus width is always 16 bits.) (3) __ enable signal (e) this signal becomes l level while reading or writing data from and to the data bus. (refer to table 3.1.1. ) (4) __ read/write signal (r/w) this signal indicates the state of the data bus. this signal becomes l level while writing data to __ __ the data bus. table 3.1.1 lists the state of the data bus indicated with the e and r/w signals. _ table 3.1.1 state of data bus indicated with e and __ r/w signals __ e h l __ r/w h l h l state of data bus not used read data write data
connection with external devices 7721 group users manual 3C3 3.1 signals required for accessing external devices fig. 3.1.1 pin configurations when external data bus width is 16 bits and 8 bits (top view) p8 7 /t x d 1 p9 0 /dmaack0 p9 1 /dmareq0 p9 2 /dmaack1 p9 3 /dmareq1 p9 4 /dmaack2 p9 5 /dmareq2 p9 6 /dmaack3 p9 7 /dmareq3 a 0 /ma 0 a 1 /ma 1 a 2 /ma 2 a 3 /ma 3 a 4 /ma 4 a 5 /ma 5 a 6 /ma 6 a 7 /ma 7 a 8 /d 8 a 9 /d 9 a 10 /d 10 a 11 /d 11 a 12 /d 12 a 13 /d 13 a 14 /d 14 a 15 /d 15 a 16 /d 0 a 17 /d 1 a 18 /d 2 a 19 /d 3 a 20 /d 4 p8 6 /r x d 1 p8 5 /clk 1 p8 4 /cts 1 /rts 1 p8 3 /t x d 0 p8 2 /r x d 0 p8 1 /clk 0 p8 0 /cts 0 /rts 0 v cc av cc v ref av ss v ss p7 7 /an 7 /ad trg p7 6 /an 6 p7 5 /an 5 p7 4 /an 4 p7 3 /an 3 p7 2 /an 2 p7 1 /an 1 p7 0 /an 0 p6 7 /rtp1 3 p6 6 /rtp1 2 p6 5 /rtp1 1 p6 4 /rtp1 0 p6 3 /rtp0 3 p6 2 /rtp0 2 p6 1 /rtp0 1 p6 0 /rtp0 0 p5 7 /tb1 in p5 6 /tb0 in p5 5 /ta4 in p5 4 /ta4 out p5 3 /ta3 in p5 2 /ta3 out p5 1 /ta2 in p5 0 /ta2 out p10 7 /ma 9 p10 6 /ma 8 p10 5 /ras p10 4 /cas p10 3 /tc p10 2 /int 2 p10 1 /int 1 p10 0 /int 0 p4 7 p4 6 p4 5 p4 4 p4 3 1 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 1 4 3 2 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 a 21 /d 5 a 22 /d 6 a 23 /d 7 r/w bhe ble ale st0 st1 v cc v ss e x out x in reset reset out cnv ss byte hold rdy 35 37 36 38 44 39 40 41 42 43 45 46 47 48 49 50 31 32 33 34 96 94 95 93 87 92 91 90 89 88 86 85 84 83 82 81 100 99 98 97 m37721s2bfp 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 35 37 36 38 44 39 40 41 42 43 45 46 47 48 49 50 31 32 33 34 96 94 95 93 87 92 91 90 89 88 86 85 84 83 82 81 100 99 98 97 1 4 3 2 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 p8 6 /r x d 1 p8 5 /clk 1 p8 4 /cts 1 /rts 1 p8 3 /t x d 0 p8 2 /r x d 0 p8 1 /clk 0 p8 0 /cts 0 /rts 0 v cc av cc v ref av ss v ss p7 7 /an 7 /ad trg p7 6 /an 6 p7 5 /an 5 p7 4 /an 4 p7 3 /an 3 p7 2 /an 2 p7 1 /an 1 p7 0 /an 0 p6 7 /rtp1 3 p6 6 /rtp1 2 p6 5 /rtp1 1 p6 4 /rtp1 0 p6 3 /rtp0 3 p6 2 /rtp0 2 p6 1 /rtp0 1 p6 0 /rtp0 0 p5 7 /tb1 in p5 6 /tb0 in p5 5 /ta4 in p5 4 /ta4 out p5 3 /ta3 in p5 2 /ta3 out p5 1 /ta2 in p5 0 /ta2 out p10 7 /ma 9 p10 6 /ma 8 p10 5 /ras p10 4 /cas p10 3 /tc p10 2 /int 2 p10 1 /int 1 p10 0 /int 0 p4 7 p4 6 p4 5 p4 4 p4 3 1 a 21 /d 5 a 22 /d 6 a 23 /d 7 r/w bhe ble ale st0 st1 v cc v ss e x out x in reset reset out cnv ss byte hold rdy m37721s2bfp l external data bus width = 16 bits (byte = l) : external address bus, external data bus, bus control signal l external data bus width = 8 bits (byte = h) note: for the dram control signals, refer to chapter 14. dram controller. : external address bus, external data bus, bus control signal p8 7 /t x d 1 p9 0 /dmaack0 p9 1 /dmareq0 p9 2 /dmaack1 p9 3 /dmareq1 p9 4 /dmaack2 p9 5 /dmareq2 p9 6 /dmaack3 p9 7 /dmareq3 a 0 /ma 0 a 1 /ma 1 a 2 /ma 2 a 3 /ma 3 a 4 /ma 4 a 5 /ma 5 a 6 /ma 6 a 7 /ma 7 a 8 a 9 a 10 a 11 a 12 a 13 a 14 a 15 a 16 /d 0 a 17 /d 1 a 18 /d 2 a 19 /d 3 a 20 /d 4
connection with external devices 3.1 signals required for accessing external devices 7721 group users manual 3C4 (5) ____ ____ byte low enable signal (ble), byte high enable signal (bhe) ____ the ble signal indicates the access to an even address. this signal becomes l level when accessing only an even address or when simultaneously accessing both an even and an odd address. ____ the bhe signal indicates the access to an odd address. this signal becomes l level when accessing only an odd address or when simultaneously accessing both an odd and an even address. these signals are used to connect memories or i/o devices of which data bus width is 8 bits when ____ ____ the external data bus width is 16 bits. table 3.1.2 lists levels of the ble and bhe signals and access addresses. ____ ____ table 3.1.2 levels of ble and bhe signals and access addresses even and odd addresses (simultaneous 2-byte access) l l even address (1-byte access) l h odd address (1-byte access) h l access address ____ ble ____ bhe (6) address latch enable signal (ale) this signal is used to latch the address from the multiplexed signal, which consists of the address and data. (this multiplexed signal is input to or output from the a 8 /d 8 Ca 15 /d 15 and a 16 /d 0 Ca 23 /d 7 pins.) when the ale signal is h, latch the address and simultaneously output the addresses. when this signal is l, retain the latched address. (7) ____ ready function-related signal (rdy) this is the signal to use ready function (refer to section 3.3 ready function. ) (8) _____ hold function-related signal (hold) this is the signal to use hold function. (refer to section 3.4 hold function. ) (9) status signals (st0, st1) these signals indicate the bus use status. table 3.1.3 lists the bus use status indicated by the st0 and st1 signals. (10) clock f 1 this signal has the same period as f . table 3.1.3 bus use status indicated by st0 and st1 signals bus use status dram refresh hold dma cpu st1 l l h h st0 l h l h
connection with external devices 7721 group users manual 3C5 3.1 signals required for accessing external devices 3.1.2 operation of bus interface unit (biu) figures 3.1.2 and 3.1.3 show the examples of operating waveforms of the signals input from or output to the external when accessing external devices. the following explains these waveforms, being compared with the basic operating waveform. (refer to section 2.2.3 operation of bus interface unit (biu). ) (1) when fetching instructions into instruction queue buffer when the instruction which is next fetched is located at an even address when the external data bus width is 16 bits, the biu fetches 2 bytes of the instruction at a time with waveform (a). when the external data bus width is 8 bits, the biu fetches only 1 byte of the instruction with the first half of waveform (e). when the instruction which is next fetched is located at an odd address when the external data bus width is 16 bits, the biu fetches only 1 byte of the instruction with waveform (d). when the external data bus width is 8 bits, the biu fetches only 1 byte of the instruction with the first half of waveform (f). when a branch to an odd address is caused by a branch instruction etc. with the 16-bit external data bus width, the biu first fetches 1 byte of the instruction with waveform (d), and after that, fetches instructions in a unit of 2 bytes with waveform (a). (2) when reading or writing data from and to memories or i/o devices when accessing 16-bit data which begins at an even address, waveform (a) or (e) is applied. when accessing 16-bit data which begins at an odd address, waveform (b) or (f) is applied. a when accessing 8-bit data at an even address, waveform (c) or the first half of (e) is applied. ? when accessing 8-bit data at an odd address, waveform (d) or the first half of (f) is applied. for instructions that are affected by the data length flag (m) and the index register length flag (x), operation or is applied when flag m or x = 0; operation a or ? is applied when flag m or x = 1. the setup of flags m and x and the selection of the external data bus width do not affect each other.
connection with external devices 3.1 signals required for accessing external devices 7721 group users manual 3C6 fig. 3.1.2 examples of operating waveforms of signals input from or output to the external (1) a 0 to a 7 a 16 /d 0 to a 23 /d 7 e ale bhe a 8 /d 8 to a 15 /d 15 a 0 to a 7 a 16 /d 0 to a 23 /d 7 e ale bhe a 8 /d 8 to a 15 /d 15 a 0 to a 7 a 8 /d 8 to a 15 /d 15 bhe e ale a 16 /d 0 to a 23 /d 7 a 0 to a 7 a 8 /d 8 to a 15 /d 15 bhe e ale a 16 /d 0 to a 23 /d 7 (a) access beginning at even address <16-bit data access> l external data bus width = 16 bits (byte = ?? address data(odd) data(even) address address (b) access beginning at odd address address address address data(odd) address address address data(even) <8-bit data access> (c) access to even address address address data(even) address address (d) access to odd address data(odd) address address ble ble ble ble
connection with external devices 7721 group users manual 3C7 3.1 signals required for accessing external devices fig. 3.1.3 examples of operating waveforms of signals input from or output to the external (2) e ale a 0 to a 7 bhe a 8 to a 15 a 16 /d 0 to a 23 /d 7 e ale a 0 to a 7 bhe a 8 to a 15 a 16 /d 0 to a 23 /d 7 l external data bus width = 8 bits (byte = ?? <8/16-bit data access> (e) access beginning at even address address address data data 8-bit data access 16-bit data access address address address address data address data address address address address address 8-bit data access 16-bit data access (f) access beginning at odd address note: when accessing 16-bit data, 2 times of access are performed; the low-order 8 bits are accessed first, and after that, the high- order 8 bits are accessed. ble ble
connection with external devices 3.2 software wait 7721 group user's manual 3C8 3.2 software wait software wait provides a function to facilitate access to external devices that require long access time. to select the software wait, use the wait bit (bit 2 at address 5e 16 ). figure 3.2.1 shows the structure of processor mode register 0 (address 5e 16 ). figure 3.2.2 shows examples of bus timing when software wait is used. software wait is valid only for the eternal area. the internal area is always accessed with no wait. fig. 3.2.1 structure of processor mode register 0 bit bit name functions at reset rw 0 1 3 4 5 6 7 fix this bit to 0. software reset bit interrupt priority detection time select bits stack bank select bit 0 0 0 the microcomputer is reset by writing 1 to this bit. the value is 0 at reading. 0 0 : 7 cycles of 0 1 : 4 cycles of 1 0 : 2 cycles of 1 1 : do not select. 0 : bank 0 16 1 : bank ff 16 0 1 b5 b4 processor mode register 0 (address 5e 16 ) b1 b0 b2 b3 b4 b5 b6 b7 0 rw C wo 0 rw 0 rw fix this bit to 0. rw rw 0 nothing is assigned. the value is 1 at reading. 2 0 wait bit rw 0 : software wait is inserted when accessing external area. 1 : no software wait is inserted when accessing external area. : bits 0, 1, and 3 to 6 are not used for accessing external area.
connection with external devices 7721 group user's manual 3C9 3.2 software wait fig. 3.2.2 examples of bus timing when software wait is used (byte = l) clock 1 a 0 a 7 a 8 /d 8 a 15 /d 15, a 16 /d 0 a 23 /d 7 e ale address 1 bus cycle (note) note: when the external data bus is 8 bits wide (byte = h), a 8 /d 8 to a 15 /d 15 operate with the same bus timing as a 0 to a 7 . address data data address address l internal areas are always accessed with this waveform. clock 1 a 0 a 7 a 8 /d 8 a 15 /d 15, a 16 /d 0 a 23 /d 7 e ale (note) 1 bus cycle address address data data address address
connection with external devices 3.3 ready function 7721 group users manual 3C10 3.3 ready function ready function provides the function to facilitate access to external devices that require long access time. ____ the microcomputer enters ready state by input of l level to the rdy pin and retains this state while the ____ level of the rdy pin is at l. table 3.3.1 lists the microcomputers state in ready state. in ready state, the oscillators oscillation does not stop. accordingly, the internal peripheral devices can operate. ready function is valid for the internal and external areas. table 3.3.1 microcomputers state in ready state item oscillation f cpu , f ___ pins a 0 to a 7 , a 8 /d 8 to a 15 /d 15 , a 16 /d 0 to a 23 /d 7 , e, r/w, ____ ____ bhe, ble, st0, st1, ale pins p4 3 to p4 7 , p5 to p10 (note) pin f 1 watchdog timer state operating stopped at l retain the state when ready request was accepted. outputs clock f 1. operating note: this applies when this functions as a programmable i/o port.
connection with external devices 7721 group users manual 3C11 3.3 ready function 3.3.1 operation description ____ the input level of the rdy pin is judged at the falling edge of clock f 1 . when l level is detected at this point, the microcomputer enters ready state. (this is called acceptance of ready request.) ____ in ready state, the input level of the rdy pin is judged at every falling edge of clock f 1 . when h level is detected at this point, the microcomputer terminates ready state at the next rising edge of clock f 1 . figure 3.3.1 shows timing of acceptance of ready request and termination of ready state. refer also to section 16.1 memory connection for usage of ready function. a the l level which is input to th e rdy pin is accepted, so that e stops at l level for 1 cycle of clock 1 (indicated by ), and cpu stops at l level. the l level which is input to the rdy pin is not accepted, however cpu stops at l level. clock 1 cpu rdy ale ? bus not in use the l level which is input to the rdy pin is accepted, so that e stops at h level for 1 cycle of clock 1 (indicated by ), and cpu stops at l level. rdy ale a ?? cpu e e rdy pin input level sampling timing ? a bus in use ? ready state is terminated. ? the l level which is input to the rdy pin is not accepted because it is sampled immediately before wait by software wait (indicated by ), however cpu stops at l level. clock 1 rdy pin input level sampling timing bus in use fig. 3.3.1 timing of acceptance of ready request and termination of ready state
connection with external devices 3.4 hold function 7721 group users manual 3C12 3.4 hold function when composing the external circuit which accesses the bus without using the central processing unit (cpu), hold function is used to generate a timing for transferring the right to use the bus from the cpu to the external circuit. _____ the microcomputer enters hold state by input of l level to the hold pin and retains this state while the _____ level of the hold pin is at l. table 3.4.1 lists the microcomputers state in hold state. in hold state, the oscillation of the oscillator does not stop. accordingly, the internal peripheral devices can operate. however, watchdog timer stops operating. table 3.4.1 microcomputers state in hold state item oscillation f f cpu _ e __ pins a 0 to a 7 , a 8 /d 8 to a 15 /d 15 , a 16 /d 0 to a 23 /d 7 , r/w, ___ ____ bhe, ble pins ale, st1 pin st0 pin f 1 pins p4 3 to p4 7 , p5 to p10 (note) watchdog timer state operating operating stopped at l stopped at h floating output l level. outputs h level. outputs clock f 1 . retain the state when hold request was accepted. stopped note: this applies when this functions as a programmable i/o port. 3.4.1 operation description _____ judgment of the hold pin input level is performed at every falling edge of f 1 . when l level is detected at judgment of the input level, bus request (hold) becomes 1, when h level is detected, bus request (hold) becomes 0. bus request (hold) is sampled within a period when the bus request sampling signal is 1 and bus request is accepted when there is no bus request (dramc). (this is called acceptance of hold request.) for bus request, refer to section 13.2.1 bus access control circuit. when hold request is accepted, f cpu stops at l level at the next rising edge of f and the st0 pins level becomes h, the st1 pins level becomes l. when 1 cycle of f has passed after the levels of the st0 __ ____ ____ and st1 pins are changed, the r/w, bhe, ble pins and the external bus enter the floating state. _____ in hold state, when the hold pins input level becomes h, the st0 and st1 pins levels are changed at the next rising edge of f . when 1 cycle of f has passed after the levels of the st0 and st1 pins are changed, the microcomputer terminates hold state. figures 3.4.1 to 3.4.3 show timing of acceptance of hold request and termination of hold state. note: f has the same polarity and the same frequency as clock f 1 . however, f stops by acceptance of ready request, or executing the stp or wit instruction. accordingly, _____ judgment of the input level of the hold pin is not performed during ready state.
connection with external devices 7721 group users manual 3C13 3.4 hold function fig. 3.4.1 timing of acceptance of hold request and termination of hold state (1) r/w hold ale floating st0 e address b address a bus request (hold) st1 bus request sampling transfer of right to use bus l state when inputting l level to hold pin external data bus data length external data bus width 16 8, 16 unused 8, 16 8 clock 1 (note 1) external address bus ble, bhe external address bus / external data bus bus not in use hold state bus in use this is the period in which the bus is not used, so that not a new address but the address which was output immediately before is output again. notes 1: clock 1 has the same polarity and the same frequency as . timing of signals to be input from or output to the external is ordained on the basis of clock 1 . 2: bus request (hold) and bus request sampling are internal signals. floating floating (note 2) (note 2) transfer of right to use bus
connection with external devices 3.4 hold function 7721 group users manual 3C14 fig. 3.4.2 timing of acceptance of hold request and termination of hold state (2) r/w st1 hold ale st0 e bus request (hold) bus request sampling l state when inputting l level to hold pin 8 16 8, 16 16 (access beginning at even address) external data bus data length external data bus width used clock 1 (note 2) floating address a address a floating floating data address b external address bus external address bus / external data bus ble, bhe bus in use transfer of right to use bus hold state bus in use when a hold request is accepted, not a new address but the address which was output immediately before is output again. notes 1: the above diagram shows the case of no wait. 2: clock 1 has the same polarity and the same frequency as . timing of signals to be input from or output to the external is ordained on the basis of clock 1 . 3 : bus request (hold) and bus request sampling are internal signals. (note 3) (note 3) transfer of right to use bus
connection with external devices 7721 group users manual 3C15 3.4 hold function data r/w hold ale floating e address b address a when a hold request is accepted, not a new address but the address which was output immediately before is output again. st1 st0 bus request (hold) bus request sampling transfer of right to use bus l state when inputting l level to hold pin 16 8 16 (access beginning at odd address) used external data bus data length external data bus width clock 1 (note 2) floating address a + 1 data external address bus / external data bus external address bus ble, bhe bus in use hold state bus in use notes 1 : the above diagram shows the case of 2- access in low-speed running. 2 : clock 1 has the same polarity and the same frequency as . timing of signals to be input from or output to the external is ordained on the basis of clock 1 . 3 : bus request (hold) and bus request sampling are internal signals. floating (note 3) (note 3) transfer of right to use bus fig. 3.4.3 timing of acceptance of hold request and termination of hold state (3)
connection with external devices 3.4 hold function 7721 group users manual 3C16 [precautions for hold function] when a dram refresh request occurs in hold state, dram refresh is performed immediately because the bus use priority level of dram refresh is higher than that of hold function.
chapter 4 reset 4.1 hardware reset 4.2 software reset
reset 7721 group users manual 4C2 4.1 hardware reset when the power source voltage satisfies the microcomputers recommended operating conditions, the ______ microcomputer is reset by supplying l level to the reset pin. this is called a hardware reset. figure 4.1.1 shows an example of hardware reset timing. 4.1 hardware reset fig. 4.1.1 example of hardware reset timing the following explains how the microcomputer operates in periods to ? above. ______ after supplying l level to the reset pin, the microcomputer initializes pins within a period of several ten ns. (refer to table 4.1.1. ) ______ ______ while the reset pin is l level and within a period of 4 to 5 cycles of f after the reset pin goes from l to h, the microcomputer initializes the central processing unit (cpu) and sfr area. at this time, the contents of the internal ram area become undefined (except when stop or wait mode is terminated). (refer to figures 4.1.3 to 4.1.9. ) a after , the microcomputer performs internal processing sequence after reset. (refer to figure 4.1.10. ) ? the microcomputer executes a program beginning with the address set into the reset vector addresses (fffe 16 and ffff 16 ). reset program is executed. a? 2 s or more internal processing sequence after reset note: when the clock is stably supplied. (refer to section 4.1.4 time supplying l level to reset pin. ) 4 to 5 cycles of
7721 group users manual reset 4C3 4.1 hardware reset 4.1.1 pin state ______ table 4.1.1 lists the microcomputers pin state while reset pin is at l level. figure 4.1.2 shows the ________ reset out output retaining timing. ______ table 4.1.1 pin state while reset pin is at l level pin state outputs h or l level. outputs h level. outputs l level. outputs f 1 . floating. pin (bus, port) name ____ ____ a 0 /ma 0 Ca 7 /ma 7 , a 8 /d 8 Ca 15 /d 15 , a 16 /d 0 Ca 23 /d 7 , bhe, ble __ _ r/w, e, st0, st1 _________ ale, reset out f 1 _____ ____ hold, rdy, p4 3 Cp4 7 , p5Cp10 ________ fig. 4.1.2 reset out output retaining timing 1 reset reset out when reset pin input level goes from l to h in this period 3.5 cycles of 1
reset 7721 group users manual 4C4 4.1 hardware reset 4.1.2 state of cpu, sfr area, and internal ram area figure 4.1.3 shows the state of the cpu registers immediately after reset. figures 4.1.4 to 4.1.9 show the state of the sfr and internal ram areas immediately after reset. fig. 4.1.3 state of cpu registers immediately after reset 0 1 ? : ??immediately after reset. : ??immediately after reset. : undefined immediately after reset. data bank register (dt) 00 16 b7 b0 program bank register (pg) 00 16 b7 b0 program counter (pc) contents at address fffe 16 contents at address ffff 16 b7 b0 b15 b8 direct page register (dpr) 00 16 b7 b0 00 16 b15 b8 processor status register (ps) 0 0 0 0 00 0 0 00 0 1 b7 b0 b15 b8 nv mxd izc ipl ? ?? ? stack pointer (s) ? b7 b0 ? b15 b8 index register y (y) ? b7 b0 ? b15 b8 index register x (x) ? b7 b0 ? b15 b8 accumulator b (b) ? b7 b0 ? b15 b8 accumulator a (a) ? b7 b0 ? b15 b8 register name state immediately after reset : always ??at reading. 0
7721 group users manual reset 4C5 4.1 hardware reset ? 0 : 0 immediately after reset. 1 : 1 immediately after reset. ? : underfined immediately after reset. : always 0 at reading. 0 0 : always undefined at reading. : 0 immediately after reset. fix this bit to 0. 10 16 11 16 12 16 13 16 port p8 direction register 14 16 15 16 16 16 17 16 18 16 19 16 1a 16 1b 16 1c 16 1d 16 1e 16 1f 16 0 16 1 16 2 16 3 16 4 16 5 16 6 16 7 16 8 16 9 16 b 16 c 16 d 16 e 16 f 16 a 16 address port p4 register port p5 register port p4 direction register port p5 direction register port p6 register port p7 register port p6 direction register port p7 direction register port p8 register a-d control register a-d sweep pin select register register name access characteristics state immediately after reset rw rw rw rw rw rw rw rw rw rw ? 00 16 00 16 00 16 0 0 000 ? 11 b7 b0 b7 b0 : it is possible to read the bit state at reading. the written value becomes valid. : it is possible to read the bit state at reading. the written value becomes invalid. : the written value becomes valid. it is impossible to read the bit state. : nothing is assigned. it is impossible to read the bit state. the written value becomes invalid. rw ro wo l sfr area (0 16 to 7f 16 , 1fc0 16 to 1fff 16 ) rw ? ? ? ? ? ? ? ? ? ? ? ? ? 00 16 ? ? ? 0 ? ? ? ? ? ? ??? ? : always 1 at reading. 1 ? ? ? ? ? rw rw rw rw rw wo wo port p9 register port p9 direction register port p10 register port p10 direction register pulse output data register 0 pulse output data register 1 000 000 000 00 ? access characteristics state immediately after reset 00 16 00 16 fig. 4.1.4 state of sfr and internal ram areas immediately after reset (1)
reset 7721 group users manual 4C6 4.1 hardware reset uart0 transmit/receive control register 0 uart0 transmit/receive mode register uart0 baud rate register uart0 transmit buffer register uart1 receive buffer register register name uart0 transmit/receive control register 1 uart0 receive buffer register uart1 transmit/receive mode register uart1 baud rate register uart1 transmit buffer register uart1 transmit/receive control register 0 uart1 transmit/receive control register 1 30 16 31 16 32 16 33 16 34 16 35 16 36 16 37 16 38 16 39 16 3a 16 3b 16 3c 16 3d 16 3e 16 28 16 29 16 2b 16 2c 16 2d 16 2e 16 2f 16 2a 16 20 16 21 16 22 16 23 16 24 16 25 16 26 16 27 16 3f 16 address access characteristics rw wo wo ro ro b7 b0 wo rw ro ro ro rw rw ro ro rw wo wo wo rw ro rw rw state immediately after reset 1 000 00 16 0 000 00 0 ? b7 b0 00 16 00000010 0000 0 0 0 1 000 0000 0 0 1 0 ? ? ? ? ? ? ? ? ? ? ? a-d register 5 a-d register 1 a-d register 3 a-d register 2 a-d register 4 a-d register 0 a-d register 6 a-d register 7 ro ro ro ro ro ro ro ro ro ro ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ??? ? ??? fig. 4.1.5 state of sfr and internal ram areas immediately after reset (2)
7721 group users manual reset 4C7 4.1 hardware reset rw rw rw timer b2 register 40 16 41 16 42 16 43 16 44 16 45 16 46 16 47 16 48 16 49 16 50 16 51 16 52 16 53 16 54 16 55 16 56 16 57 16 58 16 59 16 5a 16 5b 16 5c 16 5d 16 5e 16 5f 16 4b 16 4c 16 4d 16 4e 16 4f 16 4a 16 address timer a2 register timer a3 register timer a4 register timer b0 register timer b1 register processor mode register 0 one-shot start register timer a0 register up-down register timer a1 register register name count start register timer a1 mode register timer a2 mode register timer a3 mode register timer b0 mode register timer b1 mode register timer b2 mode register access characteristics wo (note 1) (note 1) (note 1) (note 2) (note 2) (note 2) b7 b0 rw (note 2) rw rw rw rw rw rw wo state immediately after reset 00 16 00 16 00 16 ? 00 16 b7 b0 wo rw (note 1) (note 1) (note 1) rw timer a0 mode register timer a4 mode register (note 3) 0 00 0 0 0 0 0 0 0 0 0 0 00 0 00 0 0 0 0 0 0 0 0 rw rw ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? notes 1: the access characteristics at addresses 4a 16 to 4f 16 vary according to timer as operating mode. (refer to chapter 8. timer a. ) 2: the access characteristics at addresses 50 16 to 53 16 vary according to timer bs operating mode. (refer to chapter 9. timer b. ) 3: the access characteristics for bit 5 at addresses 5b 16 and 5c 16 vary according to timer bs operating mode. bit 5 at address 5d 16 is invalid. (refer to chapter 9. timer b. ) 4: bit 1 at address 5f 16 becomes 0 immediately after reset. for the m37721s1bfp, fix this bit to 0. rw (note 3) rw (note 3) 00 0 0 00 ? ? 0 0 0 00 0 ? ? ? processor mode register 1 rw rw rw rw rw rw rw 00 0 00 0 ? 0 0 00 0 00 0 0 0 1 ? (note 4) fig. 4.1.6 state of sfr and internal ram areas immediately after reset (3)
reset 7721 group users manual 4C8 4.1 hardware reset uart1 receive interrupt control register 60 16 61 16 62 16 63 16 64 16 65 16 66 16 67 16 68 16 69 16 70 16 71 16 72 16 73 16 74 16 75 16 76 16 77 16 78 16 79 16 7a 16 7b 16 7c 16 7d 16 7e 16 7f 16 6b 16 6c 16 6d 16 6e 16 6f 16 6a 16 address a-d conversion interrupt control register uart0 transmit interrupt control register uart1 transmit interrupt control register int 2 interrupt control register watchdog timer frequency select register register name watchdog timer register timer a0 interrupt control register timer a2 interrupt control register timer a3 interrupt control register timer a4 interrupt control register timer b1 interrupt control register timer b2 interrupt control register int 0 interrupt control register access characteristics rw b7 b0 rw state immediately after reset 0 ? (note 6) b7 b0 uart0 receive interrupt control register timer a1 interrupt control register timer b0 interrupt control register int 1 interrupt control register 0 0 00 0 by writing dummy data to address 60 16 , the value fff 16 is set to the watchdog timer. the dummy data is not retained anywhere. the value fff 16 is set to the watchdog timer. (refer to chapter 15. watchdog timer .) it is possible to read the bit state at reading. when writing 0 to this bit, this bit becomes 0. but when writing 1 to this bit, this bit does not change. rw notes 5: 6: 7: (note 5) ? ? ? rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 0 00 0 ? 0 00 0 ? 0 00 0 ? 0 00 0 ? 0 00 0 ? 0 00 0 ? 0 00 0 ? 0 00 0 ? 0 00 0 ? 0 00 0 ? 0 00 0 ? 0 00 0 0 00 0 0 00 0 0 0 0 0 0 0 ? ? ? ? ? ? ? ? ? 0 00 real-time output control register refresh timer dm ac control register l dm ac control register h dm a0 interrupt control register dm a1 interrupt control register dm a2 interrupt control register dm a3 interrupt control register rw 0 0 0 0 0 0 0 0 rw rw dram control register wo rw (note 7) rw wo rw rw rw rw 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ?? 0 0 00 0 ? ? 0 00 0 ? 0 00 0 ? 0 00 fig. 4.1.7 state of sfr and internal ram areas immediately after reset (4)
7721 group users manual reset 4C9 4.1 hardware reset fig. 4.1.8 state of sfr and internal ram areas immediately after reset (5) 1fc0 16 1fc1 16 1fc2 16 1fc3 16 1fc4 16 1fc5 16 1fc6 16 1fc7 16 1fc8 16 1fc9 16 1fd0 16 1fd1 16 1fd2 16 1fd3 16 1fd4 16 1fd5 16 1fd6 16 1fd7 16 1fd8 16 1fd9 16 1fda 16 1fdb 16 1fdc 16 1fdd 16 1fde 16 1fdf 16 1fcb 16 1fcc 16 1fcd 16 1fce 16 1fcf 16 1fca 16 address register name source address register 0 access characteristics b7 b0 state immediately after reset b7 b0 rw aa aa 0 00 0 aa aa aa aa 0 00 0 0 00 0 ? ? rw rw aa aa aa aa 0 0 00 0 aa aa 0 00 0 ? 0 00 destination address register 0 transfer counter register 0 dma0 mode register l dma0 mode register h dma0 control register source address register 1 destination address register 1 transfer counter register 1 dma1 mode register l dma1 mode register h dma1 control register rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw ? ? ? ? ? ? ? ? ? ? 0 0 00 0 0 0 0 00 ?? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 00 0 0 00 0 0 0 ??
reset 7721 group users manual 4C10 4.1 hardware reset fig. 4.1.9 state of sfr and internal ram areas immediately after reset (6) 1fe0 16 1fe1 16 1fe2 16 1fe3 16 1fe4 16 1fe5 16 1fe6 16 1fe7 16 1fe8 16 1fe9 16 1ff0 16 1ff1 16 1ff2 16 1ff3 16 1ff4 16 1ff5 16 1ff6 16 1ff7 16 1ff8 16 1ff9 16 1ffa 16 1ffb 16 1ffc 16 1ffd 16 1ffe 16 1fff 16 1feb 16 1fec 16 1fed 16 1fee 16 1fef 16 1fea 16 address register name source address register 2 access characteristics b7 b0 state immediately after reset b7 b0 rw aaa aaa 0 00 0 aa aa aaa aaa 0 00 0 0 00 0 ? ? rw rw aa aa aaa aaa 0 0 00 0 aaa aaa 0 00 0 ? 0 00 destination address register 2 transfer counter register 2 dma2 mode register l dma2 mode register h dma2 control register source address register 3 destination address register 3 transfer counter register 3 dma3 mode register l dma3 mode register h dma3 control register rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw ? ? ? ? ? ? ? ? ? ? 0 0 00 0 0 0 0 00 ?? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 00 0 0 00 0 0 0 ?? l internal ram area (addresses 80 16 to 27f 16 ) ?t hardware reset (except the case where stop or wait mode is terminated)............................................... undefined. ?t software reset.............................................................. retains the state immediately before reset ?t termination of stop or wait mode (hardware reset is used to terminate it.)............... retains the state immediately before the stp or wit instruction is executed ] ] for the m37721s2bfp, the internal ram area can be assigned to addresses 80 16 to 47f 16 by setting the internal ram area select bit (bit 1 at address 5f 16 ). (refer to section ?.4 memory assignment. )
7721 group users manual reset 4C11 4.1.3 internal processing sequence after reset figure 4.1.10 shows the internal processing sequence after reset. 4.1 hardware reset fig. 4.1.10 internal processing sequence after reset (next op-code or operand) h cpu a 0 Ca 7 a 8 /d 8 Ca 15 /d 15 fe 16 ad l e r/w l external bus width = 16 bits (byte = l) ad h (ad h ) 00 16 ff 16 00 16 00 16 (next op-code) a 16 /d 0 Ca 23 /d 7 00 16 (ad l ) 00 16 00 16 00 16 ale h cpu a 0 Ca 7 fe 16 ad l e r/w 00 16 a 16 /d 0 Ca 23 /d 7 00 16 (ad h ) 00 16 00 16 00 16 ale ff 16 a 8 Ca 15 ff 16 ad h 00 16 ff 16 00 16 (ad l ) l external bus width = 8 bits (byte = h) (next op-code)
reset 7721 group users manual 4C12 ______ 4.1.4 time supplying l level to reset pin ______ time supplying l level to the reset pin varies according to the state of the clock oscillation circuit. l when the oscillator is stably oscillating or a stable clock is input from the x in pin, supply l level for 2 s or more. l when the oscillator is not stably oscillating (including the case at power-on reset or in stop mode), supply l level until the oscillation is stabilized. the time required for stabilizing oscillation varies according to the oscillator. for details, contact the oscillator manufacturer. figure 4.1.11 shows the power-on reset conditions. figure 4.1.12 shows an example of a power-on reset circuit. ] for details about stop mode, refer to section 5.3 stop mode. for details about clocks, refer to chapter 5. clock generating circuit. 4.1 hardware reset fig. 4.1.11 power-on reset conditions fig. 4.1.12 example of power-on reset circuit 0v 0v vcc reset powered on here 4.5v 0.9v 1 in out gnd delay capacity reset vcc vss 47 sw c d gnd 3 25 5 v m51957al m37721 27 k 10 k 4 ] the delay time is about 11 ms when c d = 0.033 m f. t d ? 0.34 5 c d [ m s], c d : [ pf ] vcc
7721 group users manual reset 4C13 4.2 software reset 4.2 software reset when the power source voltage satisfies the microcomputers recommended operating conditions, the microcomputer is reset by writing 1 to the software reset bit (bit 3 at address 5e 16 ). (this is called software reset.) in this case, the microcomputer initializes pins, cpu, and sfr area just as in the case of a hardware reset. however, the microcomputer retains the contents of the internal ram area. (refer to table 4.1.1 and figures 4.1.3 to 4.1.9. ) figure 4.2.1 shows the structure of the processor mode register 0 (address 5e 16 ). after completing initialization, the microcomputer performs internal processing sequence after reset. (refer to figure 4.1.10. ) after that, it executes a program beginning from the address set into the reset vector addresses (fffe 16 and ffff 16 ) . i bit bit name functions at reset rw 0 1 2 3 4 5 6 7 software reset bit interrupt priority detection time select bits fix this bit to 0 stack bank select bit 0 0 0 0 0 0 the microcomputer is reset by writing 1 to this bit. the value of this bit is 0 at reading. 0 0 : 7 cycles of 0 1 : 4 cycles of 1 0 : 2 cycles of 1 1 : do not select. 0 : bank 0 16 1 : bank ff 16 0 b5 b4 processor mode register 0 (address 5e 16 ) : bits 0 to 2 and bits 4 to 7 are not used for software reset. b1 b0 b2 b3 b4 b5 b6 b7 0 0 rw rw wo rw rw rw rw fix this bit to 0 nothing is assigned. this bit is 1 at reading. 1 wait bit 0 : software wait is inserted when accessing external area. 1 : no software wait is inserted when accessing external area. fig. 4.2.1 structure of processor mode register 0
reset 7721 group users manual 4C14 4.2 software reset ________ when the software reset bit is set to 1, the reset out pins output level becomes l. in a period of 4.5 ________ cycles of clock f 1 after the software reset bit is set to 1, the reset out pins output level is l. figure ________ 4.2.2 shows the reset out output timing at software reset. ________ fig. 4.2.2 reset out output timing 1 e reset out set software reset bit to 1
chapter 5 clock generating circuit 5.1 oscillation circuit examples 5.2 clocks 5.3 stop mode [precautions for stop mode] 5.4 wait mode [precautions for wait mode]
clock generating circuit 7721 group users manual 5C2 5.1 oscillation circuit examples to the oscillation circuit, a ceramic resonator or a quartz-crystal oscillator can be connected, or the clock which is externally generated can be input. oscillation circuit examples are shown below. 5.1.1 connection example using resonator/oscillator figure 5.1.1 shows an example when connecting a ceramic resonator/quartz-crystal oscillator between pins x in and x out . the circuit constants such as r f , r d , c in , and c out (shown in figure 5.1.1 ) depend on the resonator/ oscillator. these values shall be set to the values recommended by the resonator/oscillator manufacturer. 5.1.2 externally generated clock input example figure 5.1.2 shows an input example of the clock which is externally generated. the external clock must be input from the x in pin, and the x out pin must be left open. 5.1 oscillation circuit examples fig. 5.1.1 connection example using resonator/oscillator fig. 5.1.2 externally generated clock input example m37721 x in x out r f c in c out r d m37721 x in x out vcc vss externally generated clock open
clock generating circuit 7721 group users manual 5C3 5.2 clocks 5.2 clocks figure 5.2.1 shows the clock generating circuit block diagram. fig. 5.2.1 clock generating circuit block diagram q x in x out 1/2 r s q r s q r s 1 cpu 1/8 1/2 f 2 1/2 1/8 f 16 f 64 f 512 f 32 f 512 interrupt request stp instruction reset wit instruction ready request cpu wait request from biu operation clock for internal peripheral devices watchdog timer cpu : central processing unit biu : bus interface unit watchdog timer frequency select bit : bit 0 at address 61 16 note: this signal is generated when the watchdog timers most significant bit becomes 0. ( note ) watchdog timer frequency select bit 0 1 bus request dramc hold dmac
clock generating circuit 7721 group users manual 5C4 5.2 clocks 5.2.1 clocks generated in clock generating circuit (1) f it is the operation clock of biu. it is also the clock source of f cpu . f stops by acceptance of ready request or execution of the stp or wit instruction. it is not stopped by acceptance of bus request. (2) f cpu it is the operation clock of cpu. f cpu stops by the following: ?execution of the stp or wit instruction, ____ ?acceptance of ready request; l level input to the rdy pin ?cpu wait request from biu; acceptance of bus request is included. (3) clock f 1 it has the same period as f and is output to the external from the f 1 pin. clock f 1 stops by execution of the stp instruction. it is not stopped by acceptance of ready or bus request, or execution of the wit instruction. (4) f 2 to f 512 each of them is the internal peripheral devices operation clock. note: refer to each functional description for details: ?execution of stp instruction ............. 5.3 stop mode ?execution of wit instruction .............. 5.4 wait mode ?ready ..................................................... 3.3 ready function ?bus request ........................................... 13.2.1 bus access control circuit
clock generating circuit 7721 group users manual 5C5 5.3 stop mode 5.3 stop mode stop mode is used to stop oscillation when there is no need to operate the central processing unit (cpu). the microcomputer enters stop mode when the stp instruction is executed. stop mode can be terminated by an interrupt request occurrence or the hardware reset. 5.3.1 stop mode when the stp instruction is executed, the oscillator stops oscillating. this state is called stop mode. in stop mode, the contents of the internal ram can be retained intact when vcc (power source voltage) is 2 v or more. additionally, the microcomputers power consumption is lowered. it is because the cpu and all internal peripheral devices using clocks f 2 to f 512 stop the operation. table 5.3.1 lists the microcomputers state and operation in and after stop mode. table 5.3.1 microcomputers state and operation in and after stop mode state and operation item oscillation f cpu , f clock f 1 , f 2 to f 512 timers a, b serial i/o a-d converter dma controller dram controller watchdog timer pins by interrupt request occurrence by hardware reset internal peripheral devices state in stop mode operation after terminating stop mode stopped can operate only in event counter mode can operate only when an external clock is selected stopped stopped (note) stopped retains the same state in which the stp instruction was executed supply of f cpu and f starts after a certain time measured by watchdog timer has passed. operates in the same way as hardware reset note: dram refresh is not performed because the refresh timer also stops.
clock generating circuit 7721 group users manual 5C6 (1) termination by interrupt request occurrence when terminating stop mode by interrupt request occurrence, instructions are executed after a certain time measured by the watchdog timer has passed. when an interrupt request occurs, the oscillator starts oscillating. simultaneously, supply of clock f 1 , f 2 to f 512 starts. the watchdog timer starts counting owing to the oscillation start. the watchdog timer counts f 32 regardless of the watchdog timer frequency select bits (bit 0 at address 61 16 ) contents. a when the watchdog timers msb becomes 0, supply of f cpu and f starts. at the same time, the watchdog timers count source returns to f 32 or f 512 that is selected by the watchdog timer frequency select bit. ? the interrupt request which occurred in is accepted. table 5.3.2 lists the interrupts used to terminate stop mode. table 5.3.2 interrupts used to terminate stop mode 5.3 stop mode conditions for using each function to generate interrupt request interrupt ____ int i interrupt (i = 0 to 2) timer ai interrupt (i = 2 to 4) timer bi interrupt (i = 0, 1) uarti transmit interrupt (i = 0, 1) uarti receive interrupt (i = 0, 1) in event counter mode when external clock is selected notes 1: since the oscillator has stopped oscillating, interrupts not listed above cannot be used. also, even the interrupts listed above cannot be used when the above conditions are not satisfied. the a-d converter does not operate, also. 2: when multiple interrupts listed above are enabled, stop mode is terminated by the interrupt request which occurs first. 3: refer to chapter 7. interrupts and the description of each internal peripheral device for details about each interrupt. before executing the stp instruction, interrupts used to terminate stop mode must be enabled. in addition, the interrupt priority level of the interrupt used to terminate stop mode must be higher than the processor interrupt priority level (ipl) of the routine where the stp instruction is executed. when multiple interrupts in table 5.3.2 are enabled, stop mode is terminated by the first interrupt request. there is a possibility that any of all interrupt requests occurs after the oscillation starts in and until supply of f cpu and f starts in a . the interrupt requests which occur during this period are accepted in order of priority after the watchdog timers msb becomes 0. for interrupts not to be accepted, set their interrupt priority levels to level 0 (interrupt disabled) before executing the stp instruction.
clock generating circuit 7721 group users manual 5C7 fig. 5.3.1 stop mode terminating sequence by interrupt request occurrence (2) termination by hardware reset ______ supply l level to the reset pin by using the external circuit until the oscillation of the oscillator is stabilized. the cpu and the sfr area are initialized in the same way as system reset. however, the internal ram area retains the same contents as that before executing the stp instruction. the terminating sequence is the same as the internal processing sequence which is performed after reset. refer to chapter 4. reset for details about reset. 5.3 stop mode cpu 7ff 16 fff 16 stop mode f(x in ) operating stopped stopped internal peripheral devices operating value of watchdog timer f 32 5 2048 counts interrupt request used to terminate stop mode (interrupt request bit) stopped operating operating operating l interrupt request used to terminate stop mode occurs. l oscillation starts.(when an external clock is input from the x in pin, clock input starts.) l watchdog timer starts counting. l stp instruction is executed l watchdog timers msb = 0 (however, watchdog timer interrupt request does not occur.) l supply of cpu , starts. l interrupt request which has been used to terminate stop mode is accepted. cpu , 1
clock generating circuit 7721 group users manual 5C8 [precautions for stop mode] when executing the stp instruction after writing to an internal area or an external area, three nop instructions must be inserted to complete the write operation before the stp instruction is executed. (refer to figure 5.3.2. ) 5.3 stop mode sta nop nop nop stp ; ; ; ; ; a, 5555 write instruction nop instruction inserted stp instruction fig. 5.3.2 nop instruction insertion example
clock generating circuit 7721 group users manual 5C9 5.4 wait mode wait mode is used to stop f cpu and f when there is no need to operate the central processing unit (cpu). the microcomputer enters wait mode when the wit instruction is executed. wait mode can be terminated by an interrupt request occurrence or the hardware reset. 5.4.1 wait mode when the wit instruction is executed, f cpu and f stop. the oscillators oscillation is not stopped. this state is called wait mode. in wait mode, the microcomputers power consumption is lowered though vcc (power source voltage) is maintained. table 5.4.1 lists the microcomputers state and operation in and after wait mode. table 5.4.1 microcomputers state and operation in and after wait mode 5.4 wait mode state and operation item oscillation f cpu , f clock f 1 , f 2 to f 512 timer a timer b serial i/o a-d converter dma controller dram controller watchdog timer pins state in wait mode operation after terminating wait mode internal peripheral devices by interrupt request occurrence by hardware reset operating stopped operating operating stopped stopped (note) operating retains the same state in which the wit instruction was executed supply of f cpu and f starts just after the termination. operates in the same way as hardware reset. note: the refresh timer operates, but dram refresh is not performed because the bus request (dramc) does not occur. (refer to section appendix 9. 7721 group q & a. )
clock generating circuit 7721 group users manual 5C10 (1) termination by interrupt request occurrence when an interrupt request occurs, supply of f cpu and f starts. the interrupt request which occurred in is accepted. the following interrupts are used to terminate wait mode. when a watchdog timer interrupt request occurs, wait mode is also terminated. ___ ?int i interrupt (i = 0 to 2) ?timer ai interrupt (i = 0 to 4) ?timer bi interrupt (i = 0 to 2) ?uarti transmit interrupt (i = 0, 1) ?uarti receive interrupt (i = 0, 1) ?a-d converter interrupt note: refer to chapter 7. interrupts and each functional description about interrupts. before executing the wit instruction, interrupts used to terminate wait mode must be enabled. in addition, the interrupt priority level of the interrupt used to terminate wait mode must be higher than the processor interrupt priority level (ipl) of the routine where the wit instruction is executed. when multiple interrupts listed above are enabled, wait mode is terminated by the interrupt request which occurs first. (2) termination by hardware reset the cpu and the sfr area are initialized in the same way as system reset. however, the internal ram area retains the same contents as that before executing the wit instruction. the terminating sequence is the same as the internal processing sequence which is performed after reset. refer to chapter 4. reset for details about reset. 5.4 wait mode
clock generating circuit 7721 group users manual 5C11 [precautions for wait mode] when executing the wit instruction after writing to an internal area or an external area, three nop instructions must be inserted to complete the write operation before the wit instruction is executed. (refer to figure 5.4.1. ) 5.4 wait mode sta nop nop nop wit a, 5555 ; ; ; ; ; write instruction nop instruction inserted wit instruction fig. 5.4.1 nop instruction insertion example
clock generating circuit 7721 group users manual 5C12 5.4 wait mode memorandum
chapter 6 input/output pins 6.1 overview 6.2 programmable i/o ports 6.3 examples of handling unused pins
7721 group users manual input/output pins 6C2 6.1 overview input/output pins (hereafter called i/o pins) have functions as programmable i/o ports, internal peripheral devicess i/o pins, external buses, etc. for the basic functions of each i/o pin, refer to section 1.3 pin description. for the i/o functions of the internal peripheral devices, refer to relevant sections of each internal peripheral device. for the external address bus, external data bus, bus control signals, etc., refer to chapter 3. connection with external devices. this chapter describes the programmable i/o ports and examples of handling unused pins. 6.2 programmable i/o ports the programmable i/o ports have direction registers and port registers in the sfr area. figure 6.2.1 shows the memory map of direction registers and port registers. 6.1 overview, 6.2 programmable i/o ports fig. 6.2.1 memory map of direction registers and port registers port p6 register port p7 register port p6 direction register port p7 direction register port p8 register port p9 register port p8 direction register port p9 direction register port p10 register port p10 direction register a 16 b 16 c 16 d 16 e 16 f 16 10 16 11 16 12 16 13 16 14 16 addresses port p4 register port p5 register port p4 direction register port p5 direction register 15 16 16 16 17 16 18 16
7721 group users manual 6C3 input/output pins 6.2.1 direction register this register determines the i/o direction of programmable i/o ports. each bit of this register corresponds one for one to each pin of the microcomputer. figure 6.2.2 shows the structure of port pi (i = 4 to 10) direction register. 6.2 programmable i/o ports bit bit name functions 0 1 2 3 4 5 6 7 port pi 0 direction bit port pi 2 direction bit port pi 3 direction bit port pi 4 direction bit port pi 6 direction bit 0 : input mode (the port functions as an input port) 1 : output mode (the port functions as an output port) port pi 5 direction bit port pi direction register (i = 4 to 10) (addresses c 16 , d 16 , 10 16 , 11 16 , 14 16 , 15 16 , 18 16 ) b1 b0 b2 b3 b4 b5 b6 b7 port pi 1 direction bit port pi 7 direction bit at reset rw 0 0 0 0 0 0 0 0 rw rw rw rw rw rw rw rw note: for bits 0 to 2 of the port p4 direction register, nothing is assigned and these bits are fixed to ??at reading. fig. 6.2.2 structure of port pi (i = 4 to 10) direction register
7721 group users manual input/output pins 6C4 6.2.2 port register data is input from or output to the external by writing/reading data to/from a port register. a port register consists of a port latch which holds the output data and a circuit which reads the pin state. each bit of the port register corresponds one for one to each pin of the microcomputer. figure 6.2.3 shows the structure of the port pi (i = 4 to 10) register. l when outputting data from programmable i/o port set to output mode by writing data to the corresponding bit of the port register, the data is written into the port latch. the data is output from the pin according to the contents of the port latch. by reading the port register of a port set to the output mode, the contents of the port latch is read out, instead of the pin state. accordingly, the output data is correctly read without being affected by an external load, etc. (refer to figures 6.2.4 and 6.2.5. ) l when inputting data from programmable i/o port set to input mode a pin which is set to the input mode enters the floating state. by reading the corresponding bit of the port register, the data which is input from the pin can be read out. by writing data to the port register of a programmable i/o port set to the input mode, the data is written only into the port latch and is not output to the external (note) . the pin remains floating. note: when executing a read-modify-write instruction ( clb, seb, inc, dec, asl, asr, lsr, rol, ror ) to the port register of a programmable i/o port set to the input mode, the instruction is executed to the data which is input from the pin and the result is written into the port register. 6.2 programmable i/o ports fig. 6.2.3 structure of port pi (i = 4 to 10) register bit bit name functions 0 1 2 3 4 5 6 7 port pi 0 ? pin port pi 2 ? pin port pi 3 ? pin port pi 4 ? pin port pi 6 ? pin data is input from or output to a pin by reading from or writing to the corresponding bit. port pi 5 ? pin port pi register (i = 4 to 10) (addresses a 16 , b 16 , e 16 , f 16 , 12 16 , 13 16 , 16 16 ) b1 b0 b2 b3 b4 b5 b6 b7 port pi 1 ? pin port pi 7 ? pin at reset rw undefined undefined undefined undefined undefined undefined undefined undefined 0 : ??level 1 : ??level rw rw rw rw rw rw rw rw note: for bits 0 to 2 of the port p4 register, nothing is assigned and these bits are fixed to ??at reading.
7721 group users manual 6C5 input/output pins figures 6.2.4 and 6.2.5 show the port peripheral circuits. 6.2 programmable i/o ports fig. 6.2.4 port peripheral circuits (1) ports p4 3 to p4 6 [inside dotted-line not included] data bus direction register port latch ports p8 3 /txd 0 , p8 7 /txd 1 , [inside dotted-line not included] ports p5 0 /ta2 out , p5 2 /ta3 out , p5 4 /ta4 out [inside dotted-line included] data bus a a a ? output port latch direction register p8 2 /rxd 0 , p8 6 /rxd 1 , ports p4 7 , p5 1 /ta2 in , p5 3 /ta3 in , p5 5 /ta4 in , p5 6 /tb0 in , p5 7 /tb1 in , [inside dotted-line included] (there is no hysteresis for p8 2 /rxd 0 and p8 6 /rxd 1 .) ports p6 0 /rtp0 0 to p6 7 /rtp1 3 data bus direction register port latch p9 1 /dmareq0, p9 3 /dmareq1, p9 5 /dmareq2, p9 7 /dmareq3, p10 0 /int 0 , p10 1 /int 1 , p10 2 /int 2 , p9 0 /dmaack0, p9 2 /dmaack1, p9 4 /dmaack2, p9 6 /dmaack3, p10 4 /cas, p10 5 /ras, p10 6 /ma 8 , p10 7 /ma 9 (internal peripheral device) latch tq ck timer underflow signal
7721 group users manual input/output pins 6C6 6.2 programmable i/o ports fig. 6.2.5 port peripheral circuits (2) ports p7 0 /an 0 to p7 6 /an 6 [inside dotted-line not included] data bus direction register port latch ports p8 0 /cts 0 /rts 0 , p8 1 /clk 0 , data bus a a output port latch direction register [inside dotted-line included] port p10 3 /tc data bus direction register port latch (internal peripheral device) port p7 7 /an 7 /ad trg analog input p8 4 /cts 1 /rts 1 , p8 5 /clk 1 ? ? a a a a ? (tc) e output pin output
7721 group user?s manual 6e7 input/output pins 6.3 examples of handling unused pins when unusing an i/o pin, some handling is necessary for the pin. examples of handling unused pins are described below. the following are just examples. the user shall modify them according to the users actual ap plication and test them. table 6.3.1 examples of handling unused pins 6.3 examples of handling unused pins handling example set these pins to the input mode and connect each pin to vcc or vss via a resistor; or set these pins to the output mode and leave them open (notes 1 and 2). leave them open. connect these pins to vcc via a resistor (pull-up) (note 2). connect this pin to vcc or vss. connect this pin to vcc. connect these pins to vss. pin name p4 3 to p4 7 , p5 to p10 ___ ___ ble, bhe, ale, f 1 , st0, st1 x out (note 3) _____ ____ hold, rdy cnvss avcc avss, v ref fig. 6.3.1 examples of handling unused pins p4 3 Cp4 7 , p5Cp10 m37721 st0 st1 ble bhe ale 1 x out av ss v ref hold rdy m37721 v cc v ss av cc l when setting ports to input mode l when setting ports to output mode left open left open left open av ss v ref hold rdy v cc v ss av cc left open p4 3 Cp4 7 , p5Cp10 left open st0 st1 ble bhe ale 1 x out cnv ss ] cnv ss ] ] cnv ss can be connected to v cc , too. notes 1: when leaving these pins open after they are set to the outpu t mode, note the following: these pins function as input ports from reset until they are switched t o the output mode by software. therefore, voltage levels of these pins are undefined and the power sou rce current may increase while these pins function as input ports. after reset, immediately set t hese ports to the output mode. software reliability can be enhanced by setting the contents of the above ports direction registers periodically. this is because these contents may be changed by noise, a program runaway which occurs owing to noise, etc. 2: for unused pins, use the shortest possible wiring (within 2 0 mm from the microcomputers pins). 3: this applies when a clock externally generated is input to the x in pin.
7721 group users manual input/output pins 6C8 memorandum 6.3 examples of handling unused pins
chapter 7 interrupts 7.1 overview 7.2 interrupt sources 7.3 interrupt control 7.4 interrupt priority level 7.5 interrupt priority level detection circuit 7.6 interrupt priority level detection time 7.7 sequence from acceptance of interrupt request until execution of interrupt routine 7.8 return from interrupt routine 7.9 multiple interrupts ____ 7.10 external interrupts (int i interrupt) 7.11 precautions for interrupts
7721 group users manual interrupts 7C2 7.1 overview the m37721 provides 23 interrupt sources to generate interrupt requests. figure 7.1.1 shows the interrupt processing sequence. when an interrupt request is accepted, a branch is made to the start address of the interrupt routine set in the interrupt vector table (addresses ffce 16 to ffff 16 ). set the start address of each interrupt routine to the corresponding interrupt vector address in the interrupt vector table. 7.1 overview fig. 7.1.1 interrupt processing sequence interrupt routine interrupt request is accepted. processing is resumed. processing is suspended. returns to original routine. rti instruction interrupt processing routine in progress branches to start address of interrupt routine.
7721 group users manual 7C3 interrupts when an interrupt request is accepted, the following registers contents just before acceptance of an interrupt request are automatically pushed onto the stack area ? ? a in that order. program bank register (pg) program counter (pc l , pc h ) a processor status register (ps l , ps h ) figure 7.1.2 shows the state of the stack area just before entering the interrupt routine. execute the rti instruction at the end of this interrupt routine to return to the routine that the microcomputer was executing before the interrupt request was accepted. by executing the rti instruction, the register contents pushed onto the stack area are pulled a ? ? in that order. then, the suspended processing is resumed from where it left off. 7.1 overview [s] is an initial address that the stack pointer (s) indicates when an interrupt request is accepted. the s? contents become ?s] ?5?after all of the above registers are pushed. address [s] ?4 [s] ?3 [s] ?2 [s] ?1 [s] ] processor status register? low-order byte (ps l ) stack area [s] ?5 processor status register? high-order byte (ps h ) program counter? low-order byte (pc l ) program counter? high-order byte (pc h ) program bank register (pg) ] fig. 7.1.2 state of stack area just before entering interrupt routine
7721 group users manual interrupts 7C4 remarks non-maskable non-maskable software interrupt non-maskable software interrupt do not use. non-maskable interrupt maskable external interrupts maskable internal interrupts maskable internal interrupts maskable internal interrupts maskable internal interrupt maskable internal interrupts 7.2 interrupt sources table 7.2.1 lists the interrupt sources and the interrupt vector addresses. when programming, set the start address of each interrupt routine at the vector addresses listed in this table. 7.2 interrupt sources low-order address fffe 16 fffc 16 fffa 16 fff8 16 fff6 16 fff4 16 fff2 16 fff0 16 ffee 16 ffec 16 ffea 16 ffe8 16 ffe6 16 ffe4 16 ffe2 16 ffe0 16 ffde 16 ffdc 16 ffda 16 ffd8 16 ffd6 16 ffd4 16 ffd2 16 ffd0 16 ffce 16 interrupt vector addresses table 7.2.1 interrupt sources and interrupt vector addresses high-order address ffff 16 fffd 16 fffb 16 fff9 16 fff7 16 fff5 16 fff3 16 fff1 16 ffef 16 ffed 16 ffeb 16 ffe9 16 ffe7 16 ffe5 16 ffe3 16 ffe1 16 ffdf 16 ffdd 16 ffdb 16 ffd9 16 ffd7 16 ffd5 16 ffd3 16 ffd1 16 ffcf 16 interrupt source reset zero division brk instruction ____ dbc (note) watchdog timer ____ int 0 ____ int 1 ____ int 2 timer a0 timer a1 timer a2 timer a3 timer a4 timer b0 timer b1 timer b2 uart0 receive uart0 transmit uart1 receive uart1 transmit a-d conversion dma0 dma1 dma2 dma3 ____ note: the dbc interrupt is used exclusively for debugger control. l maskable interrupt: an interrupt of which requests acceptance can be disabled by software. l non-maskable interrupt (including zero division, brk instruction, watchdog timer interrupts) : an interrupt which is certain to be accepted when its request occurs. these interrupts do not have their interrupt control registers and are not affected by the interrupt disable flag (i). reference 4. reset 7700 family software manual 15. watchdog timer 7.10 external interrupts ____ ( int i interrupt) 8. timer a 9. timer b 11. serial i/o 12. a-d converter 13. dma controller
7721 group users manual 7C5 interrupts 7.3 interrupt control the maskable interrupts are controlled by the following : ?interrupt request bit ?interrupt priority level select bits ?processor interrupt priority level (ipl) ?interrupt disable flag (i) figure 7.3.1 shows the memory assignment of the interrupt control registers, and figure 7.3.2 shows their structures. } } assigned to the interrupt control register of each interrupt. assigned to the processor status register (ps). 7.3 interrupt control fig. 7.3.1 memory assignment of interrupt control registers dma3 interrupt control register 6f 16 uart0 transmit interrupt control register uart0 receive interrupt control register uart1 transmit interrupt control register uart1 receive interrupt control register timer a0 interrupt control register timer a1 interrupt control register timer a2 interrupt control register timer a3 interrupt control register timer a4 interrupt control register timer b0 interrupt control register timer b1 interrupt control register timer b2 interrupt control register int 0 interrupt control register int 1 interrupt control register int 2 interrupt control register address a-d conversion interrupt control register 70 16 71 16 72 16 73 16 74 16 75 16 76 16 77 16 78 16 79 16 7a 16 7b 16 7c 16 7d 16 7e 16 7f 16 dma2 interrupt control register 6e 16 dma1 interrupt control register 6d 16 dma0 interrupt control register 6c 16
7721 group users manual interrupts 7C6 fig. 7.3.2 structures of interrupt control register note: the interrupt request bits of int 0 to int 2 interrupts are invalid when the level sense is selected. 0 : interrupt request bit is set to ?? at ??level when level sense is selected; this bit is set to ??at falling edge when edge sense is selected. 1 : interrupt request bit is set to ?? at ??level when level sense is selected; this bit is set to ??at rising edge when edge sense is selected. 0 0 0 : level 0 (interrupt disabled) 0 0 1 : level 1 0 1 0 : level 2 0 1 1 : level 3 1 0 0 : level 4 1 0 1 : level 5 1 1 0 : level 6 1 1 1 : level 7 b7 b6 b5 b4 b3 b2 b1 b0 int 0 to int 2 interrupt control registers (addresses 7d 16 to 7f 16 ) bit 4 interrupt request bit (note) 2 1 0 bit name at reset 0 rw functions b2 b1 b0 0 : no interrupt requested 1 : interrupt requested interrupt priority level select bits 3 rw rw rw rw rw 0 0 0 0 polarity select bit 0 : edge sense 1 : level sense 7, 6 5 rw 0 undefined level sense/edge sense select bit nothing is assigned. 7.3 interrupt control b7 b6 b5 b4 b3 b2 b1 b0 dma0 to dma3, a-d conversion, uart0 and 1 transmit, uart0 and 1 receive, timers a0 to a4, timers b0 to b2 interrupt control registers (addresses 6c 16 to 7c 16 ) bit 7 to 4 interrupt request bit 2 1 0 bit name at reset 0 rw functions 0 0 0 : level 0 (interrupt disabled) 0 0 1 : level 1 0 1 0 : level 2 0 1 1 : level 3 1 0 0 : level 4 1 0 1 : level 5 1 1 0 : level 6 1 1 1 : level 7 b2 b1 b0 0 : no interrupt requested 1 : interrupt requested interrupt priority level select bits 3 rw rw rw rw undefined 0 0 0 nothing is assigned.
7721 group users manual 7C7 interrupts 7.3.1 interrupt disable flag (i) all maskable interrupts can be disabled by this flag. when this flag is set to 1, all maskable interrupts are disabled; when this flag is cleared to 0, those interrupts are enabled. because this flag is set to 1 at reset, clear this flag to 0 when enabling interrupts. 7.3.2 interrupt request bit when an interrupt request occurs, this bit is set to 1. this bit remains set to 1 until the interrupt request is accepted; it is cleared to 0 when the interrupt request is accepted. this bit can also be set to 0 or 1 by software. ____ ____ the int i interrupt request bit (i = 0 to 2) is ignored when the int i interrupt is used with level sense. 7.3.3 interrupt priority level select bits and processor interrupt priority level (ipl) the interrupt priority level select bits are used to determine the priority level of each interrupt. when an interrupt request occurs, its interrupt priority level is compared with the processor interrupt priority level (ipl). the requested interrupt is enabled only when the comparison result meets the following condition. accordingly, an interrupt can be disabled by setting its interrupt priority level to 0. each interrupt priority level > processor interrupt priority level (ipl) table 7.3.1 lists the setting of interrupt priority level, and table 7.3.2 lists the interrupt enabled level corresponding to ipl contents. the interrupt disable flag (i), interrupt request bit, interrupt priority level select bits, and processor interrupt priority level (ipl) are independent of one another; they do not affect one another. interrupt requests are accepted only when the following conditions are satisfied. ?interrupt disable flag (i) = 0 ?interrupt request bit = 1 ?interrupt priority level > processor interrupt priority level (ipl) 7.3 interrupt control
7721 group users manual interrupts 7C8 b0 0 1 0 1 0 1 0 1 b2 0 0 0 0 1 1 1 1 table 7.3.1 setting of interrupt priority level b1 0 0 1 1 0 0 1 1 level 0 (interrupt disabled) level 1 level 2 level 3 level 4 level 5 level 6 level 7 low high 7.3 interrupt control interrupt priority level interrupt priority level select bits priority ipl 2 0 0 0 0 1 1 1 1 enabled interrupt priority level enable level 1 and above interrupts. enable level 2 and above interrupts. enable level 3 and above interrupts. enable level 4 and above interrupts. enable level 5 and above interrupts. enable level 6 and level 7 interrupts. enable only level 7 interrupt. disable all maskable interrupts. ipl 1 0 0 1 1 0 0 1 1 ipl 0 0 1 0 1 0 1 0 1 table 7.3.2 interrupt enabled level corresponding to ipl contents ipl 0 : bit 8 in processor status register (ps) ipl 1 : bit 9 in processor status register (ps) ipl 2 : bit 10 in processor status register (ps)
7721 group users manual 7C9 interrupts 7.4 interrupt priority level when the interrupt disable flag (i) = 0 (interrupts enabled) and more than one interrupt request is detected at the same sampling timing, which means a timing to check whether an interrupt request exists or not, they are accepted in order of priority levels. in other words, the interrupt request with the highest priority level is accepted first. among a total of 23 interrupt sources, the user can set the desired priority levels for 20 interrupt sources except software interrupts (zero division and brk instruction interrupts) and the watchdog timer interrupt. use the interrupt priority level select bits to set their priority levels. priority levels of reset, which is handled as the interrupt request with the highest priority, and the watchdog timer interrupt are set by hardware. figure 7.4.1 shows the interrupt priority set by hardware. note that software interrupts are not affected by the interrupt priority levels. whenever the instruction is executed, a program certainly branches to the interrupt routine. 7.4 interrupt priority level watchdog timer reset 20 interrupt sources except software interrupts and watchdog timer interrupt the user can set the desired priority levels inside of the dotted line. priority levels determined by hardware high low priority level fig. 7.4.1 interrupt priority level set by hardware
7721 group users manual interrupts 7C10 7.5 interrupt priority level detection circuit the interrupt priority level detection circuit selects the interrupt with the highest priority level when more than one interrupt request occurs at the same sampling timing. figure 7.5.1 shows the interrupt priority level detection circuit. 7.5 interrupt priority level detection circuit fig. 7.5.1 interrupt priority level detection circuit interrupt with the highest priority level interrupt priority level level 0 (initial value) a-d conversion uart1 transmit uart1 receive uart0 transmit uart0 receive timer b2 timer b1 timer b0 timer a4 timer a3 timer a2 timer a1 timer a0 int 2 int 1 int 0 ipl processor interrupt priority level interrupt disable flag (i) watchdog timer interrupt reset accepting of interrupt request interrupt priority level dma1 dma3 dma2 dma0
7721 group users manual 7C11 interrupts the following explains the operation of the interrupt priority detection circuit using figure 7.5.2. the interrupt priority level of a requested interrupt (y in figure 7.5.2) is compared with the resultant priority level which is sent from the preceding comparator (x in figure 7.5.2); the interrupt with the higher priority level is sent to the next comparator (z in figure 7.5.2). (initial comparison value of x is 0.) for an interrupt which is not requested, the comparison is not performed and the priority level which is sent from the preceding comparator is forwarded to the next comparator as it is. when the two priority levels are found the same by comparison, the priority level which is sent from the preceding comparator is forwarded to the next comparator. accordingly, when the same priority level is set by software, the interrupt priority levels are handled as follows: dma3 > dma2 > dma1 > dma0 > a-d conversion > uart1 transmit > uart1 receive > uart0 transmit > uart0 receive > timer b2 > timer b1 > timer b0 > timer a4 > timer a3 > timer a2 > timer a1 > timer ____ ____ ____ a0 > int 2 > int 1 > int 0 among the multiple interrupt requests sampled at the same time, one request with the highest priority level is detected by the above comparison. then, this highest interrupt priority level is compared with the processor interrupt priority level (ipl). when this interrupt priority level is higher than the processor interrupt priority level (ipl) and the interrupt disable flag (i) is 0, the interrupt request is accepted. a interrupt request which is not accepted here is held until it is accepted or its interrupt request bit is cleared to 0 by software. the interrupt priority is detected when the cpu fetches an op code, which is called the cpus op-code fetch cycle. however, when an op-code fetch cycle starts during detection of an interrupt priority, a new interrupt priority detection does not start. (refer to figure 7.6.1. ) since the state of the interrupt request bit and interrupt priority levels are latched during the interrupt priority detection, even if they change, the interrupt priority detection is performed for the previous state before the change occurred. the interrupt priority level is detected when the cpu fetches an op code. therefore, in the following execution or states, after the execution or state is terminated, no interrupt request is accepted until the cpu fetches the op code of the next instruction. ?execution of an instruction which requires many cycles, such as the mvn or mvp instruction ?during dram refreshment ?during hold state ?during dma transfer 7.5 interrupt priority level detection circuit y x z comparator (priority level comparison) l when x y then z = x l when x y then z = y interrupt source y x : priority level sent from the preceding comparator (highest priority at this point) y : priority level of interrupt source y z : highest priority at this point time fig. 7.5.2 interrupt priority level detection model
7721 group users manual interrupts 7C12 7.6 interrupt priority level detection time when the interrupt priority level detection time has passed after sampling starts, an interrupt request is accepted. the interrupt priority level detection time can be selected by software. figure 7.6.1 shows the interrupt priority level detection time. usually, select 2 cycles of f as the interrupt priority level detection time. 7.6 interrupt priority level detection time (2) interrupt priority level detection time op-code fetch cycle sampling pulse (a) 7 cycles (b) 4 cycles (c) 2 cycles interrupt priority level detection time (note) note: the pulse resides when 2 cycles of is selected. b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 0 1 1 0 1 1 processor mode register 0 (address 5e 16 ) processor mode bits software reset bit must be fixed to 0. clock 1 output select bit 7 cycles of [(a) shown below] 4 cycles of [(b) shown below] 2 cycles of [(c) shown below] interrupt priority detection time select bits do not select. (1) interrupt priority detection time select bits b5, b4 wait bit fig. 7.6.1 interrupt priority level detection time
7721 group users manual interrupts 7C13 7.7 sequence from acceptance of interrupt request until execution of interrupt routine the sequence from the acceptance of interrupt request until the execution of the interrupt routine is described below. when an interrupt request is accepted, the interrupt request bit of the accepted interrupt is cleared to 0. and then, the interrupt processing starts from the cycle just after the completion of the instruction which was executed at accepting the interrupt request. figure 7.7.1 shows the sequence from acceptance of interrupt request to execution of interrupt routine. after execution of an instruction at accepting the interrupt request is completed, an intack (interrupt acknowledge) sequence is executed, and a branch is made to the start address of the interrupt routine allocated in addresses 0 16 to ffff 16 . the intack sequence is automatically performed in the following order. the contents of the program bank register (pg) just before performing the intack sequence are pushed onto stack. the contents of the program counter (pc) just before performing the intack sequence are pushed onto stack. a the contents of the processor status register (ps) just before performing the intack sequence is pushed onto stack. ? the interrupt disable flag (i) is set to 1. ? the interrupt priority level of the accepted interrupt is set into the processor interrupt priority level (ipl). ? the contents of the program bank register (pg) are cleared to 00 16 , and the contents of the interrupt vector address are set into the program counter (pc). performing the intack sequence requires at least 13 cycles of internal clock f . figure 7.7.2 shows the intack sequence timing. after the intack sequence is completed, the instruction execution starts from the start address of the interrupt routine. 7.7 sequence from acceptance of interrupt request until execution of interrupt routine @ @ : interrupt priority level detection time interrupt request occurs. interrupt request is accepted. instruction 1 instruction 2 intack sequence instructions in interrupt routine interrupt response time time @ time from the occurrence of an interrupt request until the instruction execution which is in progress at that time is completed. time from when execution of an instruction next to begins (note) until the instruction execution which is in progress at completion of interrupt priority level detection. note: at this time, detection of interrupt priority level begins. a time required to execute the intack sequence (13 cycles of at minimum) a fig. 7.7.1 sequence from acceptance of interrupt request until execution of interrupt routine
7721 group users manual interrupts 7C14 7.7 sequence from acceptance of interrupt request until execution of interrupt routine fig. 7.7.2 intack sequence timing (at minimum) [s] h l when stack pointer (s)s contents are even and no wait pg pc h 00 00 00 00 00 00 00 00 00 00 ([s]C1) h ff 16 ad h pc h ps h ff 16 d h a p a h interrupt disable flag (i) internal clock cpu pc l pg ps l xx 16 d l ad h ad l pc l 00 xx 16 a l ad l 00 [s] l intack sequence op-code op-code : not used [s] xx 16 ad h ad l : contents of stack pointer (s) : low-order 8 bits of vector address : contents of vector address (high-order address) : contents of vector address (low-order address) cpu a p a h a l d h d l ([s]C2) h ([s]C3) h ([s]C4) h ([s]C5) h ([s]C5) h ([s]C1) l ([s]C2) l ([s]C3) l ([s]C4) l ([s]C5) l ([s]C5) l : cpu standard clock : high-order 8 bits of cpu internal address bus : middle-order 8 bits of cpu internal address bus : low-order 8 bits of cpu internal address bus : cpu internal data bus for odd address : cpu internal data bus for even address 7.7.1 change in ipl at acceptance of interrupt request when an interrupt request is accepted, the processor interrupt priority level (ipl) is replaced with the interrupt priority level of the accepted interrupt. this results in easy control of the processing for multiple interrupts. (refer to section 7.9 multiple interrupts. ) at reset or when a watchdog timer interrupt or a software interrupt is accepted, a value listed in table 7.7.1 is set into the ipl. table 7.7.1 change in ipl at acceptance of interrupt request interrupts reset watchdog timer zero division brk instruction other interrupts change in ipl level 0 (000 2 ) is set. level 7 (111 2 ) is set. not changed. not changed. accepted interrupt priority level is set.
7721 group users manual interrupts 7C15 7.7.2 push operation for registers the push operation for registers performed in the intack sequence depends on whether the contents of the stack pointer (s) at acceptance of an interrupt request are even or odd. when the contents of the stack pointer (s) are even, the contents of the program counter (pc) and the processor status register (ps) are simultaneously pushed in a unit of 16 bits. when the contents of the stack pointer (s) are odd, each of these registers is pushed in a unit of 8 bits. figure 7.7.3 shows the push operation for registers. in the intack sequence, only the contents of the program bank register (pg), program counter (pc), and processor status register (ps) are pushed onto the stack area. the other necessary registers must be pushed by software at the start of the interrupt routine. by using the psh instruction, all cpu registers except the stack pointer (s) can be pushed. 7.7 sequence from acceptance of interrupt request until execution of interrupt routine fig. 7.7.3 push operation for registers pushed in 3 times. a pushed in a unit of 16 bits. pushed in a unit of 16 bits. (1) when contents of stack pointer (s) are even low-order byte of processor status register (ps l ) program bank register (pg) address [s] ?4 (even) [s] ?3 (odd) [s] ?2 (even) [s] ?1 (odd) [s] (even) order for push [s] ?5 (odd) address [s] ?4 (odd) [s] ?3 (even) [s] ?2 (odd) [s] ?1 (even) [s] (odd) a ? ? pushed in a unit of 8 bits. order for push pushed in 5 times. [s] ?5 (even) high-order byte of processor status register (ps h ) low-order byte of program counter (pc l ) high-order byte of program counter (pc h ) (2) when contents of stack pointer (s) are odd low-order byte of processor status register (ps l ) program bank register (pg) high-order byte of processor status register (ps h ) low-order byte of program counter (pc l ) high-order byte of program counter (pc h ) ] [s] is an initial address that the stack pointer (s) indicates when an interrupt request is accepted. the s? contents become ?s] ?5?after all of the above registers are pushed.
7721 group users manual interrupts 7C16 7.8 return from interrupt routine when the rti instruction is executed at the end of the interrupt routine, the contents of the program bank register (pg), program counter (pc), and processor status register (ps) which were pushed onto the stack area just before the intack sequence, are automatically pulled. after this, the control returns to the original routine. and then, the suspended processing, which was in progress before the acceptance of the interrupt request, is resumed. before the rti instruction is executed, pull registers which were pushed by software in the interrupt routine, using the pul instruction, etc. 7.9 multiple interrupts just after a branch is made to an interrupt routine, the following occur: ?interrupt disable flag (i) = 1 (interrupts are disabled) ?interrupt request bit of accepted interrupt = 0 ?processor interrupt priority level (ipl) = interrupt priority level of accepted interrupt accordingly, as long as the ipl remains unchanged, an interrupt request whose priority level is higher than that of the interrupt which is in progress can be accepted by clearing the interrupt disable flag (i) to 0 in an interrupt routine. in this way, multiple interrupts are processed. figure 7.9.1 shows the processing for multiple interrupts. an interrupt request which has not been accepted because its priority level is lower is held. when the rti instruction is executed, the interrupt priority level of the routine which was in progress at acceptance of an interrupt request is pulled into the ipl. therefore, if the following relationship is satisfied when interrupt priority level detection is performed next, the held interrupt request is accepted. held interrupt requests priority level > processor interrupt priority level (ipl) 7.8 return from interrupt routine, 7.9 multiple interrupts
7721 group users manual interrupts 7C17 7.9 multiple interrupts fig. 7.9.1 processing for multiple interrupts main routine reset i = 1 ipl = 0 i = 0 interrupt 1 i = 1 ipl = 3 i = 0 i = 1 ipl = 5 rti i = 0 ipl = 3 rti i = 0 ipl = 0 i = 1 ipl = 2 rti i = 0 ipl = 0 interrupt 1 interrupt priority level=3 this request cannot be accepted because its priority level is lower than the interrupt 1s one. interrupt request generated nesting time : they are automatically set. : they must be set by software. i : interrupt disable flag ipl : processor interrupt priority level multiple interrupts interrupt 2 interrupt priority level=5 interrupt 3 interrupt priority level=2 interrupt 2 interrupt 3 interrupt 3 the instruction in the main routine is not executed.
7721 group users manual interrupts 7C18 ____ 7.10 external interrupts (int i interrupt) ____ an external interrupt request occurs by an input signal to the int i (i = 0 to 2) pin. the occurrence factor of the interrupt request can be selected by the level sense/edge sense select bit and the polarity select bit (bits 5 and 4 at addresses 7d 16 to 7f 16 ) shown in figure 7.10.1. table 7.10.1 lists the occurrence factor of ____ int i interrupt request. ____ ____ when using p10 0 /int 0 to p10 2 /int 2 pins as input pins of external interrupts, set the corresponding bits at address 18 16 (port p10 direction register) to 0. (refer to figure 7.10.2. ) ____ the signals input to the int i pin require h- or l- level width of 250 ns or more, independent of f(x in ). ____ ____ additionally, even when using the pins p10 0 /int 0 to p10 2 /int 2 as the input pins of external interrupts, the user can obtain the pins state by reading bits 0 to 2 at address 16 16 (port p10 register). note: when selecting an input signals falling or l level as the occurrence factor of an interrupt request, make sure that the input signal is held l for 250 ns or more. when selecting an input signals rising or h level as that, make sure that the input signal is held h for 250 ns or more. ___ 7.10 external interrupts (int i interrupt) ___ table 7.10.1 occurrence factor of int i interrupt request b4 0 1 0 1 b5 0 0 1 1 ___ int i interrupt request occurrence factor ___ ___ the int i interrupt request occurs by detecting the state of pin int i all the time. therefore, when the user ___ ___ does not use the int i interrupt, set the int i interrupts priority level to level 0. ___ interrupt request occurs at the falling edge of a signal input to pin int i (edge sense). ___ interrupt request occurs at the rising edge of a signal input to pin int i (edge sense). ___ interrupt request occurs when pin int i is at h level (level sense). ___ interrupt request occurs when pin int i is at l level (level sense).
7721 group users manual interrupts 7C19 ___ 7.10 external interrupts (int i interrupt) note: the interrupt request bits of int 0 to int 2 interrupts are invalid when the level sense is selected. 0 : interrupt request bit is set to ?? at ??level when level sense is selected; this bit is set to ??at falling edge when edge sense is selected. 1 : interrupt request bit is set to ?? at ??at level when level sense is selected; this bit is set to ??at rising edge when edge sense is selected. 0 0 0 : level 0 (interrupt disabled) 0 0 1 : level 1 0 1 0 : level 2 0 1 1 : level 3 1 0 0 : level 4 1 0 1 : level 5 1 1 0 : level 6 1 1 1 : level 7 b7 b6 b5 b4 b3 b2 b1 b0 int 0 to int 2 interrupt control registers (addresses 7d 16 to 7f 16 ) bit 4 interrupt request bit (note) 2 1 0 bit name at reset 0 rw functions b2 b1 b0 0 : no interrupt requested 1 : interrupt requested interrupt priority level select bits 3 rw rw rw rw rw 0 0 0 0 polarity select bit 0 : edge sense 1 : level sense 7, 6 5 rw 0 undefined level sense/edge sense select bit nothing is assigned. ___ fig. 7.10.1 structure of int i (i=0 to 2) interrupt control register bit corresponding pin functions 0 1 2 3 4 5 6 7 int 0 pin ma 8 pin port p10 direction register (address 18 16 ) b1 b0 b2 b3 b4 b5 b6 b7 at reset rw 0 0 0 0 0 0 0 0 rw rw rw rw rw rw rw rw 0 : input mode 1 : output mode when using a pin as an input pin for an external interrupt,clear the corresponding bit to ?. : bits 3 to 7 are not used for external interrupts. int 1 pin int 2 pin tc pin cas pin ras pin ma 9 pin fig. 7.10.2 relationship between port p10 direction register and input pins of external interrupt
7721 group users manual interrupts 7C20 ___ 7.10 external interrupts (int i interrupt) ____ 7.10.1 functions of int i interrupt request bit (1) functions when edge sense is selected the interrupt request bit has the same functions as that of an internal interrupt. that is, when an interrupt request occurs, the interrupt request bit is set to 1 and retains this state until the interrupt request is accepted. when this bit is cleared to 0 by software, the interrupt request is cancelled; when this bit is set to 1 by software, the interrupt request can be generated. (2) functions when level sense is selected ___ the int i interrupt request bit is ignored. ___ ___ interrupt requests continuously occur while the level of the int i pin is the valid level ] 1 ; when the int i ___ pins level changes from the valid level to the invalid level ] 2 before the int i interrupt request is accepted, this interrupt request is not retained. (refer to figure 7.10.4. ) valid level ] 1 : this means the level selected by the polarity select bit (bit 4 at addresses 7d 16 to 7f 16 ) invalid level ] 2 : this means the reversed level of valid level int i pin edge detection circuit interrupt request level sense/edge sense select bit data bus interrupt request bit 0 1 ___ fig. 7.10.3 int i interrupt request first interrupt routine int i pin level valid invalid main routine interrupt request is accepted. return to main routine. second interrupt routine third interrupt routine main routine when the int i pins level changes to the invalid level before an interrupt request is accepted, the interrupt request is not retained. ____ fig. 7.10.4 occurrence of int i interrupt request when level sense is selected
7721 group users manual interrupts 7C21 ___ 7.10 external interrupts (int i interrupt) ___ 7.10.2 switching of int i interrupt request occurrence factor ___ when the int i interrupt request occurrence factor is switched in one of the following ways, the interrupt request bit may be set to 1: ?switching the level sense to the edge sense ?switching polarity therefore, after this switching, make sure to clear the interrupt request bit to 0. figure 7.10.5 shows an ____ example of the switching procedure for the int i interrupt request occurrence factor. clear the level sense/edge sense select bit to ?. ( edge sense is selected. ) clear the interrupt request bit to ?. set the polarity select bit. clear the interrupt request bit to ?. (2) switching polarity (1) switching level sense to edge sense set the interrupt priority level to one of levels 1? or clear the interrupt disable flag (i) to ?. (int i interrupt request is acceptable.) set the interrupt priority level to level 0 or set the interrupt disable flag (i) to ?.? (int i interrupt is disabled. ) note: the above settings must be done separately. multiple settings must not be done at the same time, in other words, they must not be done only by 1 instruction. set the interrupt priority level to level 0 or set the interrupt disable flag (i) to ?.? (int i interrupt is disabled. ) set the interrupt priority level to one of levels 1? or clear the interrupt disable flag (i) to ?. (int i interrupt request is acceptable.) ___ fig. 7.10.5 example of switching procedure for int i interrupt request occurrence factor
7721 group users manual interrupts 7C22 b4 0 1 0 1 fig. 7.11.1 program example to reserve time required for change of interrupt priority level table 7.11.1 correspondence between number of instructions to be inserted in figure 7.11.1 and interrupt priority detection time select bits 7.11 precautions for interrupts 7.11 precautions for interrupts when changing the interrupt priority level select bits (bits 0 to 2 at addresses 6c 16 to 7f 16 ), 2 to 7 cycles of f are required until the interrupt priority level is changed. therefore, when the interrupt priority level of a certain interrupt source is repeatedly changed in a very short time, which consists of a few instructions, it is necessary to reserve the time required for the change by software. figure 7.11.1 shows a program example to reserve the time required for the change. note that the time required for the change depends on the contents of the interrupt priority detection time select bits (bits 4 and 5 at address 5e 16 ). table 7.11.1 lists the correspondence between the number of instructions inserted in figure 7.11.1 and the interrupt priority detection time select bits. interrupt priority detection time select bits (note) interrupt priority level detection time 7 cycles of f 4 cycles of f 2 cycles of f do not select. b5 0 0 1 1 number of inserted nop instructions 4 or more 2 or more 1 or more note: we recommend [b5 = 1, b4 = 0]. ; write instruction for the interrupt priority level select bits ; inserted nop instruction (note) ; ; ; write instruction for the interrupt priority level select bits note: except the write instruction for address xx , any instruction which has the same cycles as the nop instruction can also be inserted. for the number of inserted nop instructions, refer to ?able 7.11.1. xx: any of 6c to 7f : ldm.b #0xh, 00xxh nop nop nop ldm.b #0xh, 00xxh : 16
chapter 8 timer a 8.1 overview 8.2 block description 8.3 timer mode [precautions for timer mode] 8.4 event counter mode [precautions for event counter mode] 8.5 one-shot pulse mode [precautions for one-shot pulse mode] 8.6 pulse width modulation (pwm) mode [precautions for pulse width modulation (pwm) mode]
7721 group users manual timer a 8.1 overview 8C2 8.1 overview timer a consists of five counters, timers a0 to a4, each equipped with a 16-bit reload function. timers a0 to a4 operate independently of one another. timer a has four operating modes listed below. timers a0 and a1 operate in the timer mode only. timers a2 to a4 have selective four operating modes listed below. (1) timer mode (timers a0 to a4) the timer counts an internally generated count source. for timers a2 to a4, the following functions can be used in this mode: ?gate function ?pulse output function (2) event counter mode (timers a2 to a4) the timer counts an external signal. the following functions can be used in this mode: ?pulse output function ?two-phase pulse signal processing function (3) one-shot pulse mode (timers a2 to a4) the timer outputs a pulse which has an arbitrary width once. (4) pulse width modulation (pwm) mode (timers a2 to a4) timer outputs pulses which have an arbitrary width in succession. the counter functions as one of the following pulse width modulators: ?16-bit pulse width modulator ?8-bit pulse width modulator in this chapter, timer ai (i = 0 to 4) indicates timers a0 to a4. timer aj (j = 2 to 4) indicates timers a2 to a4; this is applies when the timer as input/output pins are used etc. (hereafter, input/output pins are called i/o pins.)
timer a 7721 group users manual 8C3 8.2 block description 8.2 block description figure 8.2.1 shows the block diagram of timer a. explanation of registers relevant to timer a is described below. data bus (odd) data bus (even) f 2 f 16 f 64 f 512 count source select bits timer mode one-shot pulse mode pwm mode polarity switching timer mode (gate function) event counter mode trigger count start bit countdown up-down bit (low-order 8 bits) (high-order 8 bits) timer ai reload register (16) timer ai counter (16) timer ai interrupt request bit countup/countdown switching (always ?ount down?except for event counter mode) toggle f.f. pulse output function select bit taj in taj out i = 0?, j = 2? fig. 8.2.1 block diagram of timer a
timer a 7721 group users manual 8C4 8.2 block description 8.2.1 counter and reload register (timer ai register) each of timer ai counter and reload register consists of 16 bits. countdown in the counter is performed each time the count source is input. in the event counter mode, it can also function as an up-counter. the reload register is used to store the initial value of the counter. when a counter underflow or overflow occurs, the reload registers contents are reloaded into the counter. a value is set to the counter and reload register by writing the value to the timer ai register. table 8.2.1 lists the memory assignment of the timer ai register. the value written into the timer ai register while counting is not in progress is set to the counter and reload register. the value written into the timer ai register while counting is in progress is set only to the reload register. in this case, the reload registers updated contents are transferred to the counter at the next reload time. the value obtained when reading out the timer ai register varies according to the operating mode. table 8.2.2 lists reading from and writing to the timer ai register. table 8.2.2 reading from and writing to timer ai register write written only to reload register. written to both of the counter and reload register. operating mode timer mode event counter mode one-shot pulse mode pulse width modulation (pwm) mode note: at reset, the contents of the timer ai register are undefined. notes 1: also refer to [precautions for timer mode] and [precautions for event counter mode]. 2: when reading from and writing to the timer ai register, perform it in a unit of 16 bits. read counter value is read out. ( note 1 ) undefined value is read out. table 8.2.1 memory assignment of timer ai register timer ai register high-order byte low-order byte timer a0 register address 47 16 address 46 16 timer a1 register address 49 16 address 48 16 timer a2 register address 4b 16 address 4a 16 timer a3 register address 4d 16 address 4c 16 timer a4 register address 4f 16 address 4e 16
timer a 7721 group users manual 8C5 8.2 block description 8.2.2 count start register this register is used to start and stop counting. each bit of this register corresponds to each timer. figure 8.2.2 shows the structure of the count start register. fig. 8.2.2 structure of count start register bit timer b2 count start bit timer b1 count start bit timer b0 count start bit timer a4 count start bit timer a3 count start bit timer a2 count start bit timer a1 count start bit timer a0 count start bit bit name at reset 0 0 0 0 0 0 0 0 rw functions b7 b6 b5 b4 b3 b2 b1 b0 count start register (address 40 16 ) 0 : stop counting 1 : start counting rw rw rw rw rw rw rw rw 0 1 2 3 4 5 6 7 : bits 5 to 7 are not used for timer a.
timer a 7721 group users manual 8C6 8.2 block description 8.2.3 timer ai mode register figure 8.2.3 shows the structure of the timer ai mode register. the operating mode select bits are used to select the operating mode of timer ai. bits 2 to 7 have different functions according to the operating mode. these bits are described in the paragraph of each operating mode. fig. 8.2.3 structure of timer ai mode register bit 7 5 4 3 1 bit name at reset 0 0 0 0 0 0 0 0 rw functions b7 b6 b5 b4 b3 b2 b1 b0 timer ai mode register (i = 0 to 4) (addresses 56 16 to 5a 16 ) 0 0 : timer mode 0 1 : event counter mode 1 0 : one-shot pulse mode 1 1 : pulse width modulation (pwm) mode b1 b0 these bits have different functions according to the operating mode. operating mode select bits 6 2 0 rw rw rw rw rw rw rw rw
timer a 7721 group users manual 8C7 8.2 block description 8.2.4 timer ai interrupt control register figure 8.2.4 shows the structure of the timer ai interrupt control register. for details about interrupts, refer to chapter 7. interrupts. fig. 8.2.4 structure of timer ai interrupt control register (1) interrupt priority level select bits (bits 2 to 0) these bits select a timer ai interrupts priority level. when using timer ai interrupts, select one of the priority levels (1 to 7). when a timer ai interrupt request occurs, its priority level is compared with the processor interrupt priority level (ipl). the requested interrupt is enabled only when its priority level is higher than the ipl. (however, this applies when the interrupt disable flag (i) = 0.) to disable timer ai interrupts, set these bits to 000 2 (level 0). (2) interrupt request bit (bit 3) this bit is set to 1 when a timer ai interrupt request occurs. this bit is automatically cleared to 0 when the timer ai interrupt request is accepted. this bit can be set to 1 or cleared to 0 by software. b7 b6 b5 b4 b3 b2 b1 b0 timer ai interrupt control register (i = 0 to 4) (addresses 75 16 to 79 16 ) bit 7 to 4 interrupt request bit 2 1 0 bit name at reset 0 rw functions 0 0 0 : level 0 (interrupt disabled) 0 0 1 : level 1 0 1 0 : level 2 0 1 1 : level 3 1 0 0 : level 4 1 0 1 : level 5 1 1 0 : level 6 1 1 1 : level 7 b2 b1 b0 0 : no interrupt requested 1 : interrupt requested interrupt priority level select bits 3 rw rw rw rw undefined 0 0 0 nothing is assigned. low level high level
timer a 7721 group users manual 8C8 8.2 block description 8.2.5 port p5 direction register the i/o pins of timers a2 to a4 are multiplexed with port p5. when using these pins as timer ajs input pins, set the corresponding bits of the port p5 direction register to 0 to set these port pins for the input mode. when used as timer ajs output pins, these pins are forcibly set to the output pins of timer aj regardless of the direction registerss contents. figure 8.2.5 shows the relationship between the port p5 direction register and the timer ajs i/o pins. bit bit name functions 0 1 2 3 4 5 6 7 ta2 out pin ta3 out pin ta3 in pin 0 : input mode 1 : output mode when using these pins as timer aj s input pins, set the corresponding bits to ?. port p5 direction register (address d 16 ) b1 b0 b2 b3 b4 b5 b6 b7 ta2 in pin at reset rw 0 0 0 0 0 0 0 0 rw rw rw rw rw rw rw rw : bits 6 and 7 are not used for timer a. ta4 out pin tb0 in pin tb1 in pin ta4 in pin fig. 8.2.5 relationship between port p5 direction register and timer ajs i/o pins
timer a 7721 group users manual 8C9 8.3 timer mode 8.3 timer mode in this mode, the timer counts an internally generated count source. (refer to table 8.3.1. ) figure 8.3.1 shows the structures of the timer ai mode register and timer ai register in the timer mode. table 8.3.1 specifications of timer mode 1 (n + 1) item count source count operation division ratio count start condition count stop condition interrupt request occurrence timing taj in pins function taj out pins function read from timer ai register write to timer ai register specifications f 2 , f 16 , f 64 , or f 512 ? countdown ? when a counter underflow occurs, reload registers contents are reloaded, and counting continues. when the count start bit is set to 1. when the count start bit is cleared to 0. when a counter underflow occurs. programmable i/o port or gate input programmable i/o port or pulse output counter value can be read out. l while counting is stopped when a value is written to the timer ai register, it is written to both of the reload register and counter. l while counting is in progress when a value is written to the timer ai register, it is written only to the reload register. (transferred to the counter at the next reload timing.) n : timer ai registers set value
timer a 7721 group users manual 8C10 8.3 timer mode b7 b0 b7 b0 (b15) (b8) timer a0 register (addresses 47 16 , 46 16 ) timer a1 register (addresses 49 16 , 48 16 ) timer a2 register (addresses 4b 16 , 4a 16 ) timer a3 register (addresses 4d 16 , 4c 16 ) timer a4 register (addresses 4f 16 , 4e 16 ) functions bit at reset rw 15 to 0 these bits can be set to 0000 16 to ffff 16 . assuming that the set value = n, the counter divides the count source frequency by (n + 1). when reading, the register indicates the counter value. undefined rw note: read from or write to this register in a unit of 16 bits. gate function select bits pulse output function select bit 1 operating mode select bits bit name functions b7 b6 b5 b4 b3 b2 b1 b0 timer aj mode register (j = 2 to 4) (addresses 58 16 to 5a 16 ) 0 0 : timer mode 0 : no pulse output (taj out pin functions as a programmable i/o port.) 1 : pulse output (taj out pin functions as a pulse output pin.) 0 0 : f 2 0 1 : f 16 1 0 : f 64 1 1 : f 512 b7 b6 count source select bits b1 b0 b4 b3 0 0 0 0 : no gate function 0 1 : (taj in pin functions as a prog- rammable i/o port.) 1 0 : counter counts only while taj in pins input signal is at l level. 1 1 : counter counts only while taj in pins input signal is at h level. bit 4 at reset rw 0 2 0 rw 0 rw 0 rw 3 0 rw 0 rw 5 0 rw 6 7 0 rw 0 rw 0 fix this bit to 0 in timer mode. bit 5 4 3 1 bit name at reset 0 0 0 0 0 0 rw functions b7 b6 b5 b4 b3 b2 b1 b0 timer a0 mode register (address 56 16 ) timer a1 mode register (address 57 16 ) fix these bits to 0. 2 0 rw rw rw rw rw rw 000000 0 0 : f 2 0 1 : f 16 1 0 : f 64 1 1 : f 512 b7 b6 count source select bits 6 7 0 rw 0 rw fig. 8.3.1 structures of timer ai mode register and timer ai register in timer mode
timer a 7721 group users manual 8C11 8.3 timer mode 8.3.1 setting for timer mode figures 8.3.2 and 8.3.3 show an initial setting example for registers relevant to the timer mode. note that when using interrupts, set up to enable the interrupts. for details, refer to section chapter 7. interrupts. fig. 8.3.2 initial setting example for registers relevant to timer mode (1) note : the counter divides the count source frequency by (n + 1). setting division ratio b7 b0 can be set to ?000 16 ?to ?fff 16 ?(n). (b15) (b8) b7 b0 timer a0 register (addresses 47 16 , 46 16 ) timer a1 register (addresses 49 16 , 48 16 ) timer a2 register (addresses 4b 16 , 4a 16 ) timer a3 register (addresses 4d 16 , 4c 16 ) timer a4 register (addresses 4f 16 , 4e 16 ) continue to figure 8.3.3 on next page. b7 b0 pulse output function select bit 0: no pulse output. 1: pulses output. 00 selecting timer mode and each function timer ai mode register (i = 0 to 4) (addresses 56 16 to 5a 16 ) count source select bits 0 0: f 2 0 1: f 16 1 0: f 64 1 1: f 512 b7 b6 gate function select bits 0 0: 0 1: 1 0: gate function (counter counts only while taj in pin? input signal is at ??level.) 1 1: gate function (counter counts only while taj in pin? input signal is at ??level.) b4 b3 selection of timer mode no gate function 0 note : for timers a0 and a1, set bits 0 to 5 to ?.
timer a 7721 group users manual 8C12 8.3 timer mode aaaa aaaa aaaa count starts setting count start bit to ?. b7 b0 count start register (address 40 16 ) timer a0 count start bit timer a1 count start bit timer a2 count start bit timer a3 count start bit timer a4 count start bit setting interrupt priority level b7 b0 timer ai interrupt control register (i = 0 to 4) (addresses 75 16 to 79 16 ) interrupt priority level select bits when using interrupts, set these bits to one of levels 1 to 7. when disabling interrupts, set these bits to level 0. from preceding figure 8.3.2 . setting port p5 direction register b7 b0 port p5 direction register (address d 16 ) ta2 in pin ta3 in pin ta4 in pin when gate function is selected, set the bit corresponding to the taj in pin to 0. fig. 8.3.3 initial setting example for registers relevant to timer mode (2)
timer a 7721 group users manual 8C13 8.3 timer mode 8.3.2 count source in the timer mode, the count source select bits (bits 6 and 7 at addresses 56 16 to 5a 16 ) select the count source. table 8.3.2 lists the count source frequency. table 8.3.2 count source frequency b6 0 1 0 1 count source select bits b7 0 0 1 1 count source f 2 f 16 f 64 f 512 f(x in ) = 8 mhz 4 mhz 500 khz 125 khz 15625 hz count source frequency f(x in ) = 25 mhz 12.5 mhz 1.5625 mhz 390.625 khz 48.8281 khz f(x in ) = 16 mhz 8 mhz 1 mhz 250 khz 31250 hz
timer a 7721 group users manual 8C14 8.3 timer mode 8.3.3 operation in timer mode when the count start bit is set to 1, the counter starts counting of the count source. when a counter underflow occurs, the reload registers contents are reloaded, and counting continues. a the timer ai interrupt request bit is set to 1 at the underflow in . the interrupt request bit remains set to 1 until the interrupt request is accepted or the interrupt request bit is cleared to 0 by software. figure 8.3.4 shows an example of operation in the timer mode. stops counting. restarts counting. ffff 16 n 0000 16 time count start bit timer ai interrupt request bit counter contents (hex.) n = reload register? contents cleared to ??when interrupt request is accepted or cleared by software. set to ??by software. starts counting. 1 / f i 5 (n+1) fi = frequency of count source (f 2 , f 16 , f 64 , f 512 ) cleared to ??by software. set to ??by software. fig. 8.3.4 example of operation in timer mode (without pulse output and gate functions)
timer a 7721 group users manual 8C15 8.3 timer mode 8.3.4 selectable functions the following describes the selectable gate function for timers a2 to a4 and pulse output function. (1) gate function the gate function is selected by setting the gate function select bits (bits 4 and 3 at addresses 58 16 to 5a 16 ) to 10 2 or 11 2 . the gate function makes it possible to start or stop counting depending on the taj in pins input signal. table 8.3.3 lists the count valid levels. figure 8.3.5 shows an example of operation with the gate function selected. when selecting the gate function, set the port p5 direction registers bits which correspond to the taj in pin for the input mode. additionally, make sure that the taj in pins input signal has a pulse width equal to or more than two cycles of the count source. table 8.3.3 count valid levels gate function select bits b4 1 1 b3 0 1 count valid level (duration while counter counts) while taj in pins input signal is at l level while taj in pins input signal is at h level note: the counter does not count while the taj in pins input signal is not at the count valid level. fig. 8.3.5 example of operation selecting gate function ffff 16 n 0000 16 time starts counting. n = reload registers contents counter contents (hex.) stops counting. set to 1 by software. count start bit taj in pins input signal count valid level timer aj interrupt request bit cleared to 0 when interrupt request is accepted or cleared by software. the counter counts when the count start bit = 1 and the taj in pins input signal is at the count valid level. the counter stops counting while the taj in pins input signal is not at the count valid level, and the counter value is retained. invalid level
timer a 7721 group users manual 8C16 8.3 timer mode (2) pulse output function the pulse output function is selected by setting the pulse output function select bit (bit 2 at addresses 58 16 to 5a 16 ) to 1. when this function is selected, the taj out pin is forcibly set for the pulse output pin regardless of the corresponding bits of the port p5 direction register. the taj out pin outputs pulses of which polarity is inverted each time a counter underflow occurs. when the count start bit (address 40 16 ) is 0 (count stopped), the taj out pin outputs l level. figure 8.3.6 shows an example of operation with the pulse output function selected. fig. 8.3.6 example of operation selecting pulse output function ffff 16 n 0000 16 time count start bit timer aj interrupt request bit counter contents (hex.) n = reload register? contents cleared to ??when interrupt request is accepted or cleared by software. set to ??by software. starts counting. pulse output from taj out pin set to ??by software. cleared to ??by software. starts counting. restarts counting.
timer a 7721 group users manual 8C17 8.3 timer mode [precautions for timer mode] by reading the timer ai register, the counter value can be read out at any timing. however, if the timer ai register is read at the reload timing shown in figure 8.3.7, the value ffff 16 is read out. if reading is performed in the period from when a value is set into the timer ai register with the counter stopped until the counter starts counting, the set value is correctly read out. fig. 8.3.7 reading timer ai register 210 n n ?1 counter value (hex.) 21 0 ffff n ?1 read value (hex.) reload time n = reload register? contents
timer a 7721 group users manual 8C18 8.4 event counter mode 8.4 event counter mode in this mode, the timer counts an external signal. (refer to tables 8.4.1 and 8.4.2. ) timers a2 to a4 can be used in this mode. figure 8.4.1 shows the structures of the timer aj mode register and timer aj register in the event counter mode. table 8.4.1 specifications of event counter mode (when not using two-phase pulse signal processing function) specifications l external signal input to the taj in pin l the count sources valid edge can be selected from the falling edge and the rising edge by software. l countup or countdown can be switched by external signal or software. l when a counter overflow or underflow occurs, reload registers contents are reloaded, and counting continues. l for countdown l for countup when the count start bit is set to 1. when the count start bit is cleared to 0. when a counter overflow or underflow occurs. count source input programmable i/o port, pulse output, or countup/countdown switch signal input counter value can be read out. l while counting is stopped when a value is written to the timer aj register, it is written to both of the reload register and counter. l while counting is in progress when a value is written to the timer aj register, it is written only to the reload register. (transferred to the counter at the next reload time.) item count source count operation division ratio count start condition count stop condition interrupt request occurrence timing taj in pins function taj out pins function read from timer aj register write to timer aj register 1 (n + 1) 1 (ffff 16 C n + 1) n : timer aj registers set value
timer a 7721 group users manual 8C19 8.4 event counter mode table 8.4.2 specifications of event counter mode (when using two-phase pulse signal processing function) item count source count operation division ratio count start condition count stop condition interrupt request occurrence timing taj in , taj out pin function read from timer aj register write to timer aj register 1 (n + 1) specifications external signal (two-phase pulse) input to the taj in or taj out pin l countup or countdown can be switched by external signal (two- phase pulse). l when a counter overflow or underflow occurs, reload registers contents are reloaded, and counting continues. l for countdown l for countup when the count start bit is set to 1. when the count start bit is cleared to 0. when a counter overflow or underflow occurs. two-phase pulse input counter value can be read out. l while counting is stopped when a value is written to the timer aj register, it is written to both of the reload register and counter. l while counting is in progress when a value is written to the timer aj register, it is written only to the reload register. (transferred to the counter at the next reload time.) 1 (ffff 16 C n + 1) n : timer aj registers set value
timer a 7721 group users manual 8C20 8.4 event counter mode fig. 8.4.1 structures of timer aj mode register and timer aj register in event counter mode b7 b6 b5 b4 b3 b2 b1 b0 001 bit up-down switching factor select bit count polarity select bit bit name these bits are invalid in event counter mode. fix this bit to ??in event counter mode. 7 functions 0 : counts at falling edge of external signal 1 : counts at rising edge of external signal 0 : contents of up-down register 1 : input signal to taj out pin at reset 0 0 0 0 0 rw pulse output function select bit operating mode select bits 1 0 : no pulse output (taj out pin functions as a programmable i/o port.) 1 : pulse output (taj out pin functions as a pulse output pin.) 0 1 : event counter mode b1 b0 0 0 0 55 0 2 rw rw 3 4 5 6 rw rw rw rw rw rw timer aj mode register (j = 2 to 4) (addresses 58 16 to 5a 16 ) b7 b0 b7 b0 (b15) (b8) timer a2 register (addresses 4b 16 , 4a 16 ) timer a3 register (addresses 4d 16 , 4c 16 ) timer a4 register (addresses 4f 16 , 4e 16 ) rw 15 to 0 bit functions at reset rw these bits can be set to ?000 16 ?to ?fff 16 . assuming that the set value = n, the counter divides the count source frequency by (n + 1) during countdown, or by (ffff 16 ?n + 1) during countup. when reading, the register indicates the counter value. undefined note: read from or write to this register in a unit of 16 bits.
timer a 7721 group users manual 8C21 8.4 event counter mode 8.4.1 setting for event counter mode figures 8.4.2 and 8.4.3 show an initial setting example for registers relevant to the event counter mode. note that when using interrupts, set up to enable the interrupts. for details, refer to chapter 7. interrupts. fig. 8.4.2 initial setting example for registers relevant to event counter mode (1) [ the counter divides the count source frequency by (n + 1) when counting down, or by (ffff 16 C n + 1) when counting up. continue to figure 8.4.3 on next page. b7 b0 01 0 selecting event counter mode and each function timer aj mode register (j = 2 to 4) (addresses 58 16 to 5a 16 ) pulse output function select bit 0: no pulse output 1: pulse output count polarity select bit 0: counts at falling edge of external signal. 1: counts at rising edge of external signal. up-down switching factor select bit 0: contents of up-down register 1: input signal to taj out pin 5 : it may be either 0 or 1. selection of event counter mode setting division ratio b7 b0 can be set to 0000 16 to ffff 16 (n). (b15) (b8) b7 b0 timer a2 register (addresses 4b 16 , 4a 16 ) timer a3 register (addresses 4d 16 , 4c 16 ) timer a4 register (addresses 4f 16 , 4e 16 ) 55 b7 b0 setting up-down register up-down register (address 44 16 ) timer a2 up-down bit timer a3 up-down bit timer a4 up-down bit timer a2 two-phase pulse signal processing select bit timer a3 two-phase pulse signal processing select bit timer a4 two-phase pulse signal processing select bit set the corresponding up-down bit when the contents of the up-down register are selected as the up-down switching factor. set the corresponding bit to 1 when the two-phase pulse signal processing function is selected for timers a2 to a4. 0: countdown 1: countup 0: two-phase pulse signal processing function disabled 1: two-phase pulse signal processing function enabled 00
timer a 7721 group users manual 8C22 8.4 event counter mode fig. 8.4.3 initial setting example for registers relevant to event counter mode (2) aaaaaaaaaaaa aaaaaaaaaaaa aaaaaaaaaaaa aaaaaaaaaaaa aaaaaaaaaaaa aaaaaaaaaaaa aaaaa setting the count start bit to ? b7 b0 count start register (address 40 16 ) timer a2 count start bit timer a3 count start bit timer a4 count start bit aaa aaa aaa count starts from preceding figure 8.4.2 . aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa setting port p5 direction register b7 b0 port p5 direction register (address d 16 ) ta2 in pin ta3 out pin ta3 in pin ta4 out pin ta4 in pin clear the bit corresponding to the taj in pin to ?. when selecting the taj out pin? input signal as the up-down switching factor, set the bit corresponding to the taj out pin to ?. when selecting the two-phase pulse signal processing function, set the bit corresponding to the taj out pin to ?. ta2 out pin aaaaaaaaaaaaaa aaaaaaaaaaaaaa aaaaaaaaaaaaaa aaaaaaaaaaaaaa aaaaaaaaaaaaaa aaaaaaaaaaaaaa setting interrupt priority level b7 b0 timer aj interrupt control register (j = 2 to 4) (addresses 77 16 to 79 16 ) interrupt priority level select bits when using interrupts, set these bits to one of levels 1 to 7. when disabling interrupts, set these bits to level 0.
timer a 7721 group users manual 8C23 8.4 event counter mode 8.4.2 operation in event counter mode when the count start bit is set to 1, the counter starts counting of the count sources valid edges. when a counter underflow or overflow occurs, the reload registers contents are reloaded, and counting continues. a the timer aj interrupt request bit is set to 1 at the underflow or overflow in . the interrupt request bit remains set to 1 until the interrupt request is accepted or the interrupt request bit is cleared to 0 by software. figure 8.4.4 shows an example of operation in the event counter mode. fig. 8.4.4 example of operation in event counter mode (without pulse output and two-phase pulse signal processing functions) timer aj interrupt request bit ffff 16 n 0000 16 time count start bit counter contents (hex.) n = reload register? contents cleared to ?? when interrupt request is accepted or cleared by software. set to ??by software. starts counting. up-down bit note: the above applies when the up-down bit? contents are selected as the up-down switching factor (i.e., up-down switching factor select bit = ??). set to ??by software.
timer a 7721 group users manual 8C24 8.4 event counter mode 8.4.3 switching between countup and countdown the up-down register (address 44 16 ) or the input signal from the taj out pin is used to switch countup from and to countdown. this switching is performed by the up-down bit when the up-down switching factor select bit (bit 4 at addresses 58 16 to 5a 16 ) is 0, and by the input signal from the taj out pin when the up-down switching factor select bit is 1. when the switching between countup and countdown is set while counting is in progress, this switching is actually performed when the count sources next valid edge is input. (1) switching by up-down bit countdown is performed when the up-down bit is 0, and countup is performed when the up-down bit is 1. figure 8.4.5 shows the structure of the up-down register. (2) switching by taj out pins input signal countdown is performed when the taj out pins input signal is at l level, and countup is performed when the taj out pins input signal is at h level. when using the taj out pins input signal to switch countup from and to countdown, set the port p5 direction registers bit which corresponds to the taj out pin for the input mode. fig. 8.4.5 structure of up-down register bit bit name at reset 0 0 0 0 0 rw functions b7 b6 b5 b4 b3 b2 b1 b0 up-down register (address 44 16 ) 0 0 0 timer a4 up-down bit timer a3 up-down bit timer a2 up-down bit fix these bits to ?. timer a2 two-phase pulse signal processing select bit (note) timer a3 two-phase pulse signal processing select bit (note) timer a4 two-phase pulse signal processing select bit (note) 0 : countdown 1 : countup this function is valid when the contents of the up-down register is selected as the up- down switching factor. 0 : two-phase pulse signal processing function disabled 1 : two-phase pulse signal processing function enabled when not using the two-phase pulse signal processing function, set the bit to ?. the value is ??at reading. note: use the ldm or sta instruction for writing to bits 5 to 7. 0 1 2 3 4 5 6 7 rw rw rw rw rw wo wo wo 00
timer a 7721 group users manual 8C25 8.4 event counter mode 8.4.4 selectable functions the following describes the selectable pulse output, and two-phase pulse signal processing functions. (1) pulse output function the pulse output function is selected by setting the pulse output function select bit (bit 2 at addresses 58 16 to 5a 16 ) to 1. when this function is selected, the taj out pin is forcibly set for the pulse output pin regardless of the corresponding bit of the port p5 direction register. the taj out pin outputs pulses of which polarity is inverted each time a counter underflow or overflow occurs. (refer to figure 8.3.6. ) when the count start bit (address 40 16 ) is 0 (count stopped), the taj out pin outputs l level.
timer a 7721 group users manual 8C26 8.4 event counter mode (2) two-phase pulse signal processing function the two-phase pulse signal processing function is selected by setting the two-phase pulse signal processing select bits (bits 5 to 7 at address 44 16 ) to 1. (refer to figure 8.4.5.) figure 8.4.6 shows the timer aj mode registers when the two-phase pulse signal processing function is selected. for timers with the two-phase pulse signal processing function selected, the timer counts two kinds of pulses of which phases differ by 90 degrees. there are two types of the two-phase pulse signal processing: normal processing and quadruple processing. in timers a2 and a3, normal processing is performed; in timer a4, quadruple processing is performed. for some bits of the port p5 direction register correspond to pins used for two-phase pulse input, set these bits for the input mode. fig. 8.4.6 timer aj mode registers when two-phase pulse signal processing function is selected l normal processing countup is performed at the rising edges input to the tak in pin when the phase has the relationship that the tak in pins input signal level goes from l to h while the tak out (k = 2 and 3) pins input signal is at h level. countdown is performed at the falling edges input to the tak in pin when the phase has the relationship that the tak in pins input signal level goes from h to l while the tak out pins input signal is at h level. (refer to figure 8.4.7. ) fig. 8.4.7 normal processing 1 00001 timer a2 mode register (address 58 16 ) timer a3 mode register (address 59 16 ) timer a4 mode register (address 5a 16 ) b7 b6 b5 b4 b3 b2 b1 b0 5 : it may be either ??or ?. 55 tak out tak in (k=2, 3) up count +1 +1 +1 ? ? ? counted up counted up counted up counted down counted down counted down
timer a 7721 group users manual 8C27 8.4 event counter mode l quadruple processing countup is performed at all rising and falling edges input to the ta4 out and ta4 in pins when the phase has the relationship that the ta4 in pins input signal level goes from l to h while the ta4 out pins input signal is at h level. countdown is performed at all rising and falling edges input to the ta4 out and ta4 in pins when the phase has the relationship that the ta4 in pins input signal level goes from h to l while the ta4 out pins input signal is at h level. (refer to figure 8.4.8. ) table 8.4.3 lists the relationship between the input signals to the ta4 out and ta4 in pins and count operation when the quadruple processing is selected. table 8.4.3 relationship between input signals to ta4 out and ta4 in pins and count operation when quadruple processing is selected fig. 8.4.8 quadruple processing ta4 out ta4 in +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 counted up at all edges ? ? ? ? ? ? ? ? ? ? counted up at all edges counted down at all edges counted down at all edges input signal to ta4 out pin input signal to ta4 in pin h level l level rising edge falling edge h level l level rising edge falling edge rising edge falling edge l level h level falling edge rising edge h level l level up-count down-count
timer a 7721 group users manual 8C28 8.4 event counter mode [precautions for event counter mode] 1. while counting is in progress, by reading the timer aj register, the counter value can be read out at any timing. however, if the timer aj register is read at the reload timing shown in figure 8.4.9, the value ffff 16 (at an underflow) or 0000 16 (at an overflow) is read out. if reading is performed in the period from when a value is set into the timer aj register with the counter stopped until the counter starts counting, the set value is correctly read out. fig. 8.4.9 reading timer aj register 2. the taj out pin is used for all functions listed below. accordingly, only one of these functions can be selected for each timer. ?switching between countup and countdown by taj out pins input signal ?pulse output function ?two-phase pulse signal processing function 210 n n ?1 counter value (hex.) 210 ffff n ?1 read value (hex.) reload time n = reload register? contents (1) for countdown fffd fffe ffff n n + 1 fffd fffe ffff 0000 n + 1 (2) for countup counter value (hex.) read value (hex.) reload time n = reload register? contents
timer a 7721 group users manual 8C29 8.5 one-shot pulse mode 8.5 one-shot pulse mode in this mode, the timer outputs a pulse which has an arbitrary width once. (refer to table 8.5.1. ) timers a2 to a4 can be used in this mode. when a trigger occurs, the timer outputs h level from the taj out pin for an arbitrary time. figure 8.5.1 shows the structures of the timer aj mode register and timer aj register in the one-shot pulse mode. table 8.5.1 specifications of one-shot pulse mode specifications f 2 , f 16 , f 64 , or f 512 l countdown l when the counter value becomes 0000 16 , reload registers con- tents are reloaded, and counting stops. l if a trigger occurs during counting, reload registers contents are reloaded, and counting continues. l when a trigger occurs. ( note ) l internal or external trigger can be selected by software. l when the counter value becomes 0000 16 , l when the count start bit is cleared to 0 when counting stops. programmable i/o port or trigger input one-shot pulse output an undefined value is read out. l while counting is stopped when a value is written to the timer aj register, it is written to both of the reload register and counter. l while counting is in progress when a value is written to the timer aj register, it is written only to the reload register. (transferred to the counter at the next reload time.) item count source count operation output pulse width (h) count start condition count stop condition interrupt request occurrence timing taj in pins function taj out pins function read from timer aj register write to timer aj register n f i [s] n : timer aj registers set value note: the trigger is generated with the count start bit = 1.
timer a 7721 group users manual 8C30 8.5 one-shot pulse mode fig. 8.5.1 structures of timer aj mode register and timer aj register in one-shot pulse mode trigger select bits fix this bit to 1 in one-shot pulse mode. 1 ?@ bit name functions b7 b6 b5 b4 b3 b2 b1 b0 timer aj mode register (j = 2 to 4) (addresses 58 16 to 5a 16 ) 1 0 : one-shot pulse mode 7 0 0 : f 2 0 1 : f 16 1 0 : f 64 1 1 : f 512 b7 b6 count source select bits b1 b0 b4 b3 fix this bit to 0 in one-shot pulse mode. 10 1 0 0 : writing 1 to one-shot start register 0 1 : (taj in pin functions as a prog- rammable i/o port.) 1 0 : falling edge of taj in pins input signal 1 1 : rising edge of taj in pins input signal bit at reset 0 0 0 0 0 0 0 0 rw 0 4 0 2 3 5 6 rw rw rw rw rw rw rw rw operating mode select bits b7 b0 b7 b0 (b15) (b8) timer a2 register (addresses 4b 16 , 4a 16 ) timer a3 register (addresses 4d 16 , 4c 16 ) timer a4 register (addresses 4f 16 , 4e 16 ) rw 15 to 0 these bits can be set to 0001 16 to ffff 16 . assuming that the set value = n, the h level width of the one-shot pulse output from the taj out pin is expressed as follows : undefined f i : frequency of count source (f 2 , f 16 , f 64 , or f 512 ) wo n f i . note: use the ldm or sta instruction for writing to this register. read from or write to this register in a unit of 16 bits. functions bit at reset
timer a 7721 group users manual 8C31 8.5 one-shot pulse mode 8.5.1 setting for one-shot pulse mode figures 8.5.2 and 8.5.3 show an initial setting example for registers relevant to the one-shot pulse mode. note that when using interrupts, set up to enable the interrupts. for details, refer to chapter 7. interrupts. fig. 8.5.2 initial setting example for registers relevant to one-shot pulse mode (1) continue to figure 8.5.3 . aaaaaaaaaaaaaa aaaaaaaaaaaaaa aaaaaaaaaaaaaa aaaaaaaaaaaaaa aaaaaaaaaaaaaa setting interrupt priority level b7 b0 timer aj interrupt control register (j = 2 to 4) (addresses 77 16 to 79 16 ) interrupt priority level select bits when using interrupts, set these bits to one of levels 1 to 7. when disabling interrupts, set these bits to level 0. aaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaa b7 b0 10 0 selecting one-shot pulse mode and each function timer aj mode register (j = 2 to 4) (addresses 58 16 to 5a 16 ) 1 trigger select bits 0 0 : 0 1 : 1 0 : falling edge of taj in pin? input signal: external trigger 1 1 : rising edge of taj in pin? input signal: external trigger b4 b3 count source select bits 0 0 : f 2 0 1 : f 16 1 0 : f 64 1 1 : f 512 b7 b6 selection of one-shot pulse mode aaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaa setting ??level width of one-shot pulse b7 b0 can be set to ?001 16 ?to ?fff 16 ?(n). (b15) (b8) b7 b0 timer a2 register (addresses 4b 16 , 4a 16 ) timer a3 register (addresses 4d 16 , 4c 16 ) timer a4 register (addresses 4f 16 , 4e 16 ) ??level width = writing ??to one-shot start bit: internal trigger fi note . n fi: frequency of count source
timer a 7721 group users manual 8C32 8.5 one-shot pulse mode aaa aaa aaa count starts trigger generated aaaaa aaaaa trigger input to taj in pin when internal trigger is selected when external trigger is selected from preceding figure 8.5.2 . aaaaaaaaaa aaaaaaaaaa aaaaaaaaaa aaaaaaaaaa aaaaaaaaaa b7 b0 one-shot start register (address 42 16 ) setting one-shot start bit to ? timer a2 one-shot start bit timer a3 one-shot start bit timer a4 one-shot start bit aa aa a a aa aa aaaaaaaaaa aaaaaaaaaa aaaaaaaaaa aaaaaaaaaa setting count start bit to ? b7 b0 timer a2 count start bit timer a3 count start bit timer a4 count start bit count start register (address 40 16 ) aaaaaaaaa aaaaaaaaa aaaaaaaaa aaaaaaaaa aaaaaaaaa b7 b0 port p5 direction register (address d 16 ) setting port p5 direction register ta2 in pin ta3 in pin ta4 in pin set the corresponding bit to ?. aaaaaaaaaa aaaaaaaaaa aaaaaaaaaa aaaaaaaaaa aaaaaaaaaa setting count start bit to ? b7 b0 timer a2 count start bit timer a3 count start bit timer a4 count start bit count start register (address 40 16 ) 00 fig. 8.5.3 initial setting example for registers relevant to one-shot pulse mode (2)
timer a 7721 group users manual 8C33 8.5 one-shot pulse mode 8.5.2 count source in the one-shot pulse mode, the count source select bits (bits 6 and 7 at addresses 58 16 to 5a 16 ) select the count source. table 8.5.2 lists the count source frequency. table 8.5.2 count source frequency b6 0 1 0 1 count source select bits b7 0 0 1 1 count source f 2 f 16 f 64 f 512 f(x in ) = 8 mhz 4 mhz 500 khz 125 khz 15625 hz count source frequency f(x in ) = 25 mhz 12.5 mhz 1.5625 mhz 390.625 khz 48.8281 khz f(x in ) = 16 mhz 8 mhz 1 mhz 250 khz 31250 hz
timer a 7721 group users manual 8C34 8.5 one-shot pulse mode 8.5.3 trigger the counter is enabled for counting when the count start bit (address 40 16 ) is set to 1. the counter starts counting when a trigger is generated after counting has been enabled. an internal or external trigger can be selected as that trigger. an internal trigger is selected when the trigger select bits (bits 4 and 3 at addresses 58 16 to 5a 16 ) are 00 2 or 01 2 ; an external trigger is selected when the bits are 10 2 or 11 2 . if a trigger is generated during counting, the reload registers contents are reloaded and the counter continues counting. if generating a trigger during counting, make sure that a certain time which is equivalent to one cycle of the timers count source or more has passed between the previously generated trigger and a new trigger. (1) when selecting internal trigger a trigger is generated when writing 1 to the one-shot start bit (bits 2 to 4 at address 42 16 ). figure 8.5.4 shows the structure of the one-shot start register. (2) when selecting external trigger a trigger is generated at the falling edge of the taj in pins input signal when bit 3 at addresses 58 16 to 5a 16 is 0, or at its rising edge when bit 3 is 1. when using an external trigger, set the port p5 direction registers bits which correspond to the taj in pins for the input mode. fig. 8.5.4 structure of one-shot start register . bit 7 to 5 nothing is assigned. timer a4 one-shot start bit timer a3 one-shot start bit timer a2 one-shot start bit bit name at reset 0 0 undefined 0 0 0 rw functions b7 b6 b5 b4 b3 b2 b1 b0 one-shot start register (address 42 16 ) 1 : start outputting one-shot pulse (valid when internal trigger is selected.) the value is 0 at reading. 0 1 2 3 4 wo wo wo wo wo C 00 fix these bits to 0. the value is 0 at reading.
timer a 7721 group users manual 8C35 8.5 one-shot pulse mode 8.5.4 operation in one-shot pulse mode when the one-shot pulse mode is selected with the operating mode select bits, the taj out pin outputs l level. when the count start bit is set to 1, the counter is enabled for counting. after that, counting starts when a trigger is generated. a when the counter starts counting, the taj out pin outputs h level. ? when the counter value becomes 0000 16 , the output from the taj out pin becomes l level. additionally, the reload registers contents are reloaded and the counter stops counting there. ? simultaneously with ? , the timer aj interrupt request bit is set to 1. this interrupt request bit remains set to 1 until the interrupt request is accepted or the interrupt request bit is cleared to 0 by software. figure 8.5.5 shows an example of operation in the one-shot pulse mode. when a trigger is generated after ? above, the counter and taj out pin perform the same operations beginning from again. furthermore, if a trigger is generated during counting, the counter performs countdown once after this new trigger is generated, and it continues counting with the reload registers contents reloaded. if generating a trigger during counting, make sure that a certain time which is equivalent to one cycle of the timers count source or more has passed between the previously generated trigger and a new trigger. the one-shot pulse output from the taj out pin can be disabled by clearing the timer aj mode registers bit 2 to 0. accordingly, timer aj can be also used as an internal one-shot timer that does not perform the pulse output. in this case, the taj out pin functions as a programmable i/o port.
timer a 7721 group users manual 8C36 8.5 one-shot pulse mode stops counting. starts counting. ffff 16 n 0001 16 time count start bit timer aj interrupt request bit counter contents (hex.) n = reload registers contents cleared to 0 when interrupt request is accepted or cleared by software. set to 1 by software. starts counting. taj in pin input signal one-shot pulse output from taj out pin trigger during counting 1 / f i 5 (n) note: the above applies when an external trigger (rising of taj in pins input signal) is selected. 1 / f i 5 (n+1) when the count start bit = 0 (counting stopped), the taj out pin outputs l level. when a trigger is generated during counting, the counter counts the count source (n + 1) times after a new trigger is generated. fi = frequency of count source (f 2 , f 16 , f 64 , or f 512 ) stops counting. reloaded reloaded fig. 8.5.5 example of operation in one-shot pulse mode (selecting external trigger)
timer a 7721 group users manual 8C37 8.5 one-shot pulse mode [precautions for one-shot pulse mode] 1. if the count start bit is cleared to 0 during counting, the counter becomes as follows: ?the counter stops counting, and the reload registers contents are reloaded into the counter. ?the taj out pins output level becomes l. ?the timer aj interrupt request bit is set to 1. 2. a one-shot pulse is output synchronously with an internally generated count source. accordingly, when selecting an external trigger, there will be a delay equivalent to one cycle of the count source at maximum from when a trigger is input to the taj in pin until a one-shot pulse is output. note: the above applies when an external trigger (falling edge of taj in pin? input signal) is selected. taj in pin? input signal count source trigger input starts outputting of one-shot pulse one-shot pulse output from taj out pin fig. 8.5.6 output delay in one-shot pulse output 3. when the timers operating mode is set by one of the following procedures, the timer aj interrupt request bit is set to 1. l when the one-shot pulse mode is selected after reset l when the operating mode is switched from the timer mode to the one-shot pulse mode l when the operating mode is switched from the event counter mode to the one-shot pulse mode accordingly, when using the timer aj interrupt (interrupt request bit), be sure to clear the timer aj interrupt request bit to 0 after the above setting. 4. don not set 0000 16 to the timer aj register.
timer a 7721 group users manual 8C38 8.6 pulse width modulation (pwm) mode 8.6 pulse width modulation (pwm) mode in this mode, the timer continuously outputs pulses which have an arbitrary width. (refer to table 8.6.1. ) timers a2 to a4 can be used in this mode. figure 8.6.1 shows the structures of the timer aj mode registers and timer aj registers in the pwm mode. table 8.6.1 specifications of pwm mode item count source count operation pwm period/h level width count start condition count stop condition interrupt request occurrence timing taj in pins function taj out pins function read from timer aj register write to timer aj register specifications f 2 , f 16 , f 64 , or f 512 l countdown (operating as an 8-bit or 16-bit pulse width modulator) l reload registers contents are reloaded at rising edge of pwm pulse, and counting continues. l a trigger generated during counting does not affect the counting. <16-bit pulse width modulator> <8-bit pulse width modulator> l when a trigger is generated. (note) l internal or external trigger can be selected by software. when the count start bit is cleared to 0. at falling edge of pwm pulse programmable i/o port or trigger input pwm pulse output an undefined value is read out. l while counting is stopped when a value is written to the timer aj register, it is written to both of the reload register and counter. l while counting is in progress when a value is written to the timer aj register, it is written only to the reload register. (transferred to the counter at the next reload time.) period = (2 16 C1) fi [s] n fi h level width = [s] period = (m + 1)(2 8 C1) fi h level width = [s] n(m + 1) fi n : timer aj registers set value [s] m : timer aj register low-order 8 bits set value n : timer aj register high-order 8 bits set value note: the trigger is generated with the count start bit = 1.
timer a 7721 group users manual 8C39 8.6 pulse width modulation (pwm) mode fig. 8.6.1 structures of timer aj mode registers and timer aj registers in pwm mode b7 b6 b5 b4 b3 b2 b1 b0 timer aj mode register (j = 2 to 4) (addresses 58 16 to 5a 16 ) 7 0 0 : f 2 0 1 : f 16 1 0 : f 64 1 1 : f 512 b7 b6 count source select bits 11 1 at reset 0 rw trigger select bits fix this bit to 1 in pwm mode. 1 operating mode select bits functions 1 1 : pwm mode b1 b0 b4 b3 16/8-bit pwm mode select bit 0 0 : writing 1 to count start register 0 1 : in pin functions as a pro- grammable i/o port.) 1 0 : falling edge of taj in pins input signal 1 1 : rising edge of taj in pins input signal 0 : 16-bit pulse width modulator 1 : 8-bit pulse width modulator 4 0 2 3 5 6 0 0 0 0 0 0 0 rw rw rw rw rw rw rw rw (b15) b7 b0 b7 b0 (b8) timer a2 register (addresses 4b 16 , 4a 16 ) timer a3 register (addresses 4d 16 , 4c 16 ) timer a4 register (addresses 4f 16 , 4e 16 ) functions bit at reset rw 7 to 0 15 to 8 undefined undefined these bits can be set to 00 16 to ff 16 . assuming that the set value = m, pwm pulses period output from the taj out pin is expressed as follows: (m + 1)(2 8 C 1) f i wo these bits can be set to 00 16 to fe 16 . assuming that the set value = n, the h level width of the pwm pulse output from the taj out pin is expressed as follows: n(m + 1) f i wo f i : frequency of count source (f 2 , f 16 , f 64 , or f 512 ) note: use the ldm or sta instruction for writing to this register. read from or write to this register in a unit of 16 bits. b7 b0 b7 b0 timer a2 register (addresses 4b 16 , 4a 16 ) timer a3 register (addresses 4d 16 , 4c 16 ) timer a4 register (addresses 4f 16 , 4e 16 ) functions bit at reset rw 15 to 0 these bits can be set to 0000 16 to fffe 16 . assuming that the set value = n, the h level width of the pwm pulse output from the taj out pin is expressed as follows: (pwm pulse period = ) undefined (b15) (b8) wo n f i f i : frequency of count source (f 2 , f 16 , f 64 , or f 512 ) note: use the ldm or sta instruction for writing to this register. read from or write to this register in a unit of 16 bits. n 16 C 1 f i bit bit name (taj
timer a 7721 group users manual 8C40 8.6 pulse width modulation (pwm) mode 8.6.1 setting for pwm mode figures 8.6.2 and 8.6.3 show an initial setting example for registers relevant to the pwm mode. note that when using interrupts, set up to enable the interrupts. for details, refer to chapter 7. interrupts. fig. 8.6.2 initial setting example for registers relevant to pwm mode (1) note: when operating as 8-bit pulse width modulator fi : frequency of count source however, if n = ?0 16 ? the pulse width modulator does not operate and the taj out pin outputs ?? level. at this time, no timer aj interrupt request occurs. b7 b0 count source select bits 0 0 : f 2 0 1 : f 16 1 0 : f 64 1 1 : f 512 11 selecting pwm mode and each function timer aj mode register (j = 2 to 4) (addresses 58 16 to 5a 16 ) b7 b6 1 16/8-bit pwm mode select bit 0 : operates as 16-bit pulse width modulator 1 : operates as 8-bit pulse width modulator continue to figure 8.6.3 . trigger select bits 0 0 : 0 1 : 1 0 : falling edge of taj in pin? input signal 1 1 : rising edge of taj in pin? input signal b3 b4 selection of pwm mode setting pwm pulse? period and ??level width b7 b0 can be set to ?000 16 ?to ?ffe 16 ?(n) (b15) (b8) b7 b0 timer a2 register (addresses 4b 16 , 4a 16 ) timer a3 register (addresses 4d 16 , 4c 16 ) timer a4 register (addresses 4f 16 , 4e 16 ) note: when operating as 16-bit pulse width modulator fi : frequency of count source however, if n = ?000 16 ? the pulse width modulator does not operate and the taj out pin outputs ??level. at this time, no timer aj interrupt request occurs. l when operating as 16-bit pulse width modulator b7 b0 can be set to ?0 16 ?to ?f 16 ?(m) (b15) (b8) b7 b0 l when operating as 8-bit pulse width modulator can be set to ?0 16 ?to ?e 16 ?(n) timer a2 register (addresses 4b 16 , 4a 16 ) timer a3 register (addresses 4d 16 , 4c 16 ) timer a4 register (addresses 4f 16 , 4e 16 ) writing ??to count start bit: internal trigger : external trigger : external trigger ??level width = period = ??level width = period = 2 16 ?1 fi n fi (m+1) (2 8 ? ) fi n(m+1) fi
timer a 7721 group users manual 8C41 8.6 pulse width modulation (pwm) mode fig. 8.6.3 initial setting example for registers relevant to pwm mode (2) aaa aaa count tt aaaa aaaa trigger input to taj in pin when external trigger is selected when internal trigger is selected from preceding figure 8.6.2. trigger generated aaaaaaaaaa aaaaaaaaaa aaaaaaaaaa aaaaaaaaaa aaaaaaaaaa b7 b0 port p5 direction register (address d 16 ) setting port p5 direction register ta2 in pin ta3 in pin ta4 in pin clear the corresponding bit to ?. aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa setting count start bit to ? b7 b0 count start register (address 40 16 ) timer a2 count start bit timer a3 count start bit timer a4 count start bit aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa setting count start bit to ? b7 b0 count start register (address 40 16 ) timer a2 count start bit timer a3 count start bit timer a4 count start bit aaaaaaaaaaaaa aaaaaaaaaaaaa aaaaaaaaaaaaa aaaaaaaaaaaaa aaaaaaaaaaaaa setting interrupt priority level b7 b0 timer aj interrupt control register (j = 2 to 4) (addresses 77 16 to 79 16 ) interrupt priority level select bits when using interrupts, set these bits to one of levels 1 to 7. when disabling interrupts, set these bits to level 0. aa aa aa aa aa aa aa aa
timer a 7721 group users manual 8C42 8.6 pulse width modulation (pwm) mode 8.6.2 count source in the pwm mode, the count source select bits (bits 6 and 7 at addresses 58 16 to 5a 16 ) select the count source. table 8.6.2 lists the count source frequency. table 8.6.2 count source frequency b6 0 1 0 1 count source select bits b7 0 0 1 1 count source f 2 f 16 f 64 f 512 f(x in ) = 8 mhz 4 mhz 500 khz 125 khz 15625 hz count source frequency f(x in ) = 25 mhz 12.5 mhz 1.5625 mhz 390.625 khz 48.8281 khz f(x in ) = 16 mhz 8 mhz 1 mhz 250 khz 31250 hz 8.6.3 trigger when a trigger is generated, the taj out pin starts outputting pwm pulses. an internal or an external trigger can be selected as that trigger. an internal trigger is selected when the trigger select bits (bits 4 and 3 at addresses 58 16 to 5a 16 ) are 00 2 or 01 2 ; an external trigger is selected when the bits are 10 2 or 11 2 . a trigger generated during outputting of pwm pulses is invalid and it does not affect the pulse output operation. (1) when selecting internal trigger a trigger is generated when 1 is written to the count start bit (address 40 16 ). (2) when selecting external trigger a trigger is generated at the falling edge of the taj in pins input signal when bit 3 at addresses 58 16 to 5a 16 is 0, or at its rising edge when bit 3 is 1. however, the trigger input is accepted only when the count start bit is 1. when using an external trigger, set the port p5 direction registers bits which correspond to the taj in pins for the input mode.
timer a 7721 group users manual 8C43 8.6 pulse width modulation (pwm) mode 8.6.4 operation in pwm mode when the pwm mode is selected with the operating mode select bits, the taj out pin outputs l level. when a trigger is generated, the counter (pulse width modulator) starts counting and the taj out pin outputs a pwm pulse ( notes 1 and 2 ). a the timer aj interrupt request bit is set to 1 each time the pwm pulse level goes from h to l. the interrupt request bit remains set to 1 until the interrupt request is accepted or the interrupt request bit is cleared to 0 by software. ? each time a pwm pulse has been output for one period, the reload registers contents are reloaded and the counter continues counting. the following explains operations of the pulse width modulator. (1) 16-bit pulse width modulator when the 16/8-bit pwm mode select bit is set to 0, the counter operates as a 16-bit pulse width modulator. figures 8.6.4 and 8.6.5 show operation examples of the 16-bit pulse width modulator. (2) 8-bit pulse width modulator when the 16/8-bit pwm mode select bit is set to 1, the counter is divided into 8-bit halves. then, the high-order 8 bits operate as an 8-bit pulse width modulator, and the low-order 8 bits operate as an 8-bit prescaler. figures 8.6.6 and 8.6.7 show operation examples of the 8-bit pulse width modulator. notes 1: if a value 0000 16 is set into the timer aj register when the counter operates as a 16-bit pulse width modulator, the pulse width modulator does not operate and the output from the taj out pin remains l level. the timer aj interrupt request does not occur. similarly, if a value 00 16 is set into the high-order 8 bits of the timer aj register when the counter operates as an 8-bit pulse width modulator, the same is performed. 2: when the counter operates as an 8-bit pulse width modulator, after a trigger is generated, the taj out pin outputs l level which has the same width as h level width of the pwm pulse, which was set. after that, the pwm pulse output starts from the taj out pin.
timer a 7721 group users manual 8C44 8.6 pulse width modulation (pwm) mode fig. 8.6.4 operation example of 16-bit pulse width modulator fig. 8.6.5 operation example of 16-bit pulse width modulator (when counter value is updated during pulse output) 1 / f i 5 (2 16 C 1) 1 / f i 5 (n) count source taj in pins input signal pwm pulse output from taj out pin note: the above applies when reload register (n) = 0003 16 and an external trigger (rising edge of taj in pins input signal) is selected. trigger is not generated by this signal. timer aj interrupt request bit cleared to 0 when interrupt request is accepted or cleared by software. fi: frequency of count source (f 2 , f 16 , f 64 , or f 512 ) when an arbitrary value is set to the timer aj register after setting 0000 16 to it, the timing at which the pwm pulse goes h depends on the timing at which the new value is set. note: the above applies when an external trigger (rising edge of taj in pins input signal) is selected. fffe 16 n 0001 16 taj in pins input signal counter contents (hex.) (1 / f i ) 5 (2 16 C1) (2 16 C1) C n (1 / f i ) 5 (2 16 C1) pwm pulse output from taj out pin 0000 16 is set to timer aj register. 2000 16 is set to timer aj register. 2000 16 fffe 16 is set to timer aj register. n = reload registers contents fi: frequency of count source (f 2 , f 16 , f 64 , or f 512 ) restarts counting. stops counting. time (1 / f i ) 5 (2 C1) 16
timer a 7721 group users manual 8C45 8.6 pulse width modulation (pwm) mode fig. 8.6.6 operation example of 8-bit pulse width modulator count source taj in pin? input signal 1 / f i 5 (m+1) 5 (2 8 ?) pwm pulse output from taj out pin note: the above applies when the reload register? high-order 8 bits (n) = ?2 16 and low-order 8 bits (m) = ?2 16 ?and an external trigger (falling edge of taj in pin input signal) is selected. timer aj interrupt request bit cleared to ??when interrupt request is accepted or cleared by software. fi: frequency of count source (f 2 , f 16 , f 64 , or f 512 ) the 8-bit prescaler counts the count source. the 8-bit pulse width modulator counts the 8-bit prescaler? underflow signal. 8-bit prescaler? underflow signal 1 / f i 5 (m+1) 5 (n) 1 / f i 5 (m+1)
timer a 7721 group users manual 8C46 8.6 pulse width modulation (pwm) mode fig. 8.6.7 operation example of 8-bit pulse width modulator (when counter value is updated during pulse output) (1 / f i ) 5 (m+1) 5 (2 8 ?) pwm pulse output from taj out pin count source taj in pin? input signal (1 / f i ) 5 (m+1) 5 (2 8 ?) (1 / f i ) 5 (m + 1) 5 (2 8 ?) 00 16 prescaler's contents (hex.) 02 16 time stops counting. 01 16 counter? contents (hex.) 04 16 0a 16 time when an arbitrary value is set to the timer aj register after setting ?0 16 ?to it, the timing at which the pwm pulse level goes ??depends on the timing at which the new value is set. ?002 16 ?is set to timer aj register. 0a02 16 is set to timer aj register. ?402 16 ?is set to timer aj register. restarts counting. note: the above applies when an external trigger (falling edge of taj in pin? input signal) is selected. fi: frequency of count source (f 2 , f 16 , f 64 , or f 512 ) m: contents of reload register? low-order 8 bits
timer a 7721 group users manual 8C47 8.6 pulse width modulation (pwm) mode [precautions for pwm mode] 1. if the count start bit is cleared to 0 while outputting pwm pulses, the counter stops counting. when the taj out pin was outputting h level at that time, the output level becomes l and the timer aj interrupt request bit is set to 1. when the taj out pin was outputting l level, the output level does not change and a timer aj interrupt request does not occur. 2. when the timers operating mode is set by one of the following procedures, the timer aj interrupt request bit is set to 1. l when the pwm mode is selected after reset l when the operating mode is switched from the timer mode to the pwm mode l when the operating mode is switched from the event counter mode to the pwm mode accordingly, when using the timer aj interrupt (interrupt request bit), be sure to clear the timer aj interrupt request bit to 0 after the above setting.
timer a 7721 group users manual 8C48 8.6 pulse width modulation (pwm) mode memorandum
chapter 9 timer b 9.1 overview 9.2 block description 9.3 timer mode [precautions for timer mode] 9.4 event counter mode [precautions for event counter mode] 9.5 pulse period/pulse width measurement mode [precautions for pulse period/pulse width measurement (pwm) mode]
timer b 7721 group users manual 9C2 9.1 overview timer b consists of three counters, timers b0 to b2, each equipped with a 16-bit reload function. timers b0 to b2 operate independently of one another. timer b has three operating modes listed below. timers b0 and b1 have selective three operating modes listed below. timer b2 operates only in the timer mode. (1) timer mode (timers b0 to b2) the timer counts an internally generated count source. (2) event counter mode (timers b0 and b1) the timer counts an external signal. (3) pulse period/pulse width measurement mode (timers b0 and b1) the timer measures an external signals pulse period or pulse width. in this chapter, timer bi (i = 0 to 2) indicates timers b0 to b2. timer bj (j = 0, 1) indicates timers b0 and b1; this is used when the timer bs input/output pins are used etc. (hereafter, input/output pins are called i/o pins.) 9.2 block description figure 9.2.1 shows the block diagram of timer b. explanation of registers relevant to timer b is described below. 9.1 overview 9.2 block description f 2 f 16 f 64 f 512 count source select bits timer mode pulse period/pulse width measurement mode polarity switching and edge pulse generating circuit event counter mode count start bit counter reset circuit data bus (odd) data bus (even) (low-order 8 bits) (high-order 8 bits) timer bi reload register (16) timer bi counter (16) timer bi interrupt request bit tbj in timer bj overflow flag (valid in pulse period/pulse width measurement mode) i = 0?, j = 0, 1 fig. 9.2.1 block diagram of timer b
7721 group users manual timer b 9C3 9.2 block description 9.2.1 counter and reload register (timer bi register) each of timer bi counter and reload register consists of 16 bits and has the following functions. (1) functions in timer mode and event counter mode countdown in the counter is performed each time the count source is input. the reload register is used to store the initial value of the counter. when a counter underflow occurs, the reload registers contents are reloaded into the counter. a value is set to the counter and reload register by writing the value to the timer bi register. table 9.2.1 lists the memory assignment of the timer bi register. the value written into the timer bi register when the counting is not in progress is set to the counter and reload register. the value written into the timer bi register when the counting is in progress is set only to the reload register. in this case, the reload registers updated contents are transferred to the counter when the next underflow occurs. the counter value is read out by reading out the timer bi register. note: when reading from or writing to the timer bi register, perform it in a unit of 16 bits. for more information about the value obtained by reading the timer bi register, refer to [precautions for timer mode] and [precautions for event counter mode]. (2) functions in pulse period/pulse width measurement mode countup in the counter is performed each time the count source is input. the reload register is used to retain the pulse period or pulse width measurement result. when a valid edge is input to the tbj in pin, the counter value is transferred to the reload register. in this mode, the value obtained by reading the timer bj register is the reload registers contents, so that the measurement result is obtained. note: when reading from the timer bj register, perform it in a unit of 16 bits. timer bi register timer b0 register timer b1 register timer b2 register low-order byte address 50 16 address 52 16 address 54 16 high-order byte address 51 16 address 53 16 address 55 16 note : at reset, the contents of the timer bi register are undefined. table 9.2.1 memory assignment of timer bi registers
timer b 7721 group users manual 9C4 9.2.2 count start register this register is used to start and stop counting. each bit of this register corresponds to each timer. figure 9.2.2 shows the structure of the count start register. 9.2 block description fig. 9.2.2 structure of count start register bit timer b2 count start bit timer b1 count start bit timer b0 count start bit timer a4 count start bit timer a3 count start bit timer a2 count start bit timer a1 count start bit timer a0 count start bit bit name at reset 0 0 0 0 0 0 0 0 rw functions b7 b6 b5 b4 b3 b2 b1 b0 count start register (address 40 16 ) 0 : stop counting 1 : start counting rw rw rw rw rw rw rw rw 0 1 2 3 4 5 6 7 : bits 0 to 4 are not used for timer b.
7721 group users manual timer b 9C5 9.2.3 timer bi mode register figure 9.2.3 shows the structure of the timer bi mode register. the operating mode select bits are used to select the operating mode of timer bi. bits 2, 3, and bits 5 to 7 have different functions according to the operating mode. these bits are described in the paragraph of each operating mode. 9.2 block description fig. 9.2.3 structure of timer bi mode register nothing is assigned. these bits have different functions according to the operating mode. 1 operating mode select bits bit name functions b7 b6 b5 b4 b3 b2 b1 b0 timer bi mode register (i = 0 to 2) (addresses 5b 16 to 5d 16 ) 0 0 : timer mode 0 1 : event counter mode 1 0 : pulse period/pulse width measurement mode 1 1 : do not select. b1 b0 bit 5 at reset rw 0 2 0 rw rw rw 6 7 note: bit 5 is invalid in the timer and event counter modes; its value is undefined at reading. 3 0 0 rw 0 C undefined 4 ro (note) undefined rw 0 rw 0 these bits have different functions according to the operating mode.
timer b 7721 group users manual 9C6 9.2.4 timer bi interrupt control register figure 9.2.4 shows the structure of the timer bi interrupt control register. for details about interrupts, refer to chapter 7. interrupts. 9.2 block description fig. 9.2.4 structure of timer bi interrupt control register (1) interrupt priority level select bits (bits 2 to 0) these bits select a timer bi interrupts priority level. when using timer bi interrupts, select one of the priority levels (1 to 7). when a timer bi interrupt request occurs, its priority level is compared with the processor interrupt priority level (ipl). the requested interrupt is enabled only when its priority level is higher than the ipl. (however, this applies when the interrupt disable bit (i) = 0.) to disable timer bi interrupts, set these bits to 000 2 (level 0). (2) interrupt request bit (bit 3) this bit is set to 1 when a timer bi interrupt request occurs. this bit is automatically cleared to 0 when the timer bi interrupt request is accepted. this bit can be set to 1 or cleared to 0 by software. b7 b6 b5 b4 b3 b2 b1 b0 bit 7 to 4 interrupt request bit 2 1 0 bit name at reset 0 rw functions 0 0 0 : level 0 (interrupt disabled) 0 0 1 : level 1 low level 0 1 0 : level 2 0 1 1 : level 3 1 0 0 : level 4 1 0 1 : level 5 1 1 0 : level 6 1 1 1 : level 7 high level b2 b1 b0 0 : no interrupt requested 1 : interrupt requested interrupt priority level select bits 3 rw rw rw rw undefined 0 0 0 nothing is assigned. timer bi interrupt control register (i = 0 to 2) (addresses 7a 16 to 7c 16 )
7721 group users manual timer b 9C7 9.2.5 port p5 direction register input pins of timer bj are multiplexed with port p5. when using these pins as timer bjs input pins, set the corresponding bits of the port p5 direction register to 0 to set these port pins for the input mode. figure 9.2.5 shows the relationship between port p5 direction register and the timer bjs input pins. 9.2 block description fig. 9.2.5 relationship between port p5 direction register and timer bjs input pins 0 1 2 3 4 5 6 7 ta2 out pin pin ta3 out pin ta4 out tb0 por t p5 direction register (address d 16 ) b1 b0 b2 b3 b4 b5 b6 b7 ta2 i i n rw 0 0 0 0 0 0 0 0 : bits 0 to 5 are not used for timer b. corresponding pin name functions bit at reset 0 : input mode 1 : output mode when using these pins as timer bj' s input pins, set the corresponding bits to "0 ." rw rw rw rw rw rw rw rw pin ta3 n pin i ta4 n pin i n pin tb1 i n pin
7721 group users manual timer b 9C8 9.3 timer mode 9.3 timer mode in this mode, the timer counts an internally generated count source. (refer to table 9.3.1. ) figure 9.3.1 shows the structures of the timer bi mode register and timer bi register in the timer mode. table 9.3.1 specifications of timer mode item count source count operation division ratio count start condition count stop condition interrupt request occurrence timing tbj in pins function read from timer bi register write to timer bi register specifications f 2 , f 16 , f 64 , or f 512 ?countdown ?when a counter underflow occurs, reload registers contents are reloaded, and counting continues. when the count start bit is set to 1. when the count start bit is cleared to 0. when a counter underflow occurs. programmable i/o port counter value can be read out. l while counting is stopped when a value is written to the timer bi register, it is written to both of the reload register and counter. l while counting is in progress when a value is written to the timer bi register, it is written only to the reload register. (transferred to the counter at the next reload time.) 1 (n + 1) n : timer bi registers set value
timer b 7721 group users manual 9C9 9.3 timer mode fig. 9.3.1 structures of timer bi mode register and timer bi register in timer mode b7 b6 b5 b4 b3 b2 b1 b0 00 bit this bit is invalid in timer mode; its value is undefined at reading. nothing is assigned. bit name count source select bits functions at reset rw these bits are invalid in timer mode. operating mode select bits 1 0 0 : timer mode b1 b0 0 5 5 0 2 rw rw 3 rw rw timer bi mode register (i = 0 to 2) (addresses 5b 16 to 5d 16 ) 5 0 0 0 undefined 4 undefined 5 6 7 0 0 : f 2 0 1 : f 16 1 0 : f 64 1 1 : f 512 b7 b6 rw 0 rw 0 ro b7 b0 b7 b0 (b15) (b8) timer b0 register (addresses 51 16 , 50 16 ) timer b1 register (addresses 53 16 , 52 16 ) timer b2 register (addresses 55 16 , 54 16 ) rw 15 to 0 bit functions at reset these bits can be set to ?000 16 ?to ?fff 16 . assuming that the set value = n, the counter divides the count source frequency by (n + 1). when reading, the register indicates the counter value. undefined rw note: read from or write to this register in a unit of 16 bits.
7721 group user?s manual timer b 9C10 9.3 timer mode 9.3.1 setting for timer mode figure 9.3.2 shows an initial setting example for registers relevant to the timer mode. note that when using interrupts, set up to enable the interr upts. for details, refer to chapter 7. interrupts. fig. 9.3.2 initial setting example for registers relevant to timer mode count starts b7 b0 count source select bits 0 0 : f 2 0 1 : f 16 1 0 : f 64 1 1 : f 512 selecting timer mode and count source timer bi mode register (i = 0 to 2) (addresses 5b 16 to 5d 16 ) setting count start bit to 1 b7 b0 count start register (address 40 16 ) timer b0 count start bit timer b1 count start bit timer b2 count start bit b7 b6 setting interrupt priority level b7 b0 timer bi interrupt control register (i = 0 to 2) (addresses 7a 16 to 7c 16 ) interrupt priority level select bits when using interrupts, set these bits to one of levels 1 to 7. when disabling interrupts, set these bits to level 0. 5 : it may be either 0 or 1. selection of timer mode note : the counter divides the count source by (n + 1). setting division ratio b7 b0 can be set to 0000 16 to ffff 16 (n). (b15) (b8) b7 b0 timer b0 register (addresses 51 16 , 50 16 ) timer b1 register (addresses 53 16 , 52 16 ) timer b2 register (addresses 55 16 , 54 16 ) 00 55 5
timer b 7721 group users manual 9C11 9.3 timer mode 9.3.2 count source in the timer mode, the count source select bits (bits 6 and 7 at addresses 5b 16 to 5d 16 ) select the count source. table 9.3.2 lists the count source frequency. table 9.3.2 count source frequency b6 0 1 0 1 count source select bits b7 0 0 1 1 count source f 2 f 16 f 64 f 512 f(x in ) = 8 mhz 4 mhz 500 khz 125 khz 15625 hz count source frequency f(x in ) = 25 mhz 12.5 mhz 1.5625 mhz 390.625 khz 48.8281 khz f(x in ) = 16 mhz 8 mhz 1 mhz 250 khz 31250 hz
7721 group users manual timer b 9C12 9.3 timer mode 9.3.3 operation in timer mode when the count start bit is set to 1, the counter starts counting of the count source. when a counter underflow occurs, the reload registers contents are reloaded, and counting continues. a the timer bi interrupt request bit is set to 1 at the underflow in . the interrupt request bit remains set to 1 until the interrupt request is accepted or the interrupt request bit is cleared to 0 by software. figure 9.3.3 shows an example of operation in the timer mode. stops counting. restarts counting. ffff 16 n 0000 16 time count start bit timer bi interrupt request bit counter contents (hex.) n = reload register? contents cleared to ??when interrupt request is accepted or cleared by software. set to ??by software. starts counting. set to ??by software. 1 / f i 5 (n+1) fi = frequency of count source (f 2 , f 16 , f 64 , f 512 ) cleared to ??by software. fig. 9.3.3 example of operation in timer mode
timer b 7721 group users manual 9C13 9.3 timer mode [precautions for timer mode] while counting is in progress, by reading the timer bi register, the counter value can be read out at any timing. however, if the timer bi register is read at the reload timing shown in figure 9.3.4, the value ffff 16 is read out. if reading is performed in the period from when a value is set into the timer bi register with the counter stopped until the counter starts counting, the set value is correctly read out. fig. 9.3.4 reading timer bi register 210 n n ?1 counter value (hex.) 210 ffff n ?1 read value (hex.) reload time n = reload register? contents
7721 group users manual timer b 9C14 9.4 event counter mode 9.4 event counter mode in this mode, the timer counts an external signal. (refer to table 9.4.1. ) figure 9.4.1 shows the structures of the timer bj mode register and the timer bj register in the event counter mode. table 9.4.1 specifications of event counter mode specifications ?external signal input to the tbj in pin ?the count sources valid edge can be selected from the falling edge, the rising edge, and both of the falling and rising edges by software. ?countdown ?when a counter underflow occurs, reload registers contents are reloaded, and counting continues. when the count start bit is set to 1. when the count start bit is cleared to 0. when a counter underflow occurs. count source input counter value can be read out. l while counting is stopped when a value is written to the timer bj register, it is written to both of the reload register and counter. l while counting is in progress when a value is written to the timer bj register, it is written only to the reload register. (transferred to the counter at the next reload time.) 1 (n + 1) n : timer bj registers set value item count source count operation division ratio count start condition count stop condition interrupt request occurrence timing tbj in pins function read from timer bj register write to timer bj register
timer b 7721 group users manual 9C15 9.4 event counter mode fig. 9.4.1 structures of timer bj mode register and timer bj register in event counter mode b7 b0 b7 b0 (b15) (b8) timer b0 register (addresses 51 16 , 50 16 ) timer b1 register (addresses 53 16 , 52 16 ) rw 15 to 0 bit functions at reset rw these bits can be set to ?000 16 ?to ?fff 16 . assuming that the set value = n, the counter divides the count source frequency by (n + 1). when reading, the register indicates the counter value. undefined note: read from or write to this register in a unit of 16 bits. 0 0 : count at falling edge of external signal 0 1 : count at rising edge of external signal 1 0 : counts at both falling and rising edges of external signal 1 1 : do not select. b7 b6 b5 b4 b3 b2 b1 b0 01 bit count polarity select bits bit name these bits are invalid in event counter mode. this bit is invalid in event counter mode; its value is undefined at reading. 7 functions at reset 0 0 0 rw operating mode select bits 1 0 1 : event counter mode b1 b0 0 0 0 55 0 2 rw rw 3 4 5 6 rw rw rw rw timer bj mode register (j = 0, 1) (addresses 5b 16 , 5c 16 ) b3 b2 nothing is assigned. 5 undefined undefined ro
7721 group users manual timer b 9C16 9.4 event counter mode 9.4.1 setting for event counter mode figure 9.4.2 shows an initial setting example for registers relevant to the event counter mode. note that when using interrupts, set up to enable the interrupts. for details, refer to chapter 7. interrupts. note : the counter divides the count source by (n + 1). setting division ratio b7 b0 can be set to 0000 16 to ffff 16 (n). (b15) (b8) b7 b0 timer b0 register (addresses 51 16 , 50 16 ) timer b1 register (addresses 53 16 , 52 16 ) count starts b7 b0 0 0 : counts at falling edge of external signal. 0 1 : counts at rising edge of external signal. 1 0 : counts at both of falling and rising edges of external signal. 1 1 : do not select. 01 selecting event counter mode and count polarity timer bj mode register (j = 0, 1) (addresses 5b 16 , 5c 16 ) setting count start bit to 1 b7 b0 count start register (address 40 16 ) timer b0 count start bit timer b1 count start bit b3 b2 setting interrupt priority level b7 b0 timer bj interrupt control register (j = 0, 1) (addresses 7a 16 , 7b 16 ) interrupt priority level select bits when using interrupts, set these bits to one of levels 1 to 7. when disabling interrupts, set these bits to level 0. setting port p5 direction register b7 b0 port p5 direction register (address d 16 ) clear the corresponding bit to 0. tb0 in pin tb1 in pin 5 5 : it may be 0 or 1. selection of event counter mode count polarity select bits 5 5 fig. 9.4.2 initial setting example for registers relevant to event counter mode
timer b 7721 group users manual 9C17 9.4 event counter mode 9.4.2 operation in event counter mode when the count start bit is set to 1, the counter starts counting of the count sources valid edges. when a counter underflow occurs, the reload registers contents are reloaded, and counting continues. a the timer bj interrupt request bit is set to 1 at the underflow in . the interrupt request bit remains set to 1 until the interrupt request is accepted or the interrupt request bit is cleared to 0 by software. figure 9.4.3 shows an example of operation in the event counter mode. stops counting. restarts counting . ffff 16 n 0000 16 time count start bit timer bj interrupt request bit counter contents (hex.) n = reload registers contents cleared to 0 when interrupt request is accepted or cleared by software. set to 1 by software. starts counting. cleared to 0 by software. set to 1 by software. fig. 9.4.3 example of operation in event counter mode
7721 group users manual timer b 9C18 9.4 event counter mode [precautions for event counter mode] while counting is in progress, by reading the timer bj register, the counter value can be read out at any timing. however, if the timer bj register is read at the reload timing shown in figure 9.4.4, the value ffff 16 is read out. if reading is performed in the period from when a value is set into the timer bj register with the counter stopped until the counter starts counting, the set value is correctly read out. fig. 9.4.4 reading timer bj register 21 0 n n ?1 counter value (hex.) 21 0 ffff n ?1 read value (hex.) reload time n = reload register? contents
timer b 7721 group users manual 9C19 9.5 pulse period/pulse width measurement mode 9.5 pulse period/pulse width measurement mode in this mode, the timer measures an external signals pulse period or pulse width. (refer to table 9.5.1. ) timers b0 and b1 can be used in this mode. figure 9.5.1 shows the structures of the timer bj mode register and timer bj register in the pulse period/pulse width measurement mode. l pulse period measurement the timer measures the pulse period of the external signal that is input to the tbj in pin. l pulse width measurement the timer measures the pulse width (l level and h level widths) of the external signal that is input to the tbj in pin. table 9.5.1 specifications of pulse period/pulse width measurement mode item count source count operation count start condition count stop condition interrupt request occurrence timing tbj in pins function read from timer bj register write to timer bj register timer bj overflow flag ] : the bit used to identify the source of an interrupt request occurrence. notes 1: no interrupt request occurs when the first valid edge is input after the counter starts counting. 2: the value read out from the timer bj register is undefined after the counter starts counting until the second valid edge is input. specifications f 2 , f 16 , f 64 , or f 512 l countup l counter value is transferred to the reload register at valid edge of measurement pulse, and counting continues after clearing the counter value to 0000 16 . when the count start bit is set to 1. when the count start bit is cleared to 0. l when valid edge of measurement pulse is input ( note 1 ). l when a counter overflow occurs (timer bj overflow flag ] is set to 1 simultaneously.) measurement pulse input the value obtained by reading timer bj register is the reload registers contents (measurement result) ( note 2 ). invalid
7721 group users manual timer b 9C20 9.5 pulse period/pulse width measurement mode fig. 9.5.1 structures of timer bj mode register and timer bj register in pulse period/pulse width measurement mode measurement mode select bits 1 operating mode select bits bit name functions b7 b6 b5 b4 b3 b2 b1 b0 timer bj mode register (j = 0, 1) (addresses 5b 16 , 5c 16 ) 1 0 : pulse period/pulse width measurement mode 7 0 0 : f 2 0 1 : f 16 1 0 : f 64 1 1 : f 512 b7 b6 count source select bits b1 b0 b3 b2 nothing is assigned. 0 1 0 0 : pulse period measurement (interval between falling edges of measurement pulse) 0 1 : pulse period measurement (interval between rising edges of measurement pulse) 1 0 : pulse width measurement (interval from a falling edge to a rising edge, and from a rising edge to a falling edge of measurement pulse) 1 1 : do not select. bit at reset undefined 0 rw 4 0 2 3 6 rw rw rw rw C rw rw 5 0 0 0 timer bj overflow flag (note) 0 : no overflow 1 : overflowed undefined ro 0 0 note: the timer bj overflow flag is cleared to 0 at the next count timing of the count source when a value is written to the timer bj mode register with the count start bit = 1. b7 b0 b7 b0 (b15) (b8) timer b0 register (addresses 51 16 , 50 16 ) timer b1 register (addresses 53 16 , 52 16 ) rw 15 to 0 the measurement result of pulse period or pulse width is read out. undefined ro note: read from this register in a unit of 16 bits. functions bit at reset
timer b 7721 group users manual 9C21 9.5 pulse period/pulse width measurement mode 9.5.1 setting for pulse period/pulse width measurement mode figure 9.5.2 shows an initial setting example for registers relevant to the pulse period/pulse width measurement mode. note that when using interrupts, set up to enable the interrupts. for details, refer to chapter 7. interrupts. fig. 9.5.2 initial setting example for registers relevant to pulse period/pulse width measurement mode aaaa aaaa aaaa aaaa count starts b7 b0 measurement mode select bits 10 selecting pulse period/pulse width measurement mode and each function timer bj mode register (i = 0, 1) (addresses 5b 16 , 5c 16 ) setting count start bit to ? b7 b0 count start register (address 40 16 ) timer b0 count start bit timer b1 count start bit b3 b2 count source select bits b7 b6 timer bj overflow flag (note) 0: no overflow 1: overflowed setting port p5 direction register b7 b0 port p5 direction register (address d 16 ) clear the corresponding bit to ?. tb0 in pin tb1 in pin 0 0 : pulse period measurement (interval between falling edges of measurement pulse) 0 1 : pulse period measurement (interval between rising edges of measurement pulse) 1 0 : pulse width measurement 1 1 : do not select. 0 0 : f 2 0 1 : f 16 1 0 : f 64 1 1 : f 512 note: the timer bj overflow flag is a read-only bit. this bit is undefined after reset. when a value is written to the timer bj mode register with the count start bit = ?,?this bit is cleared to ??at the next count timing of the count source. setting interrupt priority level b7 b0 timer bj interrupt control register (j = 0, 1) (addresses 7a 16 , 7b 16 ) interrupt priority level select bits when using interrupts, set these bits to one of levels 1 to 7. when disabling interrupts, set these bits to level 0. selection of pulse period/pulse width measurement mode
7721 group users manual timer b 9C22 9.5 pulse period/pulse width measurement mode 9.5.2 count source in the pulse period/pulse width measurement mode, the count source select bits (bits 6 and 7 at addresses 5b 16 and 5c 16 ) select the count source. table 9.5.2 lists the count source frequency. table 9.5.2 count source frequency b6 0 1 0 1 count source select bits b7 0 0 1 1 count source f 2 f 16 f 64 f 512 f(x in ) = 8 mhz 4 mhz 500 khz 125 khz 15625 hz count source frequency f(x in ) = 25 mhz 12.5 mhz 1.5625 mhz 390.625 khz 48.8281 khz f(x in ) = 16 mhz 8 mhz 1 mhz 250 khz 31250 hz
timer b 7721 group users manual 9C23 9.5 pulse period/pulse width measurement mode 9.5.3 operation in pulse period/pulse width measurement mode when the count start bit is set to 1, the counter starts counting of the count source. the counter value is transferred to the reload register when an valid edge of the measurement pulse is detected. (refer to section (1) pulse period/pulse width measurement. ) a the counter value is cleared to 0000 16 after the transfer in , and the counter continues counting. ? the timer bj interrupt request bit is set to 1 when the counter value is cleared to 0000 16 in a ( note ). the interrupt request bit remains set to 1 until the interrupt request is accepted or the interrupt request bit is cleared to 0 by software. ? the timer repeats operations to ? above. note: no timer bj interrupt request occurs when the first valid edge is input after the counter starts counting. (1) pulse period/pulse width measurement the measurement mode select bits (bits 2 and 3 at addresses 5b 16 and 5c 16 ) specify whether the pulse period of an external signal is measured or its pulse width is done. table 9.5.3 lists the relationship between the measurement mode select bits and the pulse period/pulse width measurements. make sure that the measurement pulse interval from the falling edge to the rising edge, and vice versa are two cycles of the count source or more. additionally, use software to identify whether the measurement result indicates the h level or the l level width. table 9.5.3 relationship between measurement mode select bits and pulse period/pulse width measurements b3 0 0 1 pulse period/pulse width measurement pulse period measurement pulse width measurement measurement interval (valid edges) from falling edge to falling edge (falling edges) from rising edge to rising edge (rising edges) from falling edge to rising edge, and vice versa (falling and rising edges) b2 0 1 0 (2) timer bj overflow flag a timer bj interrupt request occurs when a measurement pulses valid edge is input or a counter overflow occurs. the timer bj overflow flag is used to identify the cause of the interrupt request, that is, whether it is an overflow occurrence or a valid edge input. the timer bj overflow flag is set to 1 by an overflow. accordingly, the cause of the interrupt request occurrence is identified by checking the timer bj overflow flag in the interrupt routine. when a value is written to the timer bj mode register with the count start bit = 1, the timer bj overflow flag is cleared to 0 at the next count timing of the count source the timer bj overflow flag is a read-only bit. use the timer bi interrupt request bit to detect the overflow timing. do not use the timer bi overflow flag for this detection. figure 9.5.3 shows the operation during pulse period measurement. figure 9.5.4 shows the operation during pulse width measurement.
7721 group users manual timer b 9C24 9.5 pulse period/pulse width measurement mode fig. 9.5.3 operation during pulse period measurement fig. 9.5.4 operation during pulse width measurement count source measurement pulse timing at which counter is cleared to 0000 16 note: the above applies when measurement is performed for an interval from one falling edge to the next falling edge of the measurement pulse. reload register counter transfer timing count start bit counter is initialized by completion of measurement. counter overflow. cleared to 0 when interrupt request is accepted or cleared by software. timer bj interrupt request bit timer bj overflow flag transferred (undefined value) transferred (measured value) measurement pulse count source timing at which counter is cleared to 0000 16 count start bit timer bj interrupt request bit timer bj overflow flag reload register counter transfer timing counter is initialized by completion of measurement. counter overflow. transferred (measured value) transferred (measured value) transferred (measured value) transferred (undefined value) cleared to 0 when interrupt request is accepted or cleared by software.
timer b 7721 group users manual 9C25 9.5 pulse period/pulse width measurement mode [precautions for pulse period/pulse width measurement mode] 1. a timer bj interrupt request is generated by the following sources: l input of measured pulses valid edge l counter overflow when the overflow generates the interrupt request, the timer bj overflow flag is set to 1. 2. after reset, the timer bj overflow flag is undefined. when a value is written to the timer bj mode register with the count start bit = 1, this flag is cleared to 0 at the next count timing of the count source. 3. an undefined value is transferred to the reload register when the first valid edge is input after the counter starts counting. in this case, no timer bj interrupt request occurs. 4. the counter value at start of counting is undefined. accordingly, a timer bj interrupt request may be generated by an overflow immediately after the counter starts counting. 5. if the contents of the measurement mode select bits are changed after the counter starts counting, the timer bj interrupt request bit is set to 1. when the same value which has been set in these bits are written again, the timer bj interrupt request bit is not changed, that is, the bit retains the state. 6. if the input signal to the tbj in pin is affected by noise, etc., the counter may not perform the exact measurement. we recommend to verify, by software, that the measurement values are within a constant range.
7721 group users manual timer b 9C26 9.5 pulse period/pulse width measurement mode memorandum
chapter 10 real-time output 10.1 overview 10.2 block description 10.3 setting of real-time output 10.4 real-time output operation
real-time output 7721 group users manual 10C2 10.1 overview 10.1 overview the real-time output has the function of changing the output level of several pins simultaneously at every period of the timer. figure 10.1.1 shows the block diagram of real-time output per bit. real-time output has two operating modes described below. (1) pulse mode 0 the 8-bit pulse output pins serve for two independent 4-bit outputs. figure 10.1.2 shows the configuration of real-time output in the pulse mode 0. (2) pulse mode 1 the 8-bit pulse output pins serve for a 2-bit and a 6-bit outputs. figure 10.1.3 shows the configuration of real-time output in the pulse mode 1. fig. 10.1.1 block diagram of real-time output per bit data bus pulse output data register j waveform output select bit j bit i of port p6 direction register t d q timer aj underflow signal 1 0 p6 i /rtp0 k , p6 i /rtp1 k ?i = 0? ?j = 0, 1 ?k = 0? flip-flop port p6 i latch
real-time output 7721 group users manual 10C3 fig. 10.1.2 configuration of real-time output in pulse mode 0 10.1 overview fig. 10.1.3 configuration of real-time output in pulse mode 1 a port p6 i direction register port p6i latch (i = 0C7) 1 0 data bus (even) a a a a p6 4 /rtp1 0 p6 5 /rtp1 1 p6 6 /rtp1 2 p6 7 /rtp1 3 timer a1 t d q t d q t d q t d q b7 b0 pulse output data register 0 bit 0 of waveform output select bits p6 0 /rtp0 0 p6 1 /rtp0 1 p6 2 /rtp0 2 p6 3 /rtp0 3 a a a a t d q t d q t d q t d q b7 b0 timer a0 pulse output data register 1 bit 1 of waveform output select bits a port p6 i direction register port p6 i latch (i = 0C7) 1 0 data bus (even) pulse output data register 0 bit 0 of waveform output select bits p6 0 /rtp0 0 p6 1 /rtp0 1 a a t d q t d q b7 b0 timer a0 a p6 2 /rtp0 2 p6 3 /rtp0 3 p6 4 /rtp1 0 p6 5 /rtp1 1 p6 6 /rtp1 2 p6 7 /rtp1 3 bit 1 of waveform output select bits t d q t d q t d q t d q a a a a a t d q t d q b7 b0 timer a1 pulse output data register 1
real-time output 7721 group users manual 10C4 10.2 block description relevant registers to real-time output are described below. 10.2.1 real-time output control register figure 10.2.1 shows the structure of the real-time output control register. 10.2 block description fig. 10.2.1 structure of real-time output control register b7 b6 b5 b4 b3 b2 b1 b0 bit nothing is assigned. the value is ??at reading. bit name functions at reset rw pulse output mode select bit waveform output select bits 1 see the following table. 0 0 2 rw rw 7 to 3 rw real-time output control register (address 62 16 ) 0 0 undefined 0 : pulse mode 0 1 : pulse mode 1 note: when using the p6 0 ?6 7 pins as the pulse output pins for real-time output, set the corresponding bits of the port p6 direction register (address 10 16 ) to ?. b1 b0 when pulse mode 0 is selected 00 p6 7 /rtp1 3 p6 6 /rtp1 2 p6 5 /rtp1 1 p6 4 /rtp1 0 p6 3 /rtp0 3 p6 2 /rtp0 2 p6 1 /rtp0 1 p6 0 /rtp0 0 port 01 p6 7 /rtp1 3 p6 6 /rtp1 2 p6 5 /rtp1 1 p6 4 /rtp1 0 p6 3 /rtp0 3 p6 2 /rtp0 2 p6 1 /rtp0 1 p6 0 /rtp0 0 port port rtp 10 p6 7 /rtp1 3 p6 6 /rtp1 2 p6 5 /rtp1 1 p6 4 /rtp1 0 p6 3 /rtp0 3 p6 2 /rtp0 2 p6 1 /rtp0 1 p6 0 /rtp0 0 rtp 11 p6 7 /rtp1 3 p6 6 /rtp1 2 p6 5 /rtp1 1 p6 4 /rtp1 0 p6 3 /rtp0 3 p6 2 /rtp0 2 p6 1 /rtp0 1 p6 0 /rtp0 0 port rtp rtp p6 7 /rtp1 3 p6 6 /rtp1 2 p6 5 /rtp1 1 p6 4 /rtp1 0 p6 3 /rtp0 3 p6 2 /rtp0 2 p6 1 /rtp0 1 p6 0 /rtp0 0 port port when pulse mode 1 is selected p6 7 /rtp1 3 p6 6 /rtp1 2 p6 5 /rtp1 1 p6 4 /rtp1 0 p6 3 /rtp0 3 p6 2 /rtp0 2 p6 1 /rtp0 1 p6 0 /rtp0 0 port rtp p6 7 /rtp1 3 p6 6 /rtp1 2 p6 5 /rtp1 1 p6 4 /rtp1 0 p6 3 /rtp0 3 p6 2 /rtp0 2 p6 1 /rtp0 1 p6 0 /rtp0 0 port rtp p6 7 /rtp1 3 p6 6 /rtp1 2 p6 5 /rtp1 1 p6 4 /rtp1 0 p6 3 /rtp0 3 p6 2 /rtp0 2 p6 1 /rtp0 1 p6 0 /rtp0 0 rtp rtp port : this functions as a programmable i/o port. rtp : this functions as a pulse output pin.
real-time output 7721 group users manual 10C5 10.2 block description 10.2.2 pulse output data registers 0 and 1 figure 10.2.2 shows the structure of the pulse output data registers 0 and 1. the bit position of the rtp0 2 and rtp0 3 pulse output data bits differs according to the pulse mode. before setting the pulse output data registers 0 and 1, set of the pulse output mode select bit (bit 2 at address 62 16 ). the data written into the pulse output data registers 0 and 1 is output from the corresponding pulse output pins every underflow of timers a0 and a1. bit bit name functions 0 1 2 3 7 to 4 rtp0 0 pulse output data bit pulse output data register 0 (address 1a 16 ) b1 b0 b2 b3 b4 b5 b6 b7 at reset rw undefined undefined undefined undefined undefined 0 : ??level output 1 : ??level output wo note: use the ldm or sta instruction for writing to this register rtp0 1 pulse output data bit wo wo wo rtp0 2 pulse output data bit (valid in pulse mode 0) rtp0 3 pulse output data bit (valid in pulse mode 0) nothing is assigned. bit bit name functions 0, 1 2 3 nothing is assigned. pulse output data register 1 (address 1c 16 ) b1 b0 b2 b3 b4 b5 b6 b7 at reset rw undefined undefined undefined undefined undefined 0 : ??level output 1 : ??level output wo note: use the ldm or sta instruction for writing to this register. wo wo wo rtp0 3 pulse output data bit (valid in pulse mode 1) 4 rtp0 2 pulse output data bit (valid in pulse mode 1) rtp1 0 pulse output data bit 5 6 7 rtp1 1 pulse output data bit rtp1 2 pulse output data bit rtp1 3 pulse output data bit undefined undefined wo wo fig. 10.2.2 structure of pulse output data registers 0 and 1
real-time output 7721 group users manual 10C6 10.2 block description 10.2.3 port p6 direction register the pulse output pins are shared with port p6. when using these pins as pulse output pins of real-time output, set the corresponding bits of the port p6 direction register to 1 to set these ports for the output mode. figure 10.2.3 shows the relationship between the port p6 direction register and the pulse output pins. after reset, the state of the port p6 pins are floated since these pins are in the input mode. the output levels of the pulse output pins are undefined until timer a0 or a1 underflows first after the data for the timer is written. because the pulse output data registers 0 and 1 are undefined after reset. when these conditions should be avoided, follow the procedure processing of avoiding undefined output before starting pulse output in figures 10.3.1 and 10.3.2. when reading the port p6 register (address e 16 ), the output values of the real time output pins can be read out. 10.2.4 timers a0 and a1 the data written into the pulse output registers 0 and 1 is output from the pulse output pins every underflow of timer a0 or a1. refer to section 8.3 timer mode for the setting of timers a0 and a1. fig. 10.2.3 relationship between port p6 direction register and pulse output pins bit bit name functions 0 1 2 3 4 5 6 7 rtp0 0 pin 0 : input mode 1 : output mode when using these pins as pulse output pins, set the corresponding bits to ?. port p6 direction register (address 10 16 ) b1 b0 b2 b3 b4 b5 b6 b7 at reset rw 0 0 0 0 0 0 0 0 rw rw rw rw rw rw rw rw note: when setting these bits to ?,?the corresponding pins serve as input port (floated) regardless of the state of the waveform output select bits (bits 0 and 1 at address 62 16 ). rtp0 1 pin rtp0 2 pin rtp0 3 pin rtp1 0 pin rtp1 1 pin rtp1 2 pin rtp1 3 pin
real-time output 7721 group users manual 10C7 10.3 setting of real-time output figures 10.3.1 to 10.3.3 show an initial setting example for registers relevant to the real-time output. note that when using interrupts, set up to enable the interrupts. for details, refer to chapter 7. interrupts. 10.3 setting of real-time output fig. 10.3.1 initial setting example for registers relevant to real-time output (1) p6 0 ?6 7 pins functions as the programmable i/o port. continue to ?igure 10.3.2 processing of avoiding undefined output before starting pulse output (note) b7 b0 set to initial output level of real-time output 0 : ??level 1 : ??level rtp0 0 rtp0 1 rtp0 2 rtp0 3 rtp1 0 rtp1 1 rtp1 2 rtp1 3 port p6 register (address e 16 ) aaaaaaaaaa aaaaaaaaaa aaaaaaaaaa aaaaaaaaaa aaaaaaaaaa setting port p6 direction register b7 b0 set the bits corresponding to the selected pulse output pins to ?. note: this processing can be neglected if the system is not affected by undefined output. setting pulse output mode b7 b0 real-time output control register (address 62 16 ) 0 0 pulse output mode select bit 0 : pulse mode 0 1 : pulse mode 1 when pulse mode 0 is selected aaaaaaaaa aaaaaaaaa aaaaaaaaa aaaaaaaaa aaaaaaaaa aaaaaaaaa aaaaaaaaa setting output data b0 0 : ??level 1 : ??level rtp0 0 rtp0 1 rtp0 2 rtp0 3 pulse output data register 0 (address 1a 16 ) b7 b0 rtp1 0 rtp1 1 rtp1 2 rtp1 3 b7 5 5 : it may be either ??or ?. aaaaaaaaa aaaaaaaaa aaaaaaaaa aaaaaaaaa aaaaaaaaa aaaaaaaaa aaaaaaaaa b0 b7 b0 b7 rtp0 0 rtp0 1 rtp0 2 rtp0 3 rtp1 0 rtp1 1 rtp1 2 rtp1 3 port p6 direction register (address 10 16 ) when pulse mode 1 is selected setting output data pulse output data register 1 (address 1c 16 ) 5 0 : ??level 1 : ??level 55 5 : it may be either ??or ?. rtp0 0 rtp0 1 0 : ??level 1 : ??level pulse output data register 0 (address 1a 16 ) pulse output data register 1 (address 1c 16 ) 0 : ??level 1 : ??level rtp0 2 rtp0 3 rtp1 0 rtp1 1 rtp1 2 rtp1 3
real-time output 7721 group users manual 10C8 fig. 10.3.2 initial setting example for registers relevant t o real-time output (2) 10.3 setting of real-time output from preceding figure 10.3.1 processing of avoiding undefined output before starting puls e output (note) b0 timer a0 mode register (address 56 16 ) timer a1 mode register (address 57 16 ) b7 0 select of count source f 2 0 0000 0 0 b7 set to 0000 16 b0 b7 b0 (b15) (b8) 00 16 00 16 b0 b7 0 interrupt disabled 00 0 no interrupt request b0 count start register (address 40 16 ) b7 timer a0 count start bit 1 : start counting ] when timer a0 or a1 underflows, the contents of the pulse o utput data register 0 or 1 are output from the flip-flop. b0 b7 setting timers a0, a1 b0 b7 0 count source select bits 000 0 0 b7 can be set to 0000 16 Cffff 16 (n) b0 b7 b0 (b15) (b8) 00 16 00 16 b0 b7 interrupt priority level select bits when using interrupts, set these bits to one of levels 1 to 7. when disabling interrupts, set these bits to level 0. 0 0 0 : f 2 0 1 : f 16 1 0 : f 64 1 1 : f 512 b7 b6 continue to figure 10.3.3 note: this processing can be neglected if the system is not affected by undefined output. timer a0 register (addresses 47 16 , 46 16 ) timer a1 register (addresses 49 16 , 48 16 ) timer a0 interrupt control register (address 75 16 ) timer a1 interrupt control register (address 76 16 ) timer a1 count start bit count start register (address 40 16 ) timer a0 count start bit timer a1 count start bit 0 : stop counting timer a0 mode register (address 56 16 ) timer a1 mode register (address 57 16 ) timer a0 register (addresses 47 16 , 46 16 ) timer a1 register (addresses 49 16 , 48 16 ) timer a0 interrupt control register (address 75 16 ) timer a1 interrupt control register (address 76 16 )
real-time output 7721 group users manual 10C9 10.3 setting of real-time output fig. 10.3.3 initial setting example for registers relevant to real-time output (3) when pulse mode 0 is selected continue to ?igure 10.3.2 aaaaaaaaaa aaaaaaaaaa aaaaaaaaaa aaaaaaaaaa aaaaaaaaaa aaaaaaaaaa setting real-time output port b0 0 1 : rtp0 0 ?tp0 3 1 0 : rtp1 0 ?tp1 3 1 1 : rtp0 0 ?tp0 3 and rtp1 0 ?tp1 3 real-time output control register (address 62 16 ) b7 0 b1 b0 pulse mode 0 waveform output select bits aaaaaaaaaa aaaaaaaaaa aaaaaaaaaa aaaaaaaaaa aaaaaaaaaa aaaaaaaaaa b0 b7 1 pulse mode 1 aaaaaaaaaaaa aaaaaaaaaaaa aaaaaaaaaaaa aaaaaaaaaaaa setting count start bit to ? b0 count start register (address 40 16 ) b7 timer a0 count start bit pulse output starts after overflow of timer a0 or a1 aaa aaa aaa when pulse mode 1 is selected setting real-time output port real-time output control register (address 62 16 ) 0 1 : rtp0 0 , rtp0 1 1 0 : rtp0 2 , rtp0 3 and rtp1 0 ?tp1 3 1 1 : rtp0 0 ?tp0 3 and rtp1 0 ?tp1 3 b1 b0 waveform output select bits timer a1 count start bit
real-time output 7721 group users manual 10C10 10.4 real-time output operation 10.4 real-time output operation when the timer ai (i = 0, 1) count start bit is set to 1, the counter starts counting of the count source. the contents of pulse output data register i are output from the pulse output pins at every underflow of timer ai. the timer is reloaded with the contents of the reload register and continues counting. a the timer ai interrupt request bit is set to 1 when the counter underflows in . the interrupt request bit retains 1 until the interrupt request is accepted or it is cleared by software. ? write the next output data into the pulse output data register i during the timer ai interrupt routine or after the recognition of the timer ai interrupt request occurrence. figure 10.4.1 shows an example of real-time output operation. contents of bits 3? of pulse output data register 0 rtp0 3 output rtp0 2 output rtp0 1 output rtp0 0 output timer a0 interrupt request bit 0003 16 0000 16 undefined ] 2 0011 2 0110 2 1100 2 1001 2 0011 2 undefined ] 3 starts counting ] 1 counter contents (hex.) ] 1 : written by software ] 2 : to avoid undefined output for these terms, follow the procedure ?rocessing of avoiding undefined output before starting pulse output?in figures 10.3.1 and 10.3.2. ] 3 : cleared to ??when interrupt request is accepted or cleared by software. the above figure shows an example of he following conditions: ?ulse mode 0 selected ?tp0 0 ?tp0 3 selected ?imer a0 register set value n = 0003 16 starts pulse outputting ] 1 ] 1 ] 1 ] 1 ] 1 undefined ] 2 undefined ] 2 undefined ] 2 ] 3 ] 3 ] 3 ] 3 fig. 10.4.1 example of real-time output operation
11.1 overview 11.2 block description 11.3 clock synchronous serial i/o mode [precautions for clock synchronous serial i/o mode] 11.4 clock asynchronous serial i/o (uart) mode chapter 11 serial i/o
serial i/o 7721 group users manual 11C2 11.1 overview serial i/o consists of 2 channels: uart0 and uart1. they each have a transfer clock generating timer for the exclusive use of them and can operate independently. uart0 and uart1 have the same functions. uarti (i = 0 and 1) has the following 2 operating modes: (1) clock synchronous serial i/o mode transmitter and receiver use the same clock as the transfer clock. transfer data has a length of 8 bits. (2) clock asynchronous serial i/o (uart) mode transfer rate and transfer data format can arbitrarily be set. the user can select a transfer data length of 7 bits, 8 bits, or 9 bits. figure 11.1.1 shows the transfer data formats in each operating mode. 11.1 overview l clock synchronous serial i/o mode transfer data length of 8 bits l uart mode transfer data length of 7 bits transfer data length of 8 bits transfer data length of 9 bits fig. 11.1.1 transfer data formats in each operating mode
serial i/o 7721 group users manual 11C3 11.2 block description figure 11.2.1 shows the block diagram of serial i/o. registers relevant to serial i/o are described below. 11.2 block description rxd i data bus (odd) data bus (even) 0000000 uarti receive register uarti receive buffer register uarti transmit buffer register receive control circuit transmit control circuit 1 / (n+1) 1/16 1/16 1/2 brgi clock synchronous (internal clock selected) uart clock synchronous uart clock synchronous (internal clock selected) clock synchronous (external clock selected) data bus (odd) data bus (even) txd i transfer clock transfer clock clk i brg count source select bits cts i / rts i uarti transmit register n: values set in uarti baud rate register (brgi) clock synchronous d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 f 2 f 16 f 64 f 512 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 fig. 11.2.1 block diagram of serial i/o
serial i/o 7721 group users manual 11C4 11.2.1 uarti transmit/receive mode register figure 11.2.2 shows the structure of uarti transmit/receive mode register. the serial i/o mode select bits are used to select a uartis operating mode. bits 4 to 6 are described in section 11.4.2 transfer data format , and bit 7 is done in section 11.4.8 sleep mode. 11.2 block description b7 b6 b5 b4 b3 b2 b1 b0 bit 4 2 1 0 bit name at reset 0 rw functions b2 b1 b0 3 7 6 5 rw rw rw rw rw rw rw rw 0 0 0 0 serial i/o mode select bits 0 0 0 : serial i/o disabled (p8 functions as a programmable i/o port.) 0 0 1 : clock synchronous serial i/o mode 0 1 0 : do not select. 0 1 1 : do not select. 1 0 0 : uart mode (transfer data length = 7 bits) 1 0 1 : uart mode (transfer data length = 8 bits) 1 1 0 : uart mode (transfer data length = 9 bits) 1 1 1 : do not select. sleep select bit (valid in uart mode) ( note ) parity enable bit (valid in uart mode) ( note ) odd/even parity select bit (valid in uart mode when parity enable bit is 1) ( note ) stop bit length select bit (valid in uart mode) ( note ) internal/external clock select bit uart0 transmit/receive mode register (address 30 16 ) uart1 transmit/receive mode register (address 38 16 ) note: bits 4 to 6 are invalid in the clock synchronous serial i/o mode. (they may be either 0 or 1.) additionally, fix bit 7 to 0. 0 : odd parity 1 : even parity 0 : parity disabled 1 : parity enabled 0 : sleep mode terminated (invalid) 1 : sleep mode selected 0 : internal clock 1 : external clock 0 : one stop bit 1 : two stop bits 0 0 0 fig. 11.2.2 structure of uarti transmit/receive mode register
serial i/o 7721 group users manual 11C5 (1) internal/external clock select bit (bit 3) n clock synchronous serial i/o mode by clearing this bit to 0 in order to select an internal clock, the clock which is selected with the brg count source select bits (bits 0 and 1 at addresses 34 16 , 3c 16 ) becomes the count source of the brgi (described later). the brgis output divided by 2 becomes the transfer clock. additionally, the transfer clock is output from the clk i pin. by setting this bit to 1 in order to select an external clock, the clock input to the clk i pin becomes the transfer clock. n uart mode by clearing this bit to 0 in order to select an internal clock, the clock which is selected with the brg count source select bits (bits 0 and 1 at addresses 34 16 , 3c 16 ) becomes the count source of the brgi (described later). then, the clk i pin functions as a programmable i/o port. by setting this bit to 1 in order to select an external clock, the clock input to the clk i pin becomes the count source of brgi. always in the uart mode, the brgis output divided by 16 becomes the transfer clock. 11.2 block description
serial i/o 7721 group users manual 11C6 11.2 block description 11.2.2 uarti transmit/receive control register 0 figure 11.2.3 shows the structure of uarti transmit/receive control register 0. for bits 0 and 1, refer to section 11.2.1 (1) internal/external clock select bit (bit 3). fig. 11.2.3 structure of uarti transmit/receive control register 0 (1) ____ ____ cts/rts select bit (bit 2) ____ ____ by clearing this bit to 0 in order to select the cts function, pins p8 0 and p8 4 function as cts input pins, and the input signal of l level to these pins becomes one of the transmission conditions. ____ ____ by setting this bit to 1 in order to select the rts function, pins p8 0 and p8 4 become rts output ____ pins. when the receive enable bit (bit 2 at addresses 35 16 , 3d 16 ) is 0 (reception disabled), the rts output pin outputs h level. ____ in the clock synchronous serial i/o mode, the output level of the rts pin becomes l when reception conditions are satisfied, and it becomes h when reception starts. note that, when an internal clock ____ is selected (bit 3 at addresses 30 16 , 38 16 = 0), the rts output is undefined. accordingly, do not ____ select the rts function. ____ in the clock asynchronous serial i/o mode, the output level of the rts pin becomes l when the receive enable bit is set to 1. it becomes h when reception starts and it becomes l when reception is completed. (2) transmit register empty flag (bit 3) this flag is cleared to 0 when the uarti transmit buffer registers contents are transferred to the uarti transmit register. when transmission is completed and the uarti transmit register becomes empty, this flag is set to 1. cts/rts select bit bit 1 brg count source select bits bit name at reset rw functions b7 b6 b5 b4 b3 b2 b1 b0 0 0 : f 2 0 1 : f 16 1 0 : f 64 1 1 : f 512 uart0 transmit/receive control register 0 (address 34 16 ) uart1 transmit/receive control register 0 (address 3c 16 ) b1 b0 0 : cts function selected 1 : rts function selected transmit register empty flag 0 : data present in transmit register (during transmission) 1 : no data present in transmit register (transmission completed) 1 0 0 0 0 2 rw rw ro 3 rw 7 to 4 nothing is assigned. undefined C
serial i/o 7721 group users manual 11C7 11.2 block description 11.2.3 uarti transmit/receive control register 1 figure 11.2.4 shows the structure of uarti transmit/receive control register 1. for bits 4 to 7, refer to section 11.3.6 processing on detecting overrun error and 11.4.7 processing on detecting error. bit bit name at reset 5 framing error flag (valid in uart mode) 0 0 : no framing error 1 : framing error detected rw functions b7 b6 b5 b4 b3 b2 b1 b0 uart0 transmit/receive control register 1 (address 35 16 ) uart1 transmit/receive control register 1 (address 3d 16 ) notes 1: bit 4 is cleared to 0 when the receive enable bit is cleared to 0 or when the serial i/o mode select bits (bits 2 to 0 at addresses 30 16 , 38 16 ) are cleared to 000 2 . bits 5 and 6 are cleared to 0 when one of the following is performed: ?clearing the receive enable bit to 0 ?reading the low-order byte of the uarti receive buffer register (addresses 36 16 , 3e 16 ) out ?clearing the serial i/o mode select bits (bits 2 to 0 at addresses 30 16 , 38 16 ) to 000 2 bit 7 is cleared to 0 when all of bits 4 to 6 become 0. 2: bits 5 to 7 are invalid in the clock synchronous serial i/o mode. 0 transmit enable bit 0 0 : transmission disabled 1 : transmission enabled 1 transmit buffer empty flag 1 0 : data present in transmit buffer register 1 : no data present in transmit buffer register 2 receive enable bit 0 0 : reception disabled 1 : reception enabled 3 receive complete flag 0 0 : no data present in receive buffer register 1 : data present in receive buffer register 4 overrun error flag 0 0 : no overrun error 1 : overrun error detected 6 parity error flag (valid in uart mode) 0 0 : no parity error 1 : parity error detected 7 error sum flag (valid in uart mode) 0 0 : no error 1 : error detected (notes 1, 2) (notes 1, 2) (notes 1, 2) (note 1) rw ro rw ro ro ro ro ro fig. 11.2.4 structure of uarti transmit/receive control register 1
serial i/o 7721 group users manual 11C8 (1) transmit enable bit (bit 0) by setting this bit to 1, uarti enters the transmission enable state. by clearing this bit to 0 during transmission, uarti enters the transmission disable state after the transmission which is in progress at that time is completed. (2) transmit buffer empty flag (bit 1) this flag is set to 1 when data set in the uarti transmit buffer register is transferred from the uarti transmit buffer register to the uarti transmit register. this flag is cleared to 0 when data is set in the uarti transmit buffer register. (3) receive enable bit (bit 2) by setting this bit to 1, uarti enters the reception enable state. by clearing this bit to 0 during reception, uarti quits the reception immediately and enters the reception disable state. (4) receive complete flag (bit 3) this flag is set to 1 when data is ready in the uarti receive register and that is transferred to the uarti receive buffer register (i.e., when reception is completed). this flag is cleared to 0 when one of the following is performed: ?reading the low-order byte of the uarti receive buffer register out ?clearing the receive enable bit (bit 2) to 0 ?clearing the serial i/o mode select bits (bits 2 to 0 at addresses 30 16 , 38 16 ) to 000 2 . 11.2 block description
serial i/o 7721 group users manual 11C9 11.2.4 uarti transmit register and uarti transmit buffer register figure 11.2.5 shows the block diagram for the transmitter; figure 11.2.6 shows the structure of uarti transmit buffer register. 11.2 block description fig. 11.2.5 block diagram for transmitter sp sp par ? 2sp 1sp uart 7-bit uart 8-bit uart 7-bit uart 9-bit uart clock sync. clock sync. clock sync. data bus (even) data bus (odd) txd i uarti transmit register parity enabled parity disabled d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 sp : stop bit par : parity bit uarti transmit buffer register 8-bit uart 9-bit uart fig. 11.2.6 structure of uarti transmit buffer register b7 b0 bit 8 to 0 at reset undefined rw functions wo b7 b0 (b15) (b8) 15 to 9 undefined uart0 transmit buffer register (addresses 33 16 , 32 16 ) uart1 transmit buffer register (addresses 3b 16 , 3a 16 ) nothing is assigned. transmit data is set. note: use the ldm or sta instruction for writing to this register.
serial i/o 7721 group users manual 11C10 transmit data is set into the uarti transmit buffer register. set the transmit data into the low-order byte of this register when the microcomputer operates in the clock synchronous serial i/o mode or when a 7- bit or 8-bit length of transfer data is selected in the uart mode. when a 9-bit length of transfer data is selected in the uart mode, set the transmit data into the uarti transmit buffer register as follows: ?bit 8 of the transmit data into bit 0 of high-order byte of this register. ?bits 7 to 0 of the transmit data into the low-order byte of this register. the transmit data which is set in the uarti transmit buffer register is transferred to the uarti transmit register when the transmission conditions are satisfied, and then it is output from the txd i pin synchronously with the transfer clock. the uarti transmit buffer register becomes empty when the data which is set in the uarti transmit buffer register is transferred to the uarti transmit register. accordingly, the user can set the next transmit data. when quitting the transmission which is in progress and setting the uarti transmit buffer register again, follow the procedure described bellow: clear the serial i/o mode select bits (bits 2 to 0 at addresses 30 16 , 38 16 ) to 000 2 (serial i/o disabled). set the serial i/o mode select bits again. a set the transmit enable bit (bit 0 at addresses 35 16 , 3d 16 ) to 1 (transmission enabled) and set transmit data in the uarti transmit buffer register. 11.2 block description
serial i/o 7721 group users manual 11C11 11.2.5 uarti receive register and uarti receive buffer register figure 11.2.7 shows the block diagram for the receiver; figure 11.2.8 shows the structure of uarti receive buffer register. 11.2 block description fig. 11.2.7 block diagram for receiver clock sync. sp sp par 2sp 1sp uart 0 0 0 0 0 0 0 rxd i d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 sp : stop bit par : parity bit 8-bit uart 9-bit uart 7-bit uart 9-bit uart clock sync. clock sync. 7-bit uart 8-bit uart data bus (even) data bus (odd) uarti receive register parity enabled parity disabled uarti receive buffer register b7 b0 bit 8 to 0 at reset undefined rw functions ro b7 b0 (b15) (b8) 15 to 9 uart0 receive buffer register (addresses 37 16 , 36 16 ) uart1 receive buffer register (addresses 3f 16 , 3e 16 ) nothing is assigned. the value is ??at reading. receive data is read out from here. 0 fig. 11.2.8 structure of uarti receive buffer register
serial i/o 7721 group users manual 11C12 the uarti receive register is used to convert serial data which is input to the rxd i pin into parallel data. this register takes in the signal input to the rxd i pin in a unit of 1 bit synchronously with the transfer clock. the uarti receive buffer register is used to read out receive data. when reception is completed, the receive data which is taken in the uarti receive register is automatically transferred to the uarti receive buffer register. note that the contents of the uarti receive buffer register is updated when the next data is ready in the uarti receive register before the data which has been transferred to the uarti receive buffer register is read out. (i.e., an overrun error occurs.) the uarti receive buffer register is initialized by setting the receive enable bit (bit 2 at addresses 35 16 , 3d 16 ) to 1 after clearing it to 0. figure 11.2.9 shows the contents of the uarti receive buffer register when reception is completed. 11.2 block description b7 b0 b7 b0 0 000000 0 000000 0 000000 receive data (9 bits) receive data (8 bits) receive data (7 bits) in uart mode (transfer data length : 9 bits) in clock synchronous serial i/o mode in uart mode (transfer data length : 8 bits) in uart mode (transfer data length : 7 bits) same value as bit 7 in low-order byte same value as bit 6 in low-order byte high-order byte (addresses 37 16 , 3f 16 ) low-order byte (addresses 36 16 , 3e 16 ) fig. 11.2.9 contents of uarti receive buffer register when reception is completed
serial i/o 7721 group users manual 11C13 11.2.6 uarti baud rate register (brgi) the uarti baud rate register (brgi) is an 8-bit timer exclusively used for uarti to generate a transfer clock. it has a reload register. assuming that the value set in the brgi is n (n = 00 16 to ff 16 ), the brgi divides the count source frequency by (n + 1). in the clock synchronous serial i/o mode, the brgi is valid when an internal clock is selected, and the brgis output divided by 2 becomes the transfer clock. in the uart mode, the brgi is always valid, and the brgis output divided by 16 becomes the transfer clock. the data which is written to the uarti baud rate register (brgi) is written to both the timer and the reload register whether transmission/reception is in progress or not. accordingly, writing to these register must be performed while transmission/reception is stopped. figure 11.2.10 shows the structure of the uarti baud rate register (brgi); figure 11.2.11 shows the block diagram of transfer clock generating section. 11.2 block description b7 b0 uart0 baud rate register (address 31 16 ) uart1 baud rate register (address 39 16 ) functions bit at reset rw 7 to 0 can be set to ?0 16 ?to ?f 16 . assuming that the set value = n, brgi divides the count source frequency by (n + 1). undefined wo note: writing to this register must be performed while the transmission/reception halts. use the ldm or sta instruction for writing to this register. fig. 11.2.10 structure of uarti baud rate register (brgi) brgi 1/2 transmit control circuit receive control circuit transfer clock for transmit operation transfer clock for receive operation transmit control circuit receive control circuit transfer clock for transmit operation transfer clock for receive operation brgi 1/16 f i : clock selected by brg count source select bits (f 2 , f 16 , f 64 , or f 512 ) f ext : clock input to clk i pin (external clock) 1/16 f i f ext f ext f i fig. 11.2.11 block diagram of transfer clock generating section
serial i/o 7721 group users manual 11C14 11.2.7 uarti transmit interrupt control and uarti receive interrupt control registers when using uarti, 2 types of interrupts, which are uarti transmit and uarti receive interrupts, can be used. each interrupt has its corresponding interrupt control register. figure 11.2.12 shows the structure of uarti transmit interrupt control and uarti receive interrupt control registers. for details about interrupts, refer to chapter 7. interrupts. 11.2 block description fig. 11.2.12 structure of uarti transmit interrupt control and uarti receive interrupt control registers (1) interrupt priority level select bits (bits 0 to 2) these bits select a priority level of the uarti transmit interrupt or uarti receive interrupt. when using uarti transmit/receive interrupts, select one of the priority levels (1 to 7). when a uarti transmit/receive interrupt request occurs, its priority level is compared with the processor interrupt priority level (ipl). the requested interrupt is enabled only when its priority level is higher than the ipl. (however, this applies when the interrupt disable flag (i) = 0.) to disable uarti transmit/receive interrupts, set these bits to 000 2 (level 0). (2) interrupt request bit (bit 3) the uarti transmit interrupt request bit is set to 1 when data is transferred from the uarti transmit buffer register to the uarti transmit register. the uarti receive interrupt request bit is set to 1 when data is transferred from the uarti receive register to the uarti receive buffer register. (however, when an overrun error occurs, it does not change.) each interrupt request bit is automatically cleared to 0 when its corresponding interrupt request is accepted. this bit can be set to 1 or 0 by software. b7 b6 b5 b4 b3 b2 b1 b0 uart0 transmit interrupt control register (address 71 16 ) uart0 receive interrupt control register (address 72 16 ) uart1 transmit interrupt control register (address 73 16 ) uart1 receive interrupt control register (address 74 16 ) bit 7 to 4 interrupt request bit 2 1 0 bit name at reset 0 rw functions 0 0 0 : level 0 (interrupt disabled) 0 0 1 : level 1 low level 0 1 0 : level 2 0 1 1 : level 3 1 0 0 : level 4 1 0 1 : level 5 1 1 0 : level 6 1 1 1 : level 7 high level b2 b1 b0 0 : no interrupt requested 1 : interrupt requested interrupt priority level select bits 3 rw rw rw rw undefined 0 0 0 nothing is assigned.
serial i/o 7721 group users manual 11C15 11.2 block description 11.2.8 port p8 direction register i/o pins of uarti are multiplexed with port p8. when using pins p8 2 and p8 6 as serial data input pins (rxd i ), set the corresponding bits of the port p8 direction register to 0 to set these pins for the input ____ ____ mode. when using pins p8 0 , p8 1 , p8 3 to p8 5 and p8 7 as i/o pins (cts i /rts i , clk i , txd i ) of uarti, these pins are forcibly set as i/o pins of uarti regardless of the port p8 direction registers contents. figure 11.2.13 shows the relationship between the port p8 direction register and uartis i/o pins. for details, refer to the description of each operating mode. fig. 11.2.13 relationship between port p8 direction register and uartis i/o pins bit corresponding pin functions 0 1 2 3 4 5 6 7 cts 0 / rts 0 pin rxd 0 pin txd 0 pin cts 1 / rts 1 pin rxd 1 pin 0 : input mode 1 : output mode when using pins p8 2 and p8 6 as serial data input pins (rxd 0 , rxd 1 ), set the corresponding bits to ?. clk 1 pin port p8 direction register (address 14 16 ) b1 b0 b2 b3 b4 b5 b6 b7 clk 0 pin txd 1 pin at reset rw 0 0 0 0 0 0 0 0 rw rw rw rw rw rw rw rw
serial i/o 7721 group users manual 11C16 11.3 clock synchronous serial i/o mode 11.3 clock synchronous serial i/o mode table 11.3.1 lists the performance overview in the clock synchronous serial i/o mode, and table 11.3.2 lists the functions of i/o pins in this mode. table 11.3.1 performance overview in clock synchronous serial i/o mode item transfer data format transfer rate transmit/receive control when selecting internal clock when selecting external clock functions transfer data has a length of 8 bits. lsb first brgis output divided by 2 maximum 5 mbps ____ ____ cts function or rts function can be selected by software. table 11.3.2 functions of i/o pins in clock synchronous serial i/o mode functions serial data output serial data input transfer clock output transfer clock input ____ cts input ____ rts output pin name txd i (p8 3 , p8 7 ) (note) rxd i (p8 2 , p8 6 ) clk i (p8 1 , p8 5 ) ___ ___ cts i /rts i (p8 0 , p8 4 ) method of selection (dummy data is output when performing only reception.) port p8 direction register \ 1 s corresponding bit = 0 (can be used as an i/o port when performing only transmission.) internal/external clock select bit \ 2 = 0 internal/external clock select bit = 1 ____ ____ cts/rts select bit \ 3 = 0 ____ ____ cts/rts select bit = 1 port p8 direction register \ 1 : address 14 16 internal/external clock select bit \ 2 : bit 3 at addresses 30 16 , 38 16 ____ ____ cts/rts select bit \ 3 : bit 2 at addresses 34 16 , 3c 16 note: the txd i pin outputs h level until transmission starts after uartis operating mode is selected.
serial i/o 7721 group users manual 11C17 11.3 clock synchronous serial i/o mode 11.3.1 transfer clock (synchronizing clock) data transfer is performed synchronously with the transfer clock. for the transfer clock, the user can select whether to generate the transfer clock internally or to input it from the external. the transfer clock is generated by operation of the transmit control circuit. accordingly, even when performing only reception, set the transmit enable bit to 1, and set dummy data in the uarti transmit buffer register in order to make the transmit control circuit active. (1) internal generation of transfer clock the count source selected with the brg count source select bits is divided by the brgi, and the brgi output is further divided by 2. this is the transfer clock. the transfer clock is output from the clk i pin. [setting for relevant registers] ?select an internal clock (bit 3 at addresses 30 16 , 38 16 = 0). ?select the brgis count source (bits 0 and 1 at addresses 34 16 , 3c 16 ) ?set division value C 1 (= n; 00 16 to ff 16 ) to the brgi (addresses 31 16 , 39 16 ). transfer clocks frequency = ?enable transmission (bit 0 at addresses 35 16 , 3d 16 = 1). ?set data to the uarti transmit buffer register (addresses 32 16 , 3a 16 ) [pins state] ?a transfer clock is output from the clk i pin. ?serial data is output from the txdi pin. (dummy data is output when performing only reception.) (2) input of transfer clock from the external a clock input from the clk i pin is the transfer clock. [setting for relevant registers] ?select an external clock (bit 3 at addresses 30 16 , 38 16 = 1). ?enable transmission (bit 0 at addresses 35 16 , 3d 16 = 1). ?set data to the uarti transmit buffer register (addresses 32 16 , 3a 16 ). [pins state] ?a transfer clock is input from the clk i pin. ?serial data is output from the txd i pin. (dummy data is output when performing only reception.) f i : frequency of brgis count source (f 2 , f 16 , f 64 , f 512 ) f i 2 (n+1)
serial i/o 7721 group users manual 11C18 11.3 clock synchronous serial i/o mode 11.3.2 method of transmission figure 11.3.1 shows an initial setting example for relevant registers when transmitting. transmission is started when all of the following conditions ( to a ) are satisfied. when an external clock is selected, satisfy conditions to a with the following precondition satisfied. the clk i pins input is at h level note: when an internal clock is selected, the above precondition is ignored. transmission is enabled (transmit enable bit = 1). transmit data is present in the uarti transmit buffer register (transmit buffer empty flag = 0) _____ ____ a the cts i pins input is at l level (when the cts function selected). ____ note : when the cts function is not selected, condition a is ignored. ____ ____ by connecting the rts i pin (receiver side) and cts i pin (transmitter side), the timing of transmission and that of reception can be matched. for details, refer to section 11.3.5 receive operation. when using interrupts, it is necessary to set the relevant registers to enable interrupts. for details, refer to chapter 7. interrupts. figure 11.3.2 shows writing data after start of transmission, and figure 11.3.3 shows detection of transmit completion.
serial i/o 7721 group users manual 11C19 11.3 clock synchronous serial i/o mode fig. 11.3.1 initial setting example for relevant registers when transmitting uart0 transmit buffer register (address 32 16 ) uart1 transmit buffer register (address 3a 16 ) b7 b0 transmit data is set. 1 uart0 transmit/receive control register 1 (address 35 16 ) uart1 transmit/receive control register 1 (address 3d 16 ) b7 b0 transmit enable bit 1: transmission enabled (in the case of selecting the cts function, transmission starts when the cts i pins input level is l.) uart0 transmit/receive control register 0 (address 34 16 ) uart1 transmit/receive control register 0 (address 3c 16 ) b7 b0 brg count source select bits 0 0 : f 2 0 1 : f 16 1 0 : f 64 1 1 : f 512 b1 b0 1 0 0 0 uart0 transmit/receive mode register (address 30 16 ) uart1 transmit/receive mode register (address 38 16 ) b7 b0 internal/external clock select bit 0: internal clock 1: external clock 5 : it may be 0 or 1. clock synchronous serial i/o mode 55 5 uart0 transmit interrupt control register (address 71 16 ) uart1 transmit interrupt control register (address 73 16 ) b7 b0 interrupt priority level select bits when using interrupts, set these bits to one of levels 1 to 7. when disabling interrupts, set these bits to level 0. uart0 baud rate register (brg0) (address 31 16 ) uart1 baud rate register (brg1) (address 39 16 ) b7 b0 can be set to 00 16 to ff 16 . ] necessary only when internal clock is selected. transmission starts. cts / rts select bit 0: cts function selected 1: rts function selected ( cts function disabled)
serial i/o 7721 group users manual 11C20 11.3 clock synchronous serial i/o mode fig. 11.3.3 detection of transmit completion [when not using interrupts] [when using interrupts] aaaaa aaaaa aaaaa aaaaa uarti transmit interrupt uart0 transmit interrupt control register (address 71 16 ) uart1 transmit interrupt control register (address 73 16 ) b7 b0 interrupt request bit checking start of transmission uart0 transmit/receive control register 0 (address 34 16 ) uart1 transmit/receive control register 0 (address 3c 16 ) b7 b0 aa aa checking completion of transmission transmit register empty flag 0: during transmitting 1: transmitting completed processing at completion of transmission 0: no interrupt requested 1: interrupt requested (transmission has started.) a uarti transmit interrupt request occurs when the transmission starts. note : this figure shows the bits and registers required for processing. refer to ?igures 11.3.5 and 11.3.6 for the change of flag state and the occurrence timing of an interrupt request. [when not using interrupts] [when using interrupts] a uarti transmit interrupt request occurs when the uarti transmit buffer register becomes empty. aaaaa aaaaa aaaaa aaaaa uarti transmit interrupt note : uart0 transmit buffer register (address 32 16 ) uart1 transmit buffer register (address 3a 16 ) b7 b0 writing of next transmit data set transmit data here. b0 uart0 transmit/receive control register 1 (address 35 ) uart1 transmit/receive control register 1 (address 3d ) b7 transmit buffer empty flag 0: data present in transmit buffer register 1: no data present in transmit buffer register (writing of next transmit data is possible.) checking state of uarti transmit buffer register 1 this figure shows the bits and registers required for processing. refer to ?igures 11.3.5 and 11.3.6 for the change of flag state and the occurrence timing of an interrupt request. 16 16 b0 fig. 11.3.2 writing data after start of transmission
serial i/o 7721 group users manual 11C21 11.3 clock synchronous serial i/o mode 11.3.3 transmit operation when the transmit conditions described in section 11.3.2 method of transmission are satisfied in the case of selecting an internal clock, a transfer clock is generated and the following operations are automatically performed after 1 cycle of the transfer clock has passed. when the transmit conditions are satisfied and the external clock is input to the clki pin in the case of selecting an external clock, the following operations are automatically performed. ?the uarti transmit buffer registers contents are transferred to the uarti transmit register. ?the transmit buffer empty flag is set to 1. ?the transmit register empty flag is cleared to 0. ?8 transfer clocks are generated (when an internal clock is selected). ?a uarti transmit interrupt request occurs, and the interrupt request bit is set to 1. the transmit operations are described below: data in the uarti transmit register is transmitted from the txd i pin synchronously with the falling edge of the transfer clock. this data is transmitted bit by bit sequentially beginning with the least significant bit. a when 1-byte data has been transmitted, the transmit register empty flag is set to 1. this indicates the completion of transmission. figure 11.3.4 shows the transmit operation. when an internal clock is selected, when the transmit conditions for the next data are satisfied at completion of the transmission, the transfer clock is generated continuously. accordingly, when performing transmission continuously, set the next transmit data to the uarti transmit buffer register during transmission (when the transmit register empty flag = 0). when the transmit conditions for the next data are not satisfied, the transfer clock stops at h level. figures 11.3.5 and 11.3.6 show examples of transmit timing. fig. 11.3.4 transmit operation transfer clock uarti transmit buffer register ? ? ? d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 7 d 6 d 5 d 4 d 3 d 2 d 7 d 6 d 5 d 4 d 3 transmit data ? ? ? msb b7 b0 d 0 d 1 d 2 d 7 lsb uarti transmit register
serial i/o 7721 group users manual 11C22 11.3 clock synchronous serial i/o mode d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 tc t clk clk i t end i txd i transfer clock transmit enable bit transmit buffer empty flag transmit register empty flag uarti transmit interrupt request bit data is set in uarti transmit buffer register. uarti transmit register uarti transmit buffer register. stopped because transmit enable bit = 0. t endi : next transmit conditions are examined when this signal level is h. endi is an internal signal. accordingly, it cannot be read from the external.) tc = t clk = 2(n+1) /fi 2 , f 16 , f 64 , f 512 ) cleared to 0 when interrupt request is accepted or cleared by software. the above timing diagram applies when the following conditions are satisfied: l internal clock selected l cts function not selected d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 tc cts i clk i t end i txd i transfer clock transmit enable bit transmit buffer empty flag transmit register empty flag uarti transmit interrupt request bit t clk data is set in uarti transmit buffer register. uarti transmit register uarti transmit buffer register. stopped because ctsi = h. stopped because transmit enable bit = 0. t endi : next transmit conditions are examined when this signal level is h. endi is an internal signal. accordingly, it cannot be read from the external.) tc = t clk = 2(n+1) /fi 2 , f 16 , f 64 , f 512 ) cleared to 0 when interrupt request is accepted or cleared by software. the above timing diagram applies when the following conditions are satisfied: l internal clock selected l cts function selected ____ fig. 11.3.5 example of transmit timing (when selecting internal clock, selecting cts function) ____ fig. 11.3.6 example of transmit timing (when selecting internal clock, not selecting cts function) (t fi: brgi count source frequency (f n: value set in brgi (t fi: brgi count source frequency (f n: value set in brgi
serial i/o 7721 group users manual 11C23 11.3 clock synchronous serial i/o mode 11.3.4 method of reception figures 11.3.7 and 11.3.8 show initial setting examples for relevant registers when receiving. reception is started when all of the following conditions ( to a ) are satisfied. when an external clock is selected, satisfy conditions to a with the following precondition satisfied. the clk i pins input is at h level. note: when an internal clock is selected, the above precondition is ignored. reception is enabled (receive enable bit = 1). transmission is enabled (transmit enable bit = 1). a dummy data is present in the uarti transmit buffer register (transmit buffer empty flag = 0) ____ ____ by connecting the rts i pin (receiver side) and cts i pin (transmitter side), the timing of transmission and that of reception can be matched. for details, refer to section 11.3.5 receive operation. when using interrupts, it is necessary to set the relevant registers to enable interrupts. for details, refer to chapter 7. interrupts. figure 11.3.9 shows processing after receive completion.
serial i/o 7721 group users manual 11C24 11.3 clock synchronous serial i/o mode fig. 11.3.7 initial setting example for relevant registers when receiving (1) ] necessary only when an internal clock is selected. uart0 baud rate register (brg0) (address 31 16 ) uart1 baud rate register (brg1) (address 39 16 ) b7 b0 can be set to 00 16 to ff 16 . 1 0 0 0 uart0 transmit/receive mode register (address 30 16 ) uart1 transmit/receive mode register (address 38 16 ) b7 b0 internal/external clock select bit 0: internal clock 1: external clock 5 : it may be 0 or 1. clock synchronous serial i/o mode continued to figure 11.3.8 on next page. uart0 transmit/receive control register 0 (address 34 16 ) uart1 transmit/receive control register 0 (address 3c 16 ) b7 b0 cts / rts select bit 0: cts function selected 1: rts function selected 555 brg count source select bits b1 b0 0 0 : f 2 0 1 : f 16 1 0 : f 64 1 1 : f 512
serial i/o 7721 group users manual 11C25 11.3 clock synchronous serial i/o mode fig. 11.3.8 initial setting example for relevant registers when receiving (2) port p8 direction register (address 14 16 ) b7 b0 0 r x d 0 pin 0 r x d 1 pin from preceding figure 11.3.7 uart0 receive interrupt control register (address 72 16 ) uart1 receive interrupt control register (address 74 16 ) b7 b0 interrupt priority level select bits when using interrupts, set these bits to one of levels 1 to 7. when disabling interrupts, set these bits to level 0. uart0 transmit buffer register (address 32 16 ) uart1 transmit buffer register (address 3a 16 ) b7 b0 set dummy data here. uart0 transmit/receive control register 1 (address 35 16 ) uart1 transmit/receive control register 1 (address 3d 16 ) b7 b0 transmit enable bit 1 : transmission enabled 1 1 receive enable bit 1 : reception enabled aaa aaa aaa reception starts. note: set the receive enable bit and the transmit enable bit to ??simultaneously.
serial i/o 7721 group users manual 11C26 11.3 clock synchronous serial i/o mode fig. 11.3.9 processing after receive completion [when not using interrupts] [when using interrupts] a uarti receive interrupt request occurs when reception is completed. aaa aaa aaa uarti receive interrupt processing after reading out receive data uart0 receive buffer register (address 36 16 ) uart1 receive buffer register (address 3e 16 ) b7 b0 reading of receive data receive data is read out from here. b7 b0 checking completion of reception 1 1 note : this figure shows the bits and registers required for processing. refer to ?igure 11.3.12 for the change of flag state and the occurrence timing of an interrupt request. b7 b0 checking error 1 1 overrun error flag 0: no overrun error 1: overrun error detected uart0 transmit/receive control register 1 (address 35 16 ) uart1 transmit/receive control register 1 (address 3d 16 ) uart0 transmit/receive control register 1 (address 35 16 ) uart1 transmit/receive control register 1 (address 3d 16 ) receive complete flag 0: reception not completed 1: reception completed
serial i/o 7721 group users manual 11C27 11.3 clock synchronous serial i/o mode 11.3.5 receive operation in the case of selecting an internal clock, when the receive conditions described in section 11.3.4 method of reception are satisfied, a transfer clock is generated and the reception is started after 1 cycle of the transfer clock has passed. in the case of selecting an external clock, when the receive conditions are satisfied, the uarti enters the receive enable state and reception is started by input of an external clock to the clki pin. ____ in the case of selecting an external clock and the rts function, when the uarti enters the receive enable ____ state, the rts i pins output level becomes l to inform the transmitter side that reception is enabled. when ____ ____ reception is started, the rts i pins output level becomes h. accordingly, by connecting the rts i pin to ____ the cts i pin of the transmitter side, the timing of transmission and that of reception can be matched. when ____ ____ an internal clock is selected, do not use the rts function. it is because the rts output becomes undefined. figure 11.3.10 shows a connection example. the receive operations are described below: the input signal of the rxd i pin is taken into the most significant bit of the uarti receive register synchronously with the rising edge of the transfer clock. the contents of the uarti receive register are shifted by 1 bit to the right. a steps and are repeated at each rising edge of the transfer clock. ? when 1-byte data is prepared in the uarti receive register, the contents of this register are transferred to the uarti receive buffer register. ? simultaneously with step ? , the receive complete flag is set to 1, and a uarti receive interrupt request occurs and its interrupt request bit is set to 1. the receive complete flag is cleared to 0 when the low-order byte of the uarti receive buffer register ____ is read out. the rts i pin outputs h level until the receive conditions are next satisfied (when selecting ____ the rts function). figure 11.3.11 shows the receive operation, and figure 11.3.12 shows an example of receive timing (when selecting an external clock). fig. 11.3.10 connection example txd i rxd i clk i txd i rxd i clk i transmitter side receiver side cts i rts i
serial i/o 7721 group users manual 11C28 11.3 clock synchronous serial i/o mode fig. 11.3.11 receive operation fig. 11.3.12 example of receive timing (when selecting external clock) uarti receive register d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 0 d 1 d 0 receive data msb b7 b0 lsb d 2 d 1 d 0 transfer clock uarti receive buffer register ? ? ? ? ? ? d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 1/f ext rts i clk i rxd i : when the clki pins input level is h, satisfy the following conditions: l transmit enable bit ? 1 l receive enable bit ? 1 l writing of dummy data to uarti transmit buffer register receive enable bit transmit enable bit transmit buffer empty flag dummy data is set to uarti transmit buffer register. uarti transmit register ? uarti transmit buffer register received data taken in uarti receive register ? uarti receive buffer register uarti receive buffer register is read out. receive complete flag uarti receive interrupt request bit the above timing diagram applies when the following setting conditions are satisfied: cleared to 0 when interrupt request is accepted or cleared by software. l external clock selected l rts function selected f ext : frequency of external clock
serial i/o 7721 group users manual 11C29 11.3 clock synchronous serial i/o mode 11.3.6 processing on detecting overrun error in the clock synchronous serial i/o mode, an overrun error can be detected. an overrun error occurs when the next data is prepared in the uarti receive register with the receive complete flag = 1 (data is present in the uarti receive buffer register) and next data is transferred to the uarti receive buffer register, in other words, when the next data is prepared before reading out the contents of the uarti receive buffer register. when an overrun error occurs, the next receive data is written into the uarti receive buffer register, and the uarti receive interrupt request bit is not changed. an overrun error is detected when data is transferred from the uarti receive register to the uarti receive buffer register and the overrun error flag is set to 1. the overrun error flag is cleared to 0 by clearing the serial i/o mode select bits to 000 2 or clearing the receive enable bit to 0. when an overrun error occurs during reception, initialize the overrun error flag and the uarti receive buffer register before performing reception again. when it is necessary to perform retransmission owing to an overrun error which occurs in the receiver side, set the uarti transmit buffer register again before starting transmission again. the method of initializing the uarti receive buffer register and that of setting the uarti transmit buffer register again are described below. (1) method of initializing uarti receive buffer register clear the receive enable bit to 0 (reception disabled). set the receive enable bit to 1 again (reception enabled). (2) method of setting uarti transmit buffer register again clear the serial i/o mode select bits to 000 2 (serial i/o invalid). set the serial i/o mode select bits to 001 2 again. a set the transmit enable bit to 1 (transmission enabled), and set the transmit data to the uarti transmit buffer register.
serial i/o 7721 group users manual 11C30 11.3 clock synchronous serial i/o mode [precautions for clock synchronous serial i/o mode] 1. the transfer clock is generated by operation of the transmit control circuit. accordingly, even when performing only reception, transmit operation (setting for transmission) must be performed. in this case, dummy data is output from the txd i pin. 2. when receiving, simultaneously set the receive enable bit and the transmit enable bit to 1. 3. when receiving data, write dummy data to the low-order byte of the uarti transmit buffer register for each reception of 1-byte data. 4. when selecting an external clock, satisfy the following 3 conditions with the input to the clk i pin = h level. set the transmit enable bit to 1. write transmit data to the uarti transmit buffer register. ____ ____ a input l level to the cts i pin (when selecting the cts function). set the receive enable bit to 1. set the transmit enable bit to 1. a write dummy data to the uarti transmit buffer register.
7721 group users manual 11C31 serial i/o 11.4 clock asynchronous serial i/o (uart) mode 11.4 clock asynchronous serial i/o (uart) mode table 11.4.1 lists the performance overview in the uart mode, and table 11.4.2 lists the functions of i/o pins in this mode. table 11.4.1 performance overview in uart mode item transfer data format transfer rate error detection start bit character bit (transfer data) parity bit stop bit when selecting internal clock when selecting external clock functions 1 bit 7 bits, 8 bits, or 9 bits 0 bit or 1 bit (odd or even can be selected.) 1 bit or 2 bits brgis output divided by 16 maximum 312.5 kbps 4 types (overrun, framing, parity, and summing) presence of error can be detected only by checking error sum flag. table 11.4.2 functions of i/o pins in uart mode method of selection (cannot be used as a programmable i/o port even when performing only reception.) port p8 direction register \ 1 s corresponding bit = 0 (can be used as a programmable i/o port when performing only transmission.) internal/external clock select bit \ 2 = 0 internal/external clock select bit = 1 ____ ____ cts/rts function select bit \ 3 = 0 ____ ____ cts/rts function select bit = 1 pin name txd i (p8 3 , p8 7 ) (note 1) rxd i (p8 2 , p8 6 ) clk i (p8 1 , p8 5 ) ____ ____ cts i / rts i (p8 0 , p8 4 ) (note 2) functions serial data output serial data input programmable i/o port brgis count source input ____ cts input ____ rts output port p8 direction register \ 1 : address 14 16 internal/external clock select bit \ 2 : bit 3 at addresses 30 16 , 38 16 ____ ____ cts/rts select bit \ 3 : bit 2 at addresses 34 16 , 3c 16 notes 1: the txd i pin outputs h level while transmission is not performed after selecting uartis operating mode. ____ ____ 2: the cts i /rts i pin can be used as an input port when performing only reception and not using ___ ___ the rts function (when selecting cts function).
serial i/o 7721 group users manual 11C32 11.4 clock asynchronous serial i/o (uart) mode 11.4.1 transfer rate (frequency of transfer clock) the transfer rate is determined by the brgi (addresses 31 16 , 39 16 ). when setting n into brgi, brgi divides the count source frequency by (n + 1). the brgis output is further divided by 16, and the resultant clock becomes the transfer clock. accordingly, n is expressed by the following formula. n = 1 f 16 5 b n: value set in brgi (00 16 to ff 16 ) f: brgis count source frequency (hz) b: transfer rate (bps) an internal clock or an external clock can be selected as the brgis count source with the internal/external clock select bit (bit 3 at addresses 30 16 , 38 16 ). when an internal clock is selected, the clock selected with the brg count source select bits (bits 0 and 1 at addresses 34 16 , 3c 16 ) becomes the brgis count source. when an external clock is selected, the clock input to the clk i pin becomes the brgis count source. set the same transfer rate for both transmitter and receiver sides. tables 11.4.3 and 11.4.4 list the setting examples of transfer rate. table 11.4.3 setting examples of transfer rate (1) brgis set value : n 79 (4f 16 ) 159 (9f 16 ) 79 (4f 16 ) 39 (27 16 ) 159 (9f 16 ) 79 (4f 16 ) 52 (34 16 ) 39 (27 16 ) 19 (13 16 ) actual time (bps) 300.00 600.00 1200.00 2400.00 4800.00 9600.00 14490.57 19200.00 38400.00 brgis count source f 64 f 16 f 16 f 16 f 2 f 2 f 2 f 2 f 2 brgis set value : n 80 (50 16 ) 162 (a2 16 ) 80 (50 16 ) 40 (28 16 ) 162 (a2 16 ) 80 (50 16 ) 53 (35 16 ) 40 (28 16 ) 24 (18 16 ) actual time (bps) 301.41 599.12 1205.63 2381.86 4792.94 9645.06 14467.59 19054.58 31250.00 brgis count source f 64 f 16 f 16 f 16 f 2 f 2 f 2 f 2 f 2 f(x in ) = 25 mhz f(x in ) = 24.576 mhz transfer rate (bps) 300 600 1200 2400 4800 9600 14400 19200 31250 38400 brgis set value : n 71 (47 16 ) 143 (8f 16 ) 71 (47 16 ) 35 (23 16 ) 143 (8f 16 ) 71 (47 16 ) 47 (2f 16 ) 35 (23 16 ) 23 (17 16 ) 21 (15 16 ) 17 (11 16 ) 11 (0b 16 ) 5 (05 16 ) 2 (02 16 ) actual time (bps) 300.00 600.00 1200.00 2400.00 4800.00 9600.00 14400.00 19200.00 28800.00 31418.18 38400.00 57600.00 115200.00 230400.00 brgis count source f 64 f 16 f 16 f 16 f 2 f 2 f 2 f 2 f 2 f 2 f 2 f 2 f 2 f 2 f(x in ) = 22.1184 mhz transfer rate (bps) 300 600 1200 2400 4800 9600 14400 19200 28800 31250 38400 57600 115200 230400 table 11.4.4 setting examples of transfer rate (2)
7721 group users manual 11C33 serial i/o 11.4 clock asynchronous serial i/o (uart) mode 11.4.2 transfer data format the transfer data format can be selected from formats shown in figure 11.4.1. bits 4 to 6 at addresses 30 16 and 38 16 select the transfer data format. (refer to figure 11.2.2. ) set the same transfer data format for both transmitter and receiver sides. figure 11.4.2 shows an example of transfer data format. table 11.4.5 lists each bit in transmit data. transfer data length of 7 bits 1st7data 1sp 1st7data 2sp 1st7data1par1sp 1st7data1par2sp transfer data length of 8 bits 1st8data 1sp 1st8data 2sp 1st8data1par1sp 1st8data1par2sp transfer data length of 9 bits 1st9data 1sp 1st9data 2sp 1st9data1par1sp 1st9data1par2sp st : start bit data : character bit (transfer data) par : parity bit sp : stop bit fig. 11.4.1 transfer data format name st start bit data character bit par parity bit sp stop bit functions l signal equivalent to 1 character bit which is added immediately before the character bits. it indicates start of data transmission. transmit data which is set in the uarti transmit buffer register. a signal that is added immediately after the character bits in order to improve data reliability. the level of this signal changes according to selection of odd/even parity in such a way that the sum of 1s in this bit and character bits is always an odd or even number. h level signal equivalent to 1 or 2 character bits which is added immediately after the character bits (or parity bit when parity is enabled). it indicates finish of data transmission. fig. 11.4.2 example of transfer data format table 11.4.5 each bit in transmit data time ?or the case where 1st?data?par?sp st lsb msb par sp st transmit/receive data data (8 bits) next transmit/receive data (when continuously transferring)
serial i/o 7721 group users manual 11C34 11.4 clock asynchronous serial i/o (uart) mode 11.4.3 method of transmission figure 11.4.3 shows an initial setting example for relevant registers when transmitting. the difference due to selection of transfer data length (7 bits, 8 bits, or 9 bits) is only that data length. when selecting a 7- or 8-bit data length, set the transmit data into the low-order byte of the uarti transmit buffer register. when selecting a 9-bit data length, set the transmit data into the low-order byte and bit 0 of the high-order byte. transmission is started when all of the following conditions ( to a ) are satisfied: transmit is enabled (transmit enable bit = 1). transmit data is present in the uarti transmit buffer register (transmit buffer empty flag = 0). ____ ____ a the cts i pins input is at l level (when the cts function selected). ____ note: when the cts function is not selected, condition a is ignored. ____ ____ by connecting the rts i pin (receiver side) and cts i pin (transmitter side), the timing of transmission and that of reception can be matched. for details, refer to section 11.4.6 receive operation. when using interrupts, it is necessary to set the relevant registers to enable interrupts. for details, refer to chapter 7. interrupts. figure 11.4.4 shows writing data after start of transmission, and figure 11.4.5 shows detection of transmit completion.
7721 group users manual 11C35 serial i/o 11.4 clock asynchronous serial i/o (uart) mode fig. 11.4.3 initial setting example for relevant registers when transmitting uart0 baud rate register (brg0) (address 31 16 ) uart1 baud rate register (brg1) (address 39 16 b7 b0 can be set to 00 16 to ff 16 . interrupt priority level select bits when using interrupts, set these bits to one of levels 1 to 7. when disabling interrupts, set these bits to level 0. uart0 transmit interrupt control register (address 71 16 ) uart1 transmit interrupt control register (address 73 16 ) b7 1 uart0 transmit/receive control register 1 (address 35 16 ) uart1 transmit/receive control register 1 (address 3d 16 ) b7 b0 transmit enable bit 1: transmission enabled transmission starts. b0 uart0 transmit buffer register (addresses 33 16 , 32 16 ) uart1 transmit buffer register (addresses 3b 16 , 3a 16 ) b7 b0 set transmit data here. uart0 transmit/receive mode register (address 30 16 ) uart1 transmit/receive mode register (address 38 16 ) b7 b0 internal/external clock select bit 0: internal clock 1: external clock 1 0 0: uart mode (7 bits) 1 0 1: uart mode (8 bits) 1 1 0: uart mode (9 bits) stop bit length select bit 0: 1 stop bit 1: 2 stop bits odd/even parity select bit 0: odd parity 1: even parity parity enable bit 0: parity disabled 1: parity enabled sleep select bit 0: sleep mode terminated (invalid) 1: sleep mode selected 1 b2 b1 b0 uart0 transmit/receive control register 0 (address 34 16 ) uart1 transmit/receive control register 0 (address 3c 16 ) b7 b0 brg count source select bits cts / rts select bit 0: cts function selected 1: rts function selected (cts function disabled) 0 0: f 2 0 1: f 16 1 0: f 64 1 1: f 512 b1 b0 (in the case of selecting the cts function, transmission starts when the cts i pins input level is l.) b8 b15
serial i/o 7721 group users manual 11C36 11.4 clock asynchronous serial i/o (uart) mode fig. 11.4.4 writing data after start of transmission [when not using interrupts] [when using interrupts] a uarti transmit interrupt request occurs when the uarti transmit buffer register becomes empty. aaaa aaaa aaaa uarti transmit interrupt note : uart0 transmit buffer register (addresses 33 16 , 32 16 ) uart1 transmit buffer register (addresses 3b 16 , 3a 16 ) b7 b0 writing of next transmit data set transmit data here. b0 uart0 transmit/receive control register 1 (address 35 16 ) uart1 transmit/receive control register 1 (address 3d 16 ) b7 transmit buffer empty flag 0: data present in transmit buffer register 1: no data present in transmit buffer register (writing of next transmit data is possible.) checking state of uarti transmit buffer register 1 this figure shows the bits and registers required for processing. refer to ?igures 11.4.6 to 11.4.8 for the change of flag state and the occurrence timing of an interrupt request. b0 b8 b15
7721 group users manual 11C37 serial i/o 11.4 clock asynchronous serial i/o (uart) mode fig. 11.4.5 detection of transmit completion [when not using interrupts] [when using interrupts] aaa aaa uarti transmit interrupt uart0 transmit interrupt control register (address 71 16 ) uart1 transmit interrupt control register (address 73 16 ) b7 b0 interrupt request bit checking start of transmission uart0 transmit/receive control register 0 (address 34 16 ) uart1 transmit/receive control register 0 (address 3c 16 ) b7 b0 checking completion of transmission. transmit register empty flag 0: during transmission 1: transmission completed processing at completion of transmission 0: 1: no interrupt requested interrupt requested (transmission has started.) a uarti transmit interrupt request occurs when transmission starts. note : this figure shows the bits and registers required for processing. refer to ?igures 11.4.6 to 11.4.8 for the change of flag state and the occurrence timing of an interrupt request.
serial i/o 7721 group users manual 11C38 11.4 clock asynchronous serial i/o (uart) mode 11.4.4 transmit operation when the receive conditions described in section 11.4.3 method of transmission are satisfied, a transfer clock is generated and the following operations are automatically performed after 1 cycle of the transfer clock has passed. ?the uarti transmit buffer registers contents are transferred to the uarti transmit register. ?the transmit buffer empty flag is set to 1. ?the transmit register empty flag is cleared to 0. ?a uarti transmit interrupt request occurs and the interrupt request bit is set to 1. the transmit operations are described below: data in the uarti transmit register is transmitted from the txd i pin. this data is transmitted bit by bit sequentially in order of st ? data (lsb) ? ??? ? data (msb) ? par ? sp according to the transfer data format. a the transmit register empty flag is set to 1 at the center of the stop bit (or the second stop bit when selecting 2-stop bits), indicating completion of transmission. additionally, whether the transmit conditions for the next data are satisfied or not is examined. when the transmit conditions for the next data are satisfied in step a , the start bit is generated following the stop bit, and the next data is transmitted. when performing transmission continuously, set the next transmit data in the uarti transmit buffer register during transmission (when the transmit register empty flag = 0). when the transmit conditions for the next data are not satisfied, the txd i pin outputs h level and the transfer clock stops. figures 11.4.6 and 11.4.7 show examples of transmit timing when the transfer data length = 8 bits, and figure 11.4.8 shows an example of transmit timing when the transfer data length = 9 bits.
7721 group users manual 11C39 serial i/o 11.4 clock asynchronous serial i/o (uart) mode fig. 11.4.7 example of transmit timing when transfer data length = 8 bits (when parity enabled, ____ selecting 1 stop bit, selecting cts function) fig. 11.4.6 example of transmit timing when transfer data length = 8 bits (when parity enabled, ____ selecting 1 stop bit, not selecting cts function) tc d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st p sp d 0 d 1 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st p st sp t endi txd i t endi : next transmit conditions are examined when this signal level is h. (t endi is an internal signal. accordingly, it cannot be read from the external.) tc: 16(n + 1)/fi or 16(n + 1)/f ext fi: brgis count source frequency (f 2 , f 16 , f 64 , f 512 ) f ext : brgis count source frequency (external clock) n: value set in brgi transfer clock transmit enable bit transmit buffer empty flag transmit register empty flag uarti transmit interrupt request bit data is set in uarti transmit buffer register. start bit parity bit cleared to 0 when interrupt request is accepted or cleared by software. the above timing diagram applies when the following conditions are satisfied: l parity enabled l 1 stop bit l cts function not selected uarti transmit register uarti transmit buffer register stopped because transmit enable bit = 0 stop bit the above timing diagram applies when the following conditions are satisfied: l parity enabled l 1 stop bit l cts function selected tc d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st p sp d 0 d 1 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st p sp st t endi txd i t endi : next transmit conditions are examined when this signal level is h. (t endi is an internal signal. accordingly, it cannot be read from the external.) tc = 16(n + 1)/fi or 16(n + 1)/f ext fi: brgis count source frequency (f 2 , f 16 , f 64 , f 512 ) f ext : brgis count source frequency (external clock) n: value set in brgi transfer clock transmit buffer empty flag transmit register empty flag uarti transmit interrupt request bit data is set in uarti transmit buffer register. start bit parity bit cleared to 0 when interrupt request is accepted or cleared by software. uarti transmit register stopped because transmit enable bit = 0 stop bit uarti transmit buffer register transmit enable bit ctsi stopped because cts = h
serial i/o 7721 group users manual 11C40 11.4 clock asynchronous serial i/o (uart) mode the above timing diagram applies when the following conditions are satisfied: l parity disabled l 2 stop bits l cts function disabled d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st d 8 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st sp d 0 d 1 st d 8 sp sp sp tc t endi txd i t endi : next transmit conditions are examined when this signal level is h. (t endi is an internal signal. accordingly, it cannot be read from the external.) tc = 16(n + 1)/fi or 16(n + 1)/f ext fi: brgi count source frequency (f 2 , f 16 , f 64 , f 512 ) f ext : brgi count source frequency (external clock) n: value set in brgi transfer clock transmit enable bit transmit buffer empty flag transmit register empty flag uarti transmit interrupt request bit data is set in uarti transmit buffer register. start bit cleared to 0 when interrupt request is accepted or cleared by software. uarti transmit register uarti transmit buffer register stopped because transmit enable bit = 0 stop bit stop bit fig. 11.4.8 example of transmit timing when transfer data length = 9 bits (when parity disabled, ____ selecting 2 stop bits, not selecting cts function)
7721 group users manual 11C41 serial i/o 11.4 clock asynchronous serial i/o (uart) mode 11.4.5 method of reception figure 11.4.9 shows an initial setting example for relevant registers when receiving. reception is started when all of the following conditions ( and ) are satisfied: reception is enabled (receive enable bit = 1). the start bit is detected. ____ ____ by connecting the rts i pin (receiver side) and cts i pin (transmitter side), the timing of transmission and that of reception can be matched. for details, refer to section 11.4.6 receive operation. when using interrupts, it is necessary to set the relevant registers to enable interrupts. for details, refer to chapter 7. interrupts. figure 11.4.10 shows processing after receive completion.
serial i/o 7721 group users manual 11C42 11.4 clock asynchronous serial i/o (uart) mode fig. 11.4.9 initial setting example for relevant registers when receiving reception starts when the start bit is detected. uart0 baud rate register (brg0) (address 31 16 ) uart1 baud rate register (brg1) (address 39 16 ) b7 b0 can be set to 00 16 to ff 16 . uart0 receive interrupt control register (address 72 16 ) uart1 receive interrupt control register (address 74 16 ) b7 b0 interrupt priority level select bits when using interrupts, set these bits to one of levels 1 to 7. when disabling interrupts, set these bits to level 0. note : set the transfer data format in the same way as set on the transmitter side. 1 uart0 transmit/receive control register 1 (address 35 16 ) uart1 transmit/receive control register 1 (address 3d 16 ) b7 b0 receive enable bit 1: reception enabled uart0 transmit/receive mode register (address 30 16 ) uart1 transmit/receive mode register (address 38 16 ) b7 b0 internal/external clock select bit 0: internal clock 1: external clock 1 0 0: uart mode (7 bits) 1 0 1: uart mode (8 bits) 1 1 0: uart mode (9 bits) stop bit length select bit 0: 1 stop bit 1: 2 stop bits odd/even parity select bit 0: odd parity 1: even parity parity enable bit 0: parity disabled 1: parity enabled sleep select bit 0: sleep mode terminated (invalid) 1: sleep mode selected 1 b2b1b0 uart0 transmit/receive control register 0 (address 34 ) uart1 transmit/receive control register 0 (address 3c ) b7 b0 brg count source select bits cts / rts select bit 0 : cts function selected 1 : rts function selected 0 0 : f 2 0 1 : f 16 1 0 : f 64 1 1 : f 512 b1b0 16 16 port p8 direction register (address 14 16 ) b7 b0 0 0 rxd 0 pin rxd 1 pin
7721 group users manual 11C43 serial i/o 11.4 clock asynchronous serial i/o (uart) mode fig. 11.4.10 processing after receive completion [when not using interrupts] [when using interrupts] a uarti receive interrupt request occurs when reception is completed. aaa aaa uarti receive interrupt processing after reading out receive data uart0 receive buffer register (addresses 37 16 , 36 16 ) uart1 receive buffer register (addresses 3f 16 , 3e 16 ) b15 b8 reading of receive data read out receive data. b7 b0 0 0 0 0 0 0 0 uart0 transmit/receive control register 1 (address 35 16 ) uart1 transmit/receive control register 1 (address 3d 16 ) b7 b0 receive complete flag 0 : reception not completed 1 : reception completed checking completion of reception 1 uart0 transmit/receive control register 1 (address 35 16 ) uart1 transmit/receive control register 1 (address 3d 16 ) b7 b0 checking error framing error flag parity error flag error sum flag 0 : no error 1 : error detected 1 note : this figure shows the bits and registers required for processing. refer to ?igure 11.4.12 for the change of flag state and the occurrence timing of an interrupt request. uart0 transmit/receive control register 1 (address 35 16 ) uart1 transmit/receive control register 1 (address 3d 16 ) b7 b0 checking error overrun error flag 0 : no overrun error 1 : overrun error detected 1
serial i/o 7721 group users manual 11C44 11.4 clock asynchronous serial i/o (uart) mode 11.4.6 receive operation when the receive enable bit is set to 1, the uarti enters the receive enable state. after this, reception starts when st is detected and a transfer clock is generated. ____ ____ in the case of selecting the rts function, when the reception is enabled, the rts i pins output level ____ becomes l to inform the transmitter side that reception is enabled. when reception is started, the rts i ____ ____ pins output level becomes h. accordingly, by connecting the rts i pin to the cts i pin of the transmitter side, the timing of transmission and that of reception can be matched. figure 11.4.11 shows an connection example. the receive operation is described below. the input signal of the rxd i pin is taken into the most significant bit of the uarti receive register synchronously with the transfer clocks rising edge. the contents of the uarti receive register are shifted by 1 bit to the right. a steps and are repeated at each rising edge of the transfer clock. ? when one set of data has been prepared, in other words, when the shift has been performed several times according to the selected data format, the uarti receive registers contents are transferred to the uarti receive buffer register. ? simultaneously with step ? , the receive complete flag is set to 1. additionally, a uarti receive interrupt request occurs and its interrupt request bit is set to 1. the receive complete flag is cleared to 0 when the low-order byte of the uarti receive buffer register ____ ____ is read out. the rts i pins output level becomes l simultaneously with step ? (when selecting the rts function). figure 11.4.12 shows an example of receive timing when the transfer data length = 8 bits. txd i rxd i txd i rxd i transmitter side receiver side cts i rts i fig. 11.4.11 connection example
7721 group users manual 11C45 serial i/o 11.4 clock asynchronous serial i/o (uart) mode fig. 11.4.12 example of receive timing when transfer data length = 8 bits (when parity disabled, ____ selecting 1 stop bit, selecting rts function) d 0 d 1 d 7 rxd i rts i the above timing diagram applies when the following conditions are satisfied: l parity disabled l 1 stop bit l rts function selected brgi count source receive enable bit transfer clock receive complete flag uarti receive interrupt request bit start bit sampled l received data taken in stop bit at falling edge of start bit, transfer clock is generated and reception started. uarti receive register uarti receive buffer register cleared to 0 when interrupt request is accepted or cleared by software.
serial i/o 7721 group users manual 11C46 11.4 clock asynchronous serial i/o (uart) mode 11.4.7 processing on detecting error in the uart mode, 3 types of errors can be detected. each error can be detected when the data in the uarti receive register is transferred to the uarti receive buffer register, and the corresponding error flag is set to 1. when any error occurs, the error sum flag is set to 1. accordingly, presence of errors can be judged by using the error sum flag. table 11.4.6 lists conditions for setting each error flag to 1 and method for clearing it to 0. table 11.4.6 conditions set to 1 and method cleared to 0 for each error flag method for being cleared to 0 ?clear the serial i/o mode select bits to 000 2 . ?clear the receive enable bit to 0. ?clear the serial i/o mode select bits to 000 2 . ?clear the receive enable bit to 0. ?read out the low-order byte of the uarti receive buffer register. ?clear the serial i/o mode select bits to 000 2 . ?clear the receive enable bit to 0. ?read out the low-order byte of the uarti receive buffer register. ?clear the all error flags, which are overrun, framing and parity error flags. error flag overrun error flag framing error flag parity error flag error sum flag conditions for being set to 1 when the next data is prepared in the uarti receive register with the receive complete flag = 1 (i.e., data is present in the uarti receive buffer register). in other words, when the next data is prepared before the contents of the uarti receive buffer register are read out. (note) [uarti receive interrupt request bit is not changed.] when the number of detected stop bits does not match the set number of stop bits. [uarti receive interrupt request bit is set to 1.] when the sum of 1s in the parity bit and character bits does not match the set number of 1s. [uarti receive interrupt request bit is set to 1.] when 1 or more errors listed above occur. note: the next data is written into the uarti receive buffer register. when an error occurs during reception, initialize the error flag and the uarti receive buffer register, and then perform reception again. when it is necessary to perform retransmission owing to an error which occurs in the receiver side during transmission, set the uarti transmit buffer register again, and then restarts transmission. the method of initializing the uarti receive buffer register and that of setting the uarti transmit buffer register again are described below. (1) method of initializing uarti receive buffer register clear the receive enable bit to 0 (reception disabled). set the receive enable bit to 1 again (reception enabled). (2) method of setting uarti transmit buffer register again clear the serial i/o mode select bits to 000 2 (serial i/o invalid). set the serial i/o mode select bits again. a set the transmit enable bit to 1 (transmission enabled), and set the transmit data to the uarti transmit buffer register.
7721 group users manual 11C47 serial i/o 11.4 clock asynchronous serial i/o (uart) mode 11.4.8 sleep mode this mode is used to transfer data between the specified microcomputers, which are connected by using uarti. the sleep mode is selected by setting the sleep select bit (bit 7 at addresses 30 16 , 38 16 ) to 1 when receiving. in the sleep mode, receive operation is performed when the msb (d 8 when the transfer data is 9 bits length, d 7 when it is 8 bits length, d 6 when it is 7 bits length) of the receive data is 1. receive operation is not performed when the msb is 0. (the uarti receive registers contents are not transferred to the uarti receive buffer register. additionally, the receive complete flag and error flags do not change and a uarti receive interrupt request does not occur.) the following shows an usage example of the sleep mode when the transfer data is 8 bits length. set the same transfer data format for the master and slave microcomputers. select the sleep mode for the slave microcomputers. transmit data, which has 1 in bit 7 and the address of the slave microcomputer to be communicated in bits 0 to 6, from the master microcomputer to all slave microcomputers. a all slave microcomputers receive data of step . (at this time, a uarti receive interrupt request occurs.) ? for all slave microcomputers, check in the interrupt routine whether bits 0 to 6 in the receive data match their own addresses. ? for the slave microcomputer of which address matches bits 0 to 6 in the receive data, terminate the sleep mode. (do not terminate the sleep mode for the other slave microcomputers.) by performing steps to ? , the microcomputer which performs transfer is specified. ? transmit data, which has 0 in bit 7, from the master microcomputer. (only the microcomputer specified in steps to ? can receive this data. the other microcomputers do not receive this data.) ? by repeating step ? , transfer can be performed between two specific microcomputers continuously. when communicating with another microcomputer, perform steps to ? in order to specify the new slave microcomputer. fig. 11.4.13 sleep mode master slave b slave a slave d slave c data is transferred between the master microcomputer and one specific slave microcomputer selected from multiple slave microcomputers.
serial i/o 7721 group users manual 11C48 11.4 clock asynchronous serial i/o (uart) mode memorandum
chapter 12 a-d converter 12.1 overview 12.2 block description 12.3 a-d conversion method 12.4 absolute accuracy and differential non-linearity error 12.5 one-shot mode 12.6 repeat mode 12.7 single sweep mode 12.8 repeat sweep mode 12.9 precautions for a-d converter
a-d converter 7721 group users manual 12C2 12.1 overview table 12.1.1 lists the performance specifications of the a-d converter. table 12.1.1 performance specifications of a-d converter 12.1 overview item a-d conversion method resolution absolute accuracy analog input pin conversion rate per analog input pin performance specifications successive approximation conversion method 8 bits 3 lsb 8 pins (an 0 to an 7 ) ( note ) 57 f ad ] cycles f ad ] : a-d converters operation clock the a-d converter has the 4 operation modes listed below. ?one-shot mode this mode is used to perform the operation once for a voltage input from one selected analog input pin. ?repeat mode this mode is used to perform the operation repeatedly for a voltage input from one selected analog input pin. ?single sweep mode this mode is used to perform the operation for voltages input from multiple selected analog input pins, one at a time. ?repeat sweep mode this mode is used to perform the operation repeatedly for voltages input from multiple selected analog input pins.
a-d converter 7721 group users manual 12C3 12.2 block description figure 12.2.1 shows the block diagram of the a-d converter. registers relevant to the a-d converter are described below. 12.2 block description fig. 12.2.1 block diagram of a-d converter av ss v ref v ref an 0 an 1 an 2 an 3 an 4 an 5 an 6 an 7 /ad trg v in 1/2 f 2 1/2 ad decoder resistor ladder network successive approximation register a-d register 2 a-d register 3 a-d register 4 a-d register 5 a-d register 6 a-d register 7 a-d register 0 a-d register 1 a-d control register comparator selector data bus (even) a-d sweep pin select register
a-d converter 7721 group users manual 12C4 12.2.1 a-d control register figure 12.2.2 shows the structure of the a-d control register. the a-d operation mode select bit selects the operation mode of the a-d converter. the other bits are described below. 12.2 block description fig. 12.2.2 structure of a-d control register (1) analog input select bits (bits 2 to 0) these bits are used to select an analog input pin in the one-shot mode and repeat mode. pins which are not selected as analog input pins function as programmable i/o ports. these bits must be set again when the user switches the a-d operation mode to the one-shot mode or repeat mode after a-d conversion is performed in the single sweep mode or repeat sweep mode. b7 b6 b5 b4 b3 b2 b1 b0 a-d control register (address 1e 16 ) bit a-d conversion frequency ( ad ) select bit a-d conversion start bit trigger select bit 4 a-d operation mode select bits 2 1 0 bit name at reset 0 undefined rw functions 0 0 0 : an 0 selected 0 0 1 : an 1 selected 0 1 0 : an 2 selected 0 1 1 : an 3 selected 1 0 0 : an 4 selected 1 0 1 : an 5 selected 1 1 0 : an 6 selected 1 1 1 : an 7 selected (note 2) b2 b1 b0 0 : internal trigger 1 : external trigger 0 0 : one-shot mode 0 1 : repeat mode 1 0 : single sweep mode 1 1 : repeat sweep mode 0 : stop a-d conversion 1 : start a-d conversion b4 b3 notes 1: these bits are ignored in the single sweep and repeat sweep mode. (they may be either 0 or 1.) 2: when an external trigger is selected, the an 7 pin cannot be used as an analog input pin. 3: writing to each bit (except bit 6) of the a-d control register must be performed while the a-d converter halts. analog input select bits (valid in one-shot and repeat modes) (note 1) 3 7 6 5 undefined undefined rw rw rw rw rw rw rw rw 0 0 0 0 0 : f 2 divided by 4 1 : f 2 divided by 2
a-d converter 7721 group users manual 12C5 (2) trigger select bit (bit 5) this bit is used to select the source of trigger occurrence. (refer to section (3) a-d conversion start bit. ) (3) a-d conversion start bit (bit 6) l when internal trigger is selected setting this bit to 1 generates a trigger, causing the a-d converter to start operating. clearing this bit to 0 causes the a-d converter to stop operating. in the one-shot mode or single sweep mode, this bit is cleared to 0 after the operation is completed. in the repeat mode or repeat sweep mode, the a-d converter continues operating until this bit is cleared to 0 by software. l when external trigger is selected ______ when the ad trg pin level goes from h to l with this bit = 1, a trigger occurs, causing the a-d converter to start operating. the a-d converter stops when this bit is cleared to 0. in the one-shot mode or single sweep mode, this bit remains set to 1 even after the operation is completed. in the repeat mode or repeat sweep mode, the a-d converter continues operating until this bit is cleared to 0 by software. (4) a-d conversion frequency ( f ad ) select bit (bit 7) as listed in table 12.2.1, the conversion time of the a-d converter varies depending on the operating clock ( f ad ) selected by this bit. since the a-d converters comparator consists of capacity coupling amplifiers, keep that f ad 3 250 khz during a-d conversion . 12.2 block description table 12.2.1 conversion time per one analog input pin (unit: s) 1 f 2 /2 28.5 14.25 9.12 0 f 2 /4 57.0 28.5 18.24 a-d conversion frequency ( f ad ) select bit f ad conversion time f(x in ) = 8 mhz f(x in ) = 16 mhz f(x in ) = 25 mhz
a-d converter 7721 group users manual 12C6 12.2 block description 12.2.2 a-d sweep pin select register figure 12.2.3 shows the structure of the a-d sweep pin select register. fig. 12.2.3 structure of a-d control register 1 (1) a-d sweep pin select bits (bits 1 and 0) these bits are used to select analog input pins in the single sweep mode or repeat sweep mode. in the single sweep mode and repeat sweep mode, pins which are not selected as analog input pins function as programmable i/o ports. b7 b6 b5 b4 b3 b2 b1 b0 a-d sweep pin select register (address 1f 16 ) bit 1 0 bit name at reset 1 undefined rw functions notes 1: these bits are invalid in the one-shot and repeat modes. (they may be either 0 or 1.) 2: when selecting an external trigger, the an 7 pin cannot be used as an analog input pin. 3: writing to each bit of the a-d sweep pin select register must be performed while the a-d converter halts. 7 to 2 rw 0 0 : an 0 , an 1 (2 pins) 0 1 : an 0 to an 3 (4 pins) 1 0 : an 0 to an 5 (6 pins) 1 1 : an 0 to an 7 (8 pins) (note 2) a-d sweep pin select bits (valid in single sweep and repeat sweep mode ) (note 1) b1 b0 1 rw nothing is assigned. C
a-d converter 7721 group users manual 12C7 12.2.3 a-d register i (i = 0 to 7) figure 12.2.4 shows the structure of the a-d register i. when the a-d conversion is completed, the conversion result (contents of the successive approximation register) is stored into this register. each a- d register i corresponds to an analog input pin (an i ). 12.2 block description fig. 12.2.4 structure of a-d register i a-d register 0 (addresses 20 16 ) a-d register 1 (addresses 22 16 ) a-d register 2 (addresses 24 16 ) a-d register 3 (addresses 26 16 ) a-d register 4 (addresses 28 16 ) a-d register 5 (addresses 2a 16 ) a-d register 6 (addresses 2c 16 ) a-d register 7 (addresses 2e 16 ) bit 7 to 0 at reset undefined rw functions ro reads an a-d conversion result. b7 b6 b5 b4 b3 b2 b1 b0
a-d converter 7721 group users manual 12C8 12.2.4 a-d conversion interrupt control register figure 12.2.5 shows the structure of the a-d conversion interrupt control register. for details about interrupts, refer to chapter 7. interrupts. 12.2 block description fig. 12.2.5 structure of a-d conversion interrupt control register (1) interrupt priority level select bits (bits 2 to 0) these bits select an a-d conversion interrupts priority level. when using a-d conversion interrupts, select one of the priority levels (1 to 7). when an a-d conversion interrupt request occurs, its priority level is compared with the processor interrupt priority level (ipl). the requested interrupt is enabled only when its priority level is higher than the ipl. (however, this applies when the interrupt disable flag (i) = 0.) to disable a-d conversion interrupts, set these bits to 000 2 (level 0). (2) interrupt request bit (bit 3) this bit is set to 1 when an a-d conversion interrupt request occurs. this bit is automatically cleared to 0 when the a-d conversion interrupt request is accepted. this bit can be set to 1 or cleared to 0 by software. b7 b6 b5 b4 b3 b2 b1 b0 a-d conversion interrupt control register (address 70 16 ) bit 7 to 4 interrupt request bit 2 1 0 bit name at reset 0 rw functions 0 0 0 : level 0 (interrupt disabled) 0 0 1 : level 1 low level 0 1 0 : level 2 0 1 1 : level 3 1 0 0 : level 4 1 0 1 : level 5 1 1 0 : level 6 1 1 1 : level 7 high level b2 b1 b0 0 : no interrupt requested 1 : interrupt requested interrupt priority level select bits 3 rw rw rw rw undefined 0 0 0 nothing is assigned.
a-d converter 7721 group users manual 12C9 12.2.5 port p7 direction register input pins of the a-d converter are multiplexed with port p7. when using these pins as a-d converters input pins, set the corresponding bits of the port p7 direction register to 0 to set these port pins for the input mode. figure 12.2.6 shows the relationship between the port p7 direction register and a-d converters input pins. 12.2 block description fig. 12.2.6 relationship between port p7 direction register and a-d converters input pins bit corresponding pin functions 0 1 2 3 4 5 6 7 an 0 pin 0 : input mode 1 : output mode when using these pins as a-d converter? input pins, set the corresponding bits to ?. port p7 direction register (address 11 16 ) b1 b0 b2 b3 b4 b5 b6 b7 at reset rw 0 0 0 0 0 0 0 0 rw rw rw rw rw rw rw rw an 1 pin an 2 pin an 3 pin an 4 pin an 5 pin an 6 pin an 7 /ad trg pin
7721 group users manual 12C10 a-d converter 12.3 a-d conversion method the a-d converter compares the comparison voltage (v ref ), which is internally generated according to the contents of the successive approximation register, with the analog input voltage (v in ), which is input from the analog input pin (an i ). by reflecting the comparison result on the successive approximation register, v in is converted into a digital value. when a trigger is generated, the a-d converter performs the following processing: determining bit 7 of the successive approximation register the a-d converter compares v ref with v in . at this time, the contents of the successive approximation register is 10000000 2 (initial value). bit 7 of the successive approximation register changes according to the comparison result as follows: when v ref < v in , bit 7 = 1 when v ref > v in , bit 7 = 0 determining bit 6 of the successive approximation register after setting bit 6 of the successive approximation register to 1, the a-d converter compares v ref with v in . bit 6 changes according to the comparison result as follows: when v ref < v in , bit 6 = 1 when v ref > v in , bit 6 = 0 a determining bits 5 to 0 of the successive approximation register operations in are performed for bits 5 to 0. when bit 0 is determined, the contents (conversion result) of the successive approximation register is transferred to the a-d register i. the comparison voltage (v ref ) is generated according to the latest contents of the successive approximation register. table 12.3.1 lists the relationship between the successive approximation registers contents and v ref . table 12.3.2 lists changes of the successive approximation register and v ref during the a-d conversion. figure 12.3.1 shows the ideal a-d conversion characteristics. table 12.3.1 relationship between successive approximation registers contents and v ref 12.3 a-d conversion method v ref ] 256 successive approximation registers contents: n 0 1 to 255 5 (n C 0.5) v ref (v) 0 v ref ] : reference voltage
7721 group users manual 12C11 a-d converter table 12.3.2 change in successive approximation register and v ref during a-d conversion 12.3 a-d conversion method 1 1 n 7 0000000 0000000 100 0000 n 7 n 6 10 00 00 n 7 n 6 n 5 n 4 n 3 n 2 n 1 1 n 7 n 6 n 5 n 4 n 3 n 2 n 1 n 0 b7 b0 1st comparison result 2nd comparison result successive approximation register change of v ref a-d converter halt 1st comparison 2nd comparison 3rd comparison 8th comparison conversion complete C 2 v ref 512 v ref : 2 v ref 2 v ref 4 v ref C 512 v ref 2 v ref 4 v ref 8 v ref C 512 v ref 2 v ref 4 v ref 8 v ref ...... v ref 256 C 512 v ref [v] [v] [v] [v] [v] 4 v ref ?n 7 =1 4 v ref ?n 7 =0 + C 8 v ref 8 v ref ?n 6 =1 ?n 6 =0 + C : : : : : fig. 12.3.1 ideal a-d conversion characteristics 00 16 01 16 02 16 03 16 fe 16 ff 16 analog input voltage v ref 256 5 1 v ref 256 5 2 v ref 256 5 3 5 253 v ref 256 v ref 256 5 254 v ref 256 5 255 v ref v ref 256 5 0.5 ldeal a-d conversion characteristics 0 a-d conversion result fd 16
7721 group users manual 12C12 a-d converter 12.4 absolute accuracy and differential non-linearity error 12.4 absolute accuracy and differential non-linearity error the a-d converters accuracy is described below. refer to section appendix 12.3 a-d converter standard characteristics , also. 12.4.1 absolute accuracy the absolute accuracy is the difference expressed in the lsb between the actual a-d conversion result and the output code of an a-d converter with ideal characteristics. the analog input voltage when measuring the accuracy is assumed to be the mid point of the input voltage width that outputs the same output code from an a-d converter with ideal characteristics. for example, when v ref = 5.12 v, 1 lsb width is 20 mv, and 0 mv, 20 mv, 40 mv, 60 mv, 80 mv, ... are selected as the analog input voltages. the absolute accuracy = 3 lsb indicates that when the analog input voltage is 100 mv, the output code expected from an ideal a-d conversion characteristics is 005 16 , however the actual a-d conversion result is between 002 16 to 008 16 . the absolute accuracy includes the zero error and the full-scale error. the absolute accuracy is degraded when v ref is lowered. any of the output codes for analog input voltages from v ref to av cc is ff 16 . 00 16 01 16 02 16 03 16 04 16 05 16 06 16 0 20 40 60 80 100 120 140 160 180 200 220 07 16 08 16 09 16 0a 16 0b 16 +3 lsb ? lsb ideal a-d conversion characteristics analog input voltage (mv) output code (a-d conversion result) fig. 12.4.1 absolute accuracy of a-d converter
7721 group users manual 12C13 a-d converter 12.4.2 differential non-linearity error the differential non-linearity error indicates the difference between the 1 lsb step width (the ideal analog input voltage width while the same output code is expected to output) of an a-d converter with ideal characteristics and the actual measured step width (the actual analog input voltage width while the same output code is output). for example, when v ref = 5.12 v, the 1 lsb width of an a-d converter with ideal characteristics is 20 mv, however when the differential non-linearity error is 1 lsb, the actual measured 1 lsb width is 0 to 40 mv. 12.4 absolute accuracy and differential non-linearity error fig. 12.4.2 differential non-linearity error 00 16 01 16 02 16 03 16 04 16 05 16 06 16 0 20 40 60 80 100 120 140 160 180 07 16 08 16 09 16 output code (a-d conversion result) differential non-linearity error analog input voltage (mv) 1 lsb width with ideal a-d conversion characteristics
7721 group users manual 12C14 a-d converter 12.5 one-shot mode 12.5 one-shot mode in the one-shot mode, the operation for the input voltage from the one selected analog input pin is performed once, and the a-d conversion interrupt request occurs when the operation is completed. 12.5.1 settings for one-shot mode figure 12.5.1 shows an initial setting example for registers relevant to the one-shot mode. when using an interrupt, it is necessary to set the relevant registers to enable the interrupt. refer to chapter 7. interrupts for more descriptions.
7721 group users manual 12C15 a-d converter 12.5 one-shot mode fig. 12.5.1 initial setting example for registers relevant to one-shot mode b7 b0 a-d control register (address 1e 16 ) 00 0 0 0 0 : an 0 selected 0 0 1 : an 1 selected 0 1 0 : an 2 selected 0 1 1 : an 3 selected 1 0 0 : an 4 selected 1 0 1 : an 5 selected 1 1 0 : an 6 selected 1 1 1 : an 7 selected b1 b0 b2 trigger select bit 0 : internal trigger 1 : external trigger a-d conversion start bit 0: stop a-d conversion analog input select bits a-d conversion frequency ( ad ) select bit 0 : f 2 divided by 4 1 : f 2 divided by 2 l a-d control register one-shot mode note : writing to each bit (except bit 6) of the a-d control register must be performed while the a-d converter halts (before a trigger occurs). l interrupt priority level b7 b0 a-d conversion interrupt control register (address 70 16 ) interrupt priority level select bits set to a level between 1 to 7 when using this interrupt. set to a level 0 when disabling this interrupt. l set a-d conversion start bit to 1 b7 b0 a-d control register (address 1e 16 ) 1 a-d conversion start bit when external trigger is selected when internal trigger is selected input falling edge to ad trg pin trigger occur operation start b7 b0 port p7 direction register (address 11 16 ) l port p7 direction register set the bits corresponding to analog input pins to 0. set bit 7 to 0 when selecting external trigger. an 1 an 2 an 3 an 5 an 6 an 7 an 4 an 0
7721 group users manual 12C16 a-d converter 12.5 one-shot mode 12.5.2 one-shot mode operation description (1) when an internal trigger is selected the a-d converter starts operation when the a-d conversion start bit is set to 1. the a-d conversion is completed after 57 cycles of f ad . then, the contents of the successive approximation register (conversion result) are transferred to the a-d register i. a at the same time as step , the a-d conversion interrupt request bit is set to 1. ? the a-d conversion start bit is cleared to 0 and the a-d converter stops operation. (2) when an external trigger is selected _____ the a-d converter starts operation when the input level to the ad trg pin changes from h to l while the a-d conversion start bit is 1. the a-d conversion is completed after 57 cycles of f ad . then, the contents of the successive approximation register (conversion result) are transferred to the a-d register i. a at the same time as step , the a-d conversion interrupt request bit is set to 1. ? the a-d conversion stops. the a-d conversion start bit remains set to 1 after the operation is completed. accordingly, the _____ operation of the a-d converter can be performed again from step when the level of the ad trg pin changes from h to l. _____ when the level of the ad trg pin changes from h to l during operation, the operation at that point is cancelled and is restarted from step . figure 12.5.2 shows the conversion operation in the one-shot mode. fig. 12.5.2 conversion operation in one-shot mode trigger occur convert input voltage from an i pin conversion result a-d register i a-d conversion interrupt request occurs. a-d converter halt
7721 group users manual 12C17 a-d converter 12.6 repeat mode 12.6 repeat mode in the repeat mode, the operation for the input voltage from the one selected analog input pin is performed repeatedly. in this mode, no a-d conversion interrupt request occurs. additionally, the a-d conversion start bit (bit 6 at address 1e 16 ) remains set to 1 until it is cleared to 0 by software, and the operation is performed repeatedly while the a-d conversion start bit is 1. 12.6.1 settings for repeat mode figure 12.6.1 shows an initial setting example for registers relevant to the repeat mode.
7721 group users manual 12C18 a-d converter 12.6 repeat mode fig. 12.6.1 initial setting example for registers relevant to repeat mode b7 b0 port p7 direction register (address 11 16 ) l port p7 direction register set the bits corresponding to analog input pins to 0. set bit 7 to 0 when selecting external trigger. l set a-d conversion start bit to 1 b7 b0 a-d control register (address 1e 16 ) 1 a-d conversion start bit when external trigger is selected when internal trigger is selected trigger occur operation start note : writing to each bit (except bit 6) of the a-d control register must be performed while the a-d converter halts (before a trigger occurs). input falling edge to ad trg pin an 0 an 1 an 2 an 3 an 4 an 5 an 6 an 7 b7 b0 a-d control register (address 1e 16 ) 01 0 0 0 0 : an 0 selected 0 0 1 : an 1 selected 0 1 0 : an 2 selected 0 1 1 : an 3 selected 1 0 0 : an 4 selected 1 0 1 : an 5 selected 1 1 0 : an 6 selected 1 1 1 : an 7 selected b2 a-d conversion start bit 0: stop a-d conversion analog input select bits a-d conversion frequency ( ad ) select bit l a-d control register repeat mode trigger select bit 0 : internal trigger 1 : external triggeer 0 : f 2 divided by 4 1 : f 2 divided by 2 b1 b0
7721 group users manual 12C19 a-d converter 12.6 repeat mode 12.6.2 repeat mode operation description (1) when an internal trigger is selected the a-d converter starts operation when the a-d conversion start bit is set to 1. the first a-d conversion is completed after 57 cycles of f ad . then, the contents of the successive approximation register (conversion result) are transferred to the a-d register i. a the a-d converter repeats operation until the a-d conversion start bit is cleared to 0 by software. the conversion result is transferred to the a-d register i each time the conversion is completed. (2) when an external trigger is selected ____ the a-d converter starts operation when the input level to the ad trg pin changes from h to l while the a-d conversion start bit is 1. the first a-d conversion is completed after 57 cycles of f ad . then, the contents of the successive approximation register (conversion result) are transferred to the a-d register i. a the a-d converter repeats operation until the a-d conversion start bit is cleared to 0 by software. the conversion result is transferred to the a-d register i each time the conversion is completed. _____ when the level of the ad trg pin changes from h to l during operation, the operation at that point is cancelled and is restarted from step . figure 12.6.2 shows the conversion operation in the repeat mode. trigger occur convert input voltage from an i pin conversion result a-d register i fig. 12.6.2 conversion operation in repeat mode
7721 group users manual 12C20 a-d converter 12.7 single sweep mode in the single sweep mode, the operation for the input voltage from multiple selected analog input pins is performed, one at a time. the a-d converter is operated in ascending sequence from the an 0 pin. the a-d conversion interrupt request occurs when the operation for all selected input pins are completed. 12.7.1 settings for single sweep mode figure 12.7.1 shows an initial setting example for registers relevant to the single sweep mode. when using an interrupt, it is necessary to set the relevant registers to enable the interrupt. refer to chapter 7. interrupts for more information. 12.7 single sweep mode
7721 group users manual 12C21 a-d converter 12.7 single sweep mode fig. 12.7.1 initial setting example for registers relevant to single sweep mode b7 b0 port p7 direction register (address 11 16 ) l port p7 direction register set the bits corresponding to analog input pins to 0. set bit 7 to 0 when selecting external trigger. l set a-d conversion start bit to 1 b7 b0 a-d control register (address 1e 16 ) 1 a-d conversion start bit l interrupt priority level b7 b0 a-d conversion interrupt control register (address 70 16 ) interrupt priority level select bits set to a level between 1 to 7 when using this interrupt. set to a level 0 when disabling this interrupt. when external trigger is selected when internal trigger is selected trigger occur operation start note : writing to each bit (except bit 6) of the a-d control register and each bit of the a-d sweep pin select register must be performed while the a-d converter halts (before a trigger occurs). input falling edge to ad trg pin an 0 an 1 an 2 an 3 an 4 an 5 an 6 an 7 a-d control register (address 1e 16 ) 0 0 : an 0 , an 1 (2 pins) 0 1 : an 0 Can 3 (4 pins) 1 0 : an 0 Can 5 (6 pins) 1 1 : an 0 Can 7 (8 pins) b1 b0 trigger select bit 0 : internal trigger 1 : external trigger a-d conversion start bit 0: stop a-d conversion a-d conversion frequency ( ad ) select bit 0 : f 2 divided by 4 1 : f 2 divided by 2 b7 b0 l a-d control register and a-d sweep pin select register a-d sweep pin select register (address 1f 16 ) b7 b0 10 0 55 5 a-d sweep pin select bits 5 : 0 or 1 single sweep mode
7721 group users manual 12C22 a-d converter 12.7.2 single sweep mode operation description (1) when an internal trigger is selected the operation for the input voltage from the an 0 pin starts when the a-d conversion start bit is set to 1. the a-d conversion of the input voltage from the an 0 pin is completed after 57 cycles of f ad . then, the contents of the successive approximation register (conversion result) are transferred to the a-d register 0. a for all of the selected analog input pins, the a-d conversion is performed. the conversion result is transferred to the a-d register i each time each pin is converted. ? when step a is completed, the a-d conversion interrupt request bit is set to 1. ? the a-d conversion start bit is cleared to 0 and the a-d converter stops operation. (2) when an external trigger is selected the a-d converter starts operation for the input voltage from the an 0 pin when the input level to _____ the ad trg pin changes from h to l while the a-d conversion start bit is 1. the a-d conversion of the input voltage from the an 0 pin is completed after 57 cycles of f ad . then, the contents of the successive approximation register (conversion result) are transferred to the a-d register 0. a for all of the selected analog input pins, the a-d conversion is performed. the conversion result is transferred to the a-d register i each time each pin is converted. ? when step a is completed, the a-d conversion interrupt request bit is set to 1. ? the a-d conversion stops. the a-d conversion start bit remains set to 1 after the operation is completed. accordingly, the _____ operation of the a-d converter can be performed again from step when the level of the ad trg pin changes from h to l. _____ when the level of the ad trg pin changes from h to l during operation, the operation at that point is cancelled and is restarted from step . figure 12.7.2 shows the conversion operation in the single sweep mode. 12.7 single sweep mode
7721 group users manual 12C23 a-d converter 12.7 single sweep mode trigger occur convert input voltage from an 0 pin conversion result a-d register 0 a-d register i a-d register 1 conversion result conversion result a-d converter halt a-d conver ter interrupt request occur convert input voltage from an 1 pin convert input voltage from an i pin fig. 12.7.2 conversion operation in single sweep mode
7721 group users manual 12C24 a-d converter 12.8 repeat sweep mode in the repeat sweep mode, the operation for the input voltages from the multiple selected analog input pins is performed repeatedly. the a-d converter is operated in ascending sequence from the an 0 pin. in this mode, no a-d conversion interrupt request occurs. additionally, the a-d conversion start bit (bit 6 at address 1e 16 ) remains set to 1 until it is cleared to 0 by software, and the operation is performed repeatedly while the a-d conversion start bit is 1. 12.8.1 settings for repeat sweep mode figure 12.8.1 shows an initial setting example for registers relevant to the repeat sweep mode. 12.8 repeat sweep mode
7721 group users manual 12C25 a-d converter 12.8 repeat sweep mode fig. 12.8.1 initial setting example for registers relevant to repeat sweep mode b7 b0 port p7 direction register (address 11 16 ) l port p7 direction register set the bits corresponding to analog input pins to 0. set bit 7 to 0 when selecting external trigger. l set a-d conversion start bit to 1 b7 b0 a-d control register (address 1e 16 ) 1 a-d conversion start bit when external trigger is selected when internal trigger is selected trigger occur operation start note : writing to each bit (except bit 6) of the a-d control register and each bit of the a-d sweep pin select register must be performed while the a-d converter halts (before a trigger occurs). input falling edge to ad trg pin an 0 an 1 an 2 an 3 an 4 an 5 an 6 an 7 a-d control register (address 1e 16 ) 0 0 : an 0 , an 1 (2 pins) 0 1 : an 0 Can 3 (4 pins) 1 0 : an 0 Can 5 (6 pins) 1 1 : an 0 Can 7 (8 pins) b1 b0 trigger select bit 0 : internal trigger 1 : external trigger a-d conversion start bit 0: stop a-d conversion a-d conversion frequency ( ad ) select bit 0 : f 2 divided by 4 1 : f 2 divided by 2 b7 b0 l a-d control register and a-d sweep pin select register a-d sweep pin select register (address 1f 16 ) b7 b0 11 0 55 5 a-d sweep pin select bits 5 : 0 or 1 repeat sweep mode
7721 group users manual 12C26 a-d converter 12.8.2 repeat sweep mode operation description (1) when an internal trigger is selected the operation for the input voltage from the an 0 pin starts when the a-d conversion start bit is set to 1. the a-d conversion of the input voltage from the an 0 pin is completed after 57 cycles of f ad . then, the contents of the successive approximation register (conversion result) are transferred to the a-d register 0. a for all of the selected analog input pins, the a-d conversion is performed. the conversion result is transferred to the a-d register i each time each pin is converted. ? for all of the selected analog input pins, the a-d conversion is performed again. ? the operation is performed repeatedly until the a-d conversion start bit is cleared to 0 by software. (2) when an external trigger is selected the a-d converter starts operation for the input voltage from the an 0 pin when the input level to ______ the ad trg pin changes from h to l while the a-d conversion start bit is 1. the a-d conversion of the input voltage from the an 0 pin is completed after 57 cycles of f ad . then, the contents of the successive approximation register (conversion result) are transferred to the a-d register 0. a for all of the selected analog input pins, the a-d conversion is performed. the conversion result is transferred to the a-d register i each time each pin is converted. ? for all of the selected analog input pins, the a-d conversion is performed again. ? the operation is performed repeatedly until the a-d conversion start bit is cleared to 0 by software. ______ when the level of the ad trg pin changes from h to l during operation, the operation at that point is cancelled and is restarted from step . figure 12.8.2 shows the conversion operation in the repeat sweep mode. 12.8 repeat sweep mode
7721 group users manual 12C27 a-d converter 12.8 repeat sweep mode trigger occur convert input voltage from an 0 pin conversion result a-d register 0 a-d register i a-d register 1 conversion result conversion result convert input voltage from an 1 pin convert input voltage from an i pin fig. 12.8.2 conversion operation in repeat sweep mode
7721 group users manual 12C28 a-d converter 12.9 precautions for a-d converter 12.9 precautions for a-d converter 1. writing to the following must be performed before a trigger occurs (while the a-d converter halts). ?each bit (except bit 6) of the a-d control register ?each bit of the a-d sweep pin select register _____ 2. when an external trigger is selected, the an 7 /ad trg pin is disconnected from the comparator. therefore, this pin cannot be used as an analog input pin. when the an 7 pin is selected as an analog input pin while an external trigger is selected, the a-d converter operates, however, an undefined value is stored into the a-d register 7. 3. refer to appendix. 8 countermeasure against noise when using the a-d converter.
chapter 13 dma controller 13.1 overview 13.2 block description [precautions for dmac] 13.3 control 13.4 operation [precautions for 2-bus cycle transfer] [precautions for 1-bus cycle transfer] [precautions for burst transfer mode] [precautions for cycle-steal transfer mode] 13.5 single transfer mode 13.6 repeat transfer mode 13.7 array chain transfer mode [precautions for array chain transfer mode] 13.8 link array chain transfer mode [precautions for link array chain transfer mode] 13.9 dma transfer time
7721 group users manual 13-2 dma controller 13.1 overview the dma controller (hereafter called dmac) transfers data using the bus and bypassing the cpu. dmac of the m37721 provides four independent channels of dma0Cdma3, which have the same function each. in this chapter, the source and destination of each dma transfer are represented as follows. l memory a device which needs its own address to be specified examples: internal ram and sfrs, external memory, and memory-mapped i/os l i/o a device which does not need its own address to be specified example: external i/o devices 13.1.1 performance overview table 13.1.1 lists the performance overview. table 13.1.1 dmac performance overview item performance specifications number of channels transfer space number of transfer bytes dma request source channel priority transfer rate data transfer method transfer unit address direction of transfer transfer mode continuous transfer mode 4 channels 16 mbytes (between arbitrary spaces) maximum of 16 mbytes internal 14 sources and external 1 source fixed or rotating maximum of 12.5 mbytes/sec (at f(x in ) = 25 mhz, 1-bus cycle transfer) maximum of 6.25 mbytes/sec (at f(x in ) = 25 mhz, 2-bus cycle transfer) 1-bus cycle or 2-bus cycle transfer 8 or 16 bits fixed, forward, or backward (directions of source and destination are independently selectable.) burst transfer or cycle-steal transfer mode single transfer, repeat transfer, array chain transfer, or link array chain transfer mode 13.1 overview
7721 group users manual 13-3 dma controller 13.1.2 bus use priority levels the bus use priority levels are fixed by hardware as follows: dramc > hold function > dmac > cpu (dram refresh) because dmac has the third priority, it actually operates as follows: ? when dram refresh request or hold request is generated during dma transfer after the transfer of one transfer unit (8-bit or 16-bit data), which is being performed at that time, is complete, dmac relinquishes the bus to a dram refresh or a hold function. when dmac regains the right to use bus after the dram refresh ends or the hold state is removed, dma transfer is restarted at the following address. ? when dma request is generated during dram refresh or in hold state dmac gains the right to use bus after the dram refresh ends or the hold state is removed. ? when dma request is generated while cpu uses bus upon end of the bus cycle, dmac gains the right to use bus if any dram refresh request or hold request is not generated at that time. if a dram refresh request or a hold request is generated when the bus cycle ends, dmac gains the right to use bus after the dram refresh ends or the hold state is removed. for details, refer to section 13.2.1 bus access control circuit and bus request sampling signals in timing diagrams. 13.1.3 modes dmac has the following transfer methods and modes. because these methods and modes are independent each other, any combination between them is selectable. (1) data transfer method n 2-bus cycle transfer this is a method used to transfer data between memories. a dma transfer consumes 2 cycles: a read and a write cycle of data. for details, refer to section 13.4.1 2-bus cycle transfer. n 1-bus cycle transfer this is a method used to transfer data between a memory and an i/o. a read and write of data is carried out at the same time (in 1-bus cycle), so that high-speed transfer can be accomplished. for details, refer to section 13.4.2 1-bus cycle transfer. (2) transfer unit n 8-bit transfer a minimum unit of dma transfer is 8 bits; that is, an 8-bit data is transferred for one dma request in the cycle-steal transfer mode. in the burst transfer mode, if a dram refresh request or a hold request is generated during dma ___ transfer, or if tc input is driven from h to l to force dma transfer into termination, dmac relinquishes the bus after completion of 8-bit data transfer which is being performed at that time. n 16-bit transfer a minimum unit of dma transfer is 16 bits; that is, a 16-bit data is transferred for one dma request in the cycle-steal transfer mode. in the burst transfer mode, if a dram refresh request or a hold request is generated during dma ___ transfer, or if tc input is driven from h to l to force dma transfer into termination, dmac relinquishes the bus after completion of 16-bit data transfer which is being performed at that time. 13.1 overview
7721 group users manual 13-4 dma controller (3) transfer modes n burst transfer mode when once a dma request is accepted in this mode, an entire batch of data is transferred. neither is the right to use bus returned to the cpu, nor the dma request of the channel with the higher ________ priority is accepted until the transfer is complete. however, if an external source ( dmareqi ) is selected as a dma request source with the level sense selected, dma transfer is performed when _________ the dmareqi pins input level is l, and the right to use bus is returned to the cpu when the _________ dmareqi pins input level is h. even in this case, any dma request of the other channels is not accepted until the entire batch of data has been transferred. for details, refer to section 13.4.3 burst transfer mode. n cycle-steal transfer mode for each dma request, 1 transfer unit of data is transferred. (hereafter, transferring 1-transfer-unit data, which is 8-bit or 16-bit data in the m37721, is called 1-unit transfer.) when 1-unit transfer is complete and another dma request (including that of other channels) is not generated, the dmac relinquishes the right to use bus to the cpu. in the cycle-steal transfer mode, all of the dma request sources are available. for details, refer to section 13.4.4 cycle-steal transfer mode. figure 13.1.1 shows the outline of the dma transfer modes. n burst transfer mode (external source (dmareqi), level sense) n burst transfer mode (edge sense) right to use bus (transfer of entire batch of data) cpu dmai cpu dmai dmareqi input cpu dmai cpu cpu cpu dma1 dma0 dma0 cpu right to use bus right to use bus n cycle-steal transfer mode dma0 request is accepted. dma0 request is accepted. dma1 request is accepted. dmai request is accepted. (one transfer unit) (one transfer unit) (one transfer unit) 13.1 overview fig. 13.1.1 outline of dma transfer modes
7721 group users manual 13-5 dma controller (4) continuous transfer mode n single transfer mode 1 block of data is transferred once. for details, refer to section 13.5 single transfer mode. n repeat transfer mode 1 block of data is transferred repeatedly. for details, refer to section 13.6 repeat transfer mode. n array chain transfer mode several blocks of data are transferred. the transfer parameters (transfer source and destination addresses, the number of transfer bytes) of each block must be located on the memory in series. for details, refer to section 13.7 array chain transfer mode. n link array chain transfer mode several blocks of data are transferred. transfer parameters for each block can be located on the memory in separate, in a unit of 1- blocks parameters. for details, refer to section 13.8 link array chain transfer mode. 13.1 overview
7721 group users manual 13-6 dma controller 13.2 block description figures 13.2.1 and 13.2.2 show the dmac block diagrams, and relevant registers are described below. incrementer/decrementer source address register 0 (sar0) destination address register 0 (dar0) dma latch high-order address bus decrementer transfer counter register 0 (tcr0) : microcomputer? internal bus data bus (odd) data bus (even) transfer counter register 1 (tcr1) transfer counter register 2 (tcr2) transfer counter register 3 (tcr3) source address register 1 (sar1) destination address register 1 (dar1) source address register 2 (sar2) destination address register 2 (dar2) source address register 3 (sar3) destination address register 3 (dar3) dma latch low-order : dmac? internal bus fig. 13.2.1 dmac block diagram (1) request source selection request enable channel 0 dmareq0 software timer a0 timer a1 refresh timer dram refresh request dramc hold request hold function channel priority level determination array state dmac acknowledge signal generation dmaack0 dmaack1 dmaack2 dmaack3 bus access control circuit cpu wait request bus request (dmac) st0 st1 biu bus request (dramc) hold f 16 channel 1 channel 2 channel 3 bus request (hold) fig. 13.2.2 dmac block diagram (2) 13.2 block description
7721 group users manual 13-7 dma controller 13.2 block description 13.2.1 bus access control circuit in the m37721, the bus is used by dramc, hold function, dmac, and cpu. when each request of dram refresh, hold, and dma is generated, each of dramc, hold function, and dmac issues its bus request to the bus access control circuit in dmac. (refer to figure 13.2.2. ) table 13.2.1 lists the bus request generating sources. table 13.2.1 bus request generating sources bus request bus request (dramc) bus request (hold) bus request (dmac) bus request generating source dram refresh request (generated by an underflow of the refresh timer.) hold request _____ (generated by l-level input to the hold pin.) dma request (generated by a dma request source.) the bus access control circuit relinquishes the right to use bus to the function with the highest priority among functions, which issue bus requests when the bus request signal is sampled. this is the bus request acceptance. if any bus request is not generated at bus request sampling, the cpu gains the right to use bus. the bus use priority levels are fixed by hardware, and the bus status is reported by status signal outputs st0 and st1. table 13.2.2 lists the relationship between the bus use priority level, bus status, and status signals. table 13.2.2 relationship between bus use priority level, bus status, and status signals bus use priority level 1 (highest) 2 3 4 (lowest) bus status dram refresh hold dmac cpu (including the term while the cpu does not use the bus; for example, the term when the cpu is calculating and does not use the bus) 0 0 1 1 0 1 0 1 status signals st1 st0
7721 group users manual 13-8 dma controller bus request sampling timing after completion of a dram refresh cycle every 1 cycle of f all except the following at the end of each block all except the following at the end of each block (except the last block) at the end of the last block at an array state when an instruction is fetched into queue buffer at a read from or a write into memory while cpu does not use bus the bus request signal is sampled at a break in bus use. table 13.2.3 and figure 13.2.3 shows the timings of bus request sampling. also, bus request sampling signals are shown in them. table 13.2.3 bus request sampling timing 13.2 block description after completion of 1-unit transfer after 1-unit transfer and terminate-processing (3 cycles of f ) etc. are performed sequentially after completion of 1-unit transfer n during transfer in burst transfer mode after the last 1-unit transfer of 1 block, the subsequent 3 cycles of f , and a read of the first 2 bytes in the array state of the next block are performed sequentially n during transfer in cycle-steal transfer mode after the last 1-unit transfer of 1 block and the subsequent 3 cycles of f are performed sequentially after 1-unit transfer and terminate-processing (3 cycles of f ) are performed sequentially after a read of 2 bytes of a transfer parameter after completion of 1 bus cycle after completion of 1 bus cycle, or after completion of the second bus cycle if a 16-bit data is accessed in a unit of 8 bits (note 2) . every 1 cycle of f bus user dram refresh hold dmac cpu s/r (note 1) array/ link (note 1) notes 1 : s = single transfer mode, r = repeat transfer mode, array = array chain transfer mode, link = link array chain transfer mode 2: this applies when the data bus width is 8 bits or when memory is accessed starting at an odd address. if a dram refresh request or a hold request is generated during a data transfer in the burst transfer mode, the request is accepted at the above-mentioned bus request sampling. another dma request (including that of other channels) cannot be accepted until the dma transfer which is in progress normally terminates or is forced into termination. if a dram refresh request, a hold request or another dma request (including that of other channels) is generated during a data transfer in the cycle-steal transfer mode, the bus request with the highest priority is accepted at the above-mentioned bus request sampling. (if only several dma requests are generated, the request of the channel whose priority is highest is accepted.) if any bus request is not generated at the above-mentioned bus sampling, the right to use bus is relinquished to the cpu. note that no dma request is accepted in array states.
7721 group users manual 13-9 dma controller fig. 13.2.3 timing of bus request sampling 13.2 block description the above applies on the following conditions: ?cycle-steal transfer mode ?dma request source = external request (dmareqi) ?1-bus cycle transfer ?no wait e hold bus request (hold) bus request sampling st1, st0 when access is complete in 1 bus cycle when 16-bit data is accessed in a unit of 8 bits transition of right to use bus (1, 1) (0, 0) (1, 1) refresh e refresh request bus request(dramc) bus request sampling st1, st0 (0, 0) bus used by cpu n dram refresh this is the term in which the bus is not used so that samp i ng is performed every 1 cycle of . sampling is performed after completion of sampling is performed after completion of a refresh cycle. 1 bus cycle. h hold state h dma transfer h n hold n dma transfer refresh (1, 1) hold state e dmareqi dmai request bit bus request (dmac) bus request sampling st1, st0 (1, 1) (0, 1) (1, 1) (1, 1) (1, 1) (0, 1) (1, 1) (1, 0) (1, 1) (1, 1) (1, 1) (1, 0) dma transfer this is the term in which the bus is not used so that sampling is performed every 1 cycle of . this is at holol state so that sampling is performed every 1 cycle of . sampling is performed after completion of 1 bus cycle. this is the term in which the bus is not used so that sampling is performed every 1 cycle of sampling is performed after completion of sampling is performed after complet on of 1- unit transfer. 1 bus cycle. n cpu e bus request sampling st1, st0 (1, 1) bus used by cpu by cpu bus used by cpu transition of right to use bus transition of right to use bus transition of right to use bus transition of right to use bus transition of right to use bus transition of right to use bus transition of right to use bus transition of right to use bus transition of right to use bus transition of right to use bus transition of right to use bus . this is the term in which the bus is not used so that sampling is performed every 1 cycle of sampling is performed after completion of 1 bus cycle. 16-bit data is accessed in a unit of 8 bits, so that sampling is performed after completion of the second bus cycle. bus used . i
7721 group users manual 13-10 dma controller fig. 13.2.4 structure of dmac control register l 13.2 block description 13.2.2 dmac control register l figure 13.2.4 shows the structure of dmac control register l. bit 0 is described in section 13.3.3 channel priority levels, and bits 4C7 are also in section 13.3.2 dma requests. (1) ___ tc pin validity bit (bit 1) ___ ___ when this bit is set to 1, port p10 3 functions as the tc pin. the tc pin is of an n-channel open- drain type and provides the following functions: l terminal count signal output when the transfer of an entire batch of data is normally terminated, the pin outputs l for 1 cycle of f . (refer to section 13.3.5 (1) normal termination. ) l forced termination signal input ___ when the tc pins input level goes from h to l during dma transfer, this dma transfer is forced into termination. (refer to section 13.3.5 (2) forced termination. ) notes 1: the state of bits 4 to 7 is not changed when writing 1 to these bits. 2: ? when writing to this register while any of dmai enable bits (bits 4 to 7 at address 69 16 ) is 1, use the ldm or sta instruction in m flag = 1. when dmai request bit (bits 4 to 7 at address 68 16 ) must not be changed, set dmai request bit to 1. ? when writing to this register while all of dmai enable bits (bits 4 to 7 at address 69 16 ) are 0, m flag may be 0 or 1. use the ldm or sta instruction for writing to this register. when dmai request bit (bits 4 to 7 at address 68 16 ) must not be changed, set dmai request bit to 1. 0 : fixed 1 : rotating bit bit name functions at reset rw 0 1 priority select bit undefined 0 0 : no request 1 : requested (note 1) 0 dmac control register l (address 68 16 ) b1 b0 b2 b3 b4 b5 b6 b7 rw rw 3, 2 0 rw 0 rw tc pin validity bit 0 : invalid (p10 3 pin functions as a programmable i/o port (cmos).) 1 : valid (p10 3 pin functions as tc pin (n- channel open-drain).) nothing is assigned. C 4 5 6 7 dma0 request bit dma1 request bit dma2 request bit dma3 request bit 0rw 0 rw
7721 group users manual 13-11 dma controller 13.2.3 dmac control register h figure 13.2.5 shows the structure of dmac control register h. each of bits 0C3 is a software dmai (i = 0 to 3) request bit, which corresponds to each channel. when a software dma source is selected as a dma request source, each of these bits is valid. (refer to 13.3.2 dma requests.) bits 4C7 are described in section 13.3.1 dma enabling. fig. 13.2.5 structure of dmac control register h 13.2 block description 1 : dma request (valid when software dma source is selected.) the value is ??at reading. bit bit name functions at reset rw 0 1 software dma0 request bit 0 0 : disabled 1 : enabled 0 dmac control register h (address 69 16 ) b1 b0 b2 b3 b4 b5 b6 b7 wo rw 0wo 0 rw 4 5 6 7 dma0 enable bit 0rw 0 rw 0 0 wo wo software dma1 request bit software dma2 request bit software dma3 request bit 2 3 dma0 enable bit dma1 enable bit dma2 enable bit dma3 enable bit note: when any of bits 4 to 7 is set to ?,?use the clb or seb instruction for writing to this register.
7721 group users manual 13-12 dma controller 13.2 block description 13.2.4 source address register i (sari) source address register i (hereafter called sari) is a 24-bit register with a latch. sari indicates the transfer source address of the data to be transferred next. the sari latch has the following functions: ? maintains the value written to the address of sari (in the single transfer and repeat transfer modes). ? indicates the start address of the transfer parameter memory of the next block (in the array chain transfer and link array chain transfer modes). when a value is written into the address of sari, the same value is written into sari and the sari latch. when writing a value to the address of sari, all 24 bits must be written. the contents of sari can be read by reading the address of sari; however, the value of the sari latch cannot be read. (refer to tables 13.2.4 and 13.2.5. ) 13.2.5 destination address register i (dari) destination address register i (hereafter called dari) is a 24-bit register with a latch. dari indicates the transfer destination address of the data to be transferred next. the dari latch maintains the value written to the address of dari. when a value is written into the address of dari, the same value is written into dari and the dari latch. when writing a value to the address of dari, all 24 bits must be written. the contents of dari can be read by reading the address of dari; however, the value of the dari latch cannot be read. (refer to tables 13.2.4 and 13.2.5. ) 13.2.6 transfer counter register i (tcri) transfer counter register i (hereafter called tcri) is a 24-bit register with a latch. tcri indicates the number of remaining bytes of the block under transfer. the tcri latch has the following functions: ? maintains the value written to the address of tcri (in the single transfer and repeat transfer modes). ? indicates the number of remaining blocks (in the array chain transfer mode). when a value is written into the address of tcri, the same value is written into tcri and the tcri latch. when writing a value to the address of tcri, all 24 bits must be written. the contents of tcri can be read by reading the address of tcri; however, the value of the tcri latch cannot be read. (refer to tables 13.2.4 and 13.2.5. ) table 13.2.4 addresses of sari, dari, and tcri channel 0 1 2 3 source address register i (sari) 1fc2 16 C1fc0 16 1fd2 16 C1fd0 16 1fe2 16 C1fe0 16 1ff2 16 C1ff0 16 destination address register i (dari) 1fc6 16 C1fc4 16 1fd6 16 C1fd4 16 1fe6 16 C1fe4 16 1ff6 16 C1ff4 16 1fca 16 C1fc8 16 1fda 16 C1fd8 16 1fea 16 C1fe8 16 1ffa 16 C1ff8 16 transfer counter register i (tcri)
7721 group users manual 13-13 dma controller register mode maintains the transfer start address of the source. 13.2 block description single transfer mode repeat transfer mode array chain transfer mode sari dari indicates the transfer source address of the data to be transferred next. sari sari latch dari indicates the transfer destination address of the data next to be transferred dari latch indicates the start address of the transfer parameter memory of the next block. maintains the transfer start address of the destination. (not used) tcri indicates the number of remaining bytes of the block under transfer. tcri tcri latch table 13.2.5 functions of sari, dari, and tcri maintains the byte number of the transfer data. indicates the number of remaining blocks. (not used) link array chain transfer mode (not used) (note) note: any value other than 0 (000001 16 Cffffff 16 ) must be written before dam transfer. 13.2.7 incrementer/decrementer the incrementer/decrementer is a 24-bit register. after every 1-unit transfer, that increments (adds) or decrements (subtract) the contents of sari and dari. table 13.2.6 lists the increment/decrement values. table 13.2.6 increment/decrement values transfer unit 8 bits 16 bits address directions forward backward + 1 C 1 + 2 C 2 13.2.8 decrementer the decrementer is a 24-bit register. after every 1-unit transfer, that decrements the contents of tcri by 1 when the transfer unit is 8 bits, and by 2 when 16 bits. in the array chain transfer mode, every time a transfer parameter is read, the contents of the tcri latch are also decremented by 1. 13.2.9 dma latch the dma latch is a 16-bit latch. in 2-bus cycle transfer mode, the dma latch maintains the value read from the transfer source memory with a read cycle until this value is written into the transfer destination memory. in 1-bus cycle transfer mode, the dma latch is used to copy data. for copy, refer to section 13.4.2 1-bus cycle transfer.
7721 group users manual 13-14 dma controller 13.2 block description 13.2.10 dmai mode register l figure 13.2.6 shows the structure of dmai mode register l. for bit 0, refer to section 13.1.3 (2) transfer unit. for bit 1, refer to section 13.4.1 2-bus cycle transfer and section 13.4.2 1-bus cycle transfer ; for bit 2, refer to section 13.4.3 burst transfer mode and section 13.4.4 cycle-steal transfer mode. (1) transfer source address direction select bits (bits 4 and 5) and transfer destination address direction select bits (bits 6 and 7) address direction means an order of accessing memory in dma transfer and is defined as follows: ? fixed direction: an address does not move. ? forward direction: an address moves upward from the specified start address. ? backward direction: an address moves downward from the specified start address. for details, refer to section 13.4.1 (3) address directions in 2-bus cycle transfer and section 13.4.2 (3) address directions in 1-bus cycle transfer. fig. 13.2.6 structure of dmai mode register l bit bit name at reset 5 0 rw functions b7 b6 b5 b4 b3 b2 b1 b0 dma0 mode register l (address 1fcc 16 ) dma1 mode register l (address 1fdc 16 ) dma2 mode register l (address 1fec 16 ) dma3 mode register l (address 1ffc 16 ) note: when the external data bus has a width of 8 bits and 1-bus cycle transfer is selected, set bit 0 to ?. 0 0 0 : 16 bits 1 : 8 bits 1 0 : 2-bus cycle transfer 1 : 1-bus cycle transfer 2 0 0 : burst transfer mode 1 : cycle-steal transfer mode 3 0 4 0 0 0 : fixed 0 1 : forward 1 0 : backward 1 1 : do not select. 6 0 7 rw rw 0 number-of-unit-transfer-bits select bit (note) transfer method select bit transfer mode select bit fix this bit to ?. transfer source address direction select bits transfer destination address direction select bits 0 0 : fixed 0 1 : forward 1 0 : backward 1 1 : do not select. b5b4 b7b6 rw rw rw rw 0 0 rw rw
7721 group users manual 13-15 dma controller 13.2 block description 13.2.11 dmai mode register h figure 13.2.7 shows the structure of dmai mode register h. bits 0 and 1 are used in 1-bus cycle transfer. for details, refer to section 13.4.2 1-bus cycle transfer. bits 6 and 7 are the bits for selecting the continuous transfer mode. for details, refer to section 13.5 single transfer mode through section 13.8 link array chain transfer mode. (1) transfer source wait bit and transfer destination wait bit (bits 4 and 5) when each of these bits is set to 1, 1-bus cycle in a dma transfer consumes 3 cycles of f , and when cleared to 0, 2 cycles of f . these bits are valid for the internal and external areas. in the dram area, however, 1-bus cycle consumes 3 cycles of f regardless of the states of these bits. (refer to chapter 14. dram controller. ) the wait bit (bit 2 at address 5e 16 ) is invalid in dma transfer. however, ready function is still valid in dma transfer. fig. 13.2.7 structure of dmai mode register h bit bit name at reset 5 0 rw functions b7 b6 b5 b4 b3 b2 b1 b0 dma0 mode register h (address 1fcd 16 ) dma1 mode register h (address 1fdd 16 ) dma2 mode register h (address 1fed 16 ) dma3 mode register h (address 1ffd 16 ) notes 1: set bit 0 to ??in 2-bus cycle transfer. 2: bits 4 and 5 are valid to the external and internal areas. however, dram area is always handled with ?ait?regardless of the contents of these bits. the wait bit (bit 2 at address 5e 16 ) is invalid in dma transfer. 0 0 0 : from memory to i/o 1 : from i/o to memory 1 refer to below. 2 0 3 0 4 0 6 0 7 rw rw 0 transfer direction select bit (used in 1-bus cycle transfer) (note 1) i/o connection select bit (valid in 1-bus cycle transfer) fix these bits to ?. transfer source wait bit (note 2) continuous transfer mode select bits 0 0 : single transfer 0 1 : repeat transfer 1 0 : array chain transfer 1 1 : link array chain transfer b7b6 rw rw rw rw 0 0 rw rw 0 transfer destination wait bit (note 2) 0 : wait 1 : no wait setting for i/o connection select bit transfer method 1-bus cycle transfer 2-bus cycle transfer external data bus width 8 bits 16 bits i/o connection d 0 ? 7 d 0 ? 15 (16-bit i/0 5 1 or 8-bit i/o 5 2) d 0 ? 7 (8-bit i/o) d 8 ? 15 (8-bit i/o) setting for i/o connection select bit it may be either ??or ?. 0 0 0 1
7721 group users manual 13-16 dma controller 13.2 block description 13.2.12 dmai control register figure 13.2.8 shows the structure of the dmai control register. for bits 0C4, refer to section 13.3.2 (1) dma request sources. (1) _________ dmaacki validity bit (bit 5) _________ when this bit is set to 1, the corresponding pin of port p9 serves as the dmaacki pin and outputs l during a dma transfer. for details, refer to each timing diagram of section 13.5 single transfer mode through section 13.8 link array chain transfer mode. bit bit name at reset 5 0 rw functions b7 b6 b5 b4 b3 b2 b1 b0 dma0 control register (address 1fce 16 ) dma1 control register (address 1fde 16 ) dma2 control register (address 1fee 16 ) dma3 control register (address 1ffe 16 ) note: when a certain source other than an external source is selected by bits 0 to 3 or when the cycle-steal transfer mode is selected, set bit 4 to ?.? level sense can be selected only when both of the external source and the burst transfer mode are selected. 0 0 0 0 0 0 : do not select. 0 0 0 1 : external source (dmareqi) 0 0 1 0 : software dma source 0 0 1 1 : timer a0 0 1 0 0 : timer a1 0 1 0 1 : timer a2 0 1 1 0 : timer a3 0 1 1 1 : timer a4 1 0 0 0 : timer b0 1 0 0 1 : timer b1 1 0 1 0 : timer b2 1 0 1 1 : uart0 receive 1 1 0 0 : uart0 transmit 1 1 0 1 : uart1 receive 1 1 1 0 : uart1 transmit 1 1 1 1 : a-d conversion 1 2 0 3 0 4 0 0 7, 6 rw rw dma request source select bits (note) edge sense/level sense select bit (used when external source and burst transfer mode are selected) (note) dmaacki validity bit 0 : invalid (the pin functions as a programmable i/o port.) 1 : valid (the pin functions as dmaacki.) rw rw rw rw undefined 0 : edge sense (falling edge) 1 : level sense (??level) nothing is assigned. b3b2b1b0 fig. 13.2.8 structure of dmai control register
7721 group users manual 13-17 dma controller 13.2 block description 13.2.13 dmai interrupt control register figure 13.2.9 shows the structure of the dmai interrupt control register. for details about interrupts, refer to chapter 7. interrupts. b7 b6 b5 b4 b3 b2 b1 b0 dmai interrupt control register (i = 0 to 3) (addresses 6c 16 to 6f 16 ) bit 7 to 4 interrupt request bit 2 1 0 bit name at reset 0 rw functions 0 0 0 : level 0 (interrupt disabled) 0 0 1 : level 1 0 1 0 : level 2 0 1 1 : level 3 1 0 0 : level 4 1 0 1 : level 5 1 1 0 : level 6 1 1 1 : level 7 b2 b1 b0 0 : no interrupt requested 1 : interrupt requested interrupt priority level select bits 3 rw rw rw rw undefined 0 0 0 nothing is assigned. low level high level fig. 13.2.9 structure of dmai interrupt control register (1) interrupt priority level select bits (bits 2 to 0) these bits select a dmai interrupts priority level. when using dmai interrupts, select one of the priority levels (1 to 7). when a dmai interrupt request occurs, its priority level is compared with the processor interrupt priority level (ipl). the requested interrupt is enabled only when its priority level is higher than the ipl. (however, this applies when the interrupt disable flag (i) = 0.) to disable dmai interrupts, set these bits to 000 2 (level 0). (2) interrupt request bit (bit 3) this bit is set to 1 when a dmai interrupt request occurs after the dma transfer is complete. this bit is automatically cleared to 0 when the dmai interrupt request is accepted. this bit can be set to 1 or cleared to 0 by software.
7721 group users manual 13-18 dma controller 13.2 block description 13.2.14 port p9 direction register _________ i/o pins of dmai are multiplexed with port p9. when using these pins as the dmareqi input pins, set the corresponding bits of the port p9 direction register to 0 to set these port pins for the input mode. when _________ _________ using these pins as the dmaacki output pins, these pins are forcibly set to the dmaacki output pins regardless of the direction registers contents. figure 13.2.10 shows the relationship between the port p9 direction register and dmais i/o pins. bit corresponding pin functions 0 1 2 3 4 5 6 7 dmaack0 pin 0 : input mode 1 : output mode when using pins p9 1 , p9 3 , p9 5 and p9 7 as dmareqi input pins,set the corresponding bits to ?. port p9 direction register (address 15 16 ) b1 b0 b2 b3 b4 b5 b6 b7 at reset rw 0 0 0 0 0 0 0 0 rw rw rw rw rw rw rw rw dmareq0 pin dmaack1 pin dmareq1 pin dmaack2 pin dmareq2 pin dmaack3 pin dmareq3 pin fig. 13.2.10 relationship between port p9 direction register and dmais i/o pins [precautions for dmac] do not access the registers relevant to dmac by using dma transfers; the address of the accessing register collides with that of the accessed one on the dmac internal bus.
7721 group users manual 13-19 dma controller 13.3 control 13.3 control the conditions for performing dma transfer of dmai (i = 0C3) are as follows: ? neither a dram refresh request nor a hold request is generated. ? a request of the channel with a higher priority than that of dmai is not generated; or the request is disabled though it has been generated. ? dmai is enabled (dmai enable bit = 1). ? a dmai request is generated (dmai request bit = 1). the control method for each channel is described below. 13.3.1 dma enabling each of dma channels 0C3 has a dmai enable bit (bits 4C7 at address 69 16 ). table 13.3.1 lists the conditions for changing each dmai enable bit. table 13.3.1 conditions for changing dmai enable bit dmai enable bit conditions for bit change is set to 1. is cleared to 0. a write of 1 to the dmai enable bit ? a write of 0 to the dmai enable bit ? transfer of an entire batch of data is complete (normal termination). ___ ? a change of tc input level from h to l during a dma transfer of dmai (note) ___ (forced termination, when tc pin is valid.) note: in the burst transfer mode (level sense), however, the term from the dma transfer start until the transfer completion of an entire batch of data is applied. (it is also valid while the cpu has the right to use bus.)
7721 group users manual 13-20 dma controller 13.3 control 13.3.2 dma requests (1) dma request sources dma request sources are specified by the dma request source select bits and the edge sense/level sense select bit. (refer to figure 13.2.8. ) table 13.3.2 lists the conditions for generating a dma request. table 13.3.2 conditions for generating dma request dma request sources condition for generating dma request level sense edge sense external source ________ dmareqi software dmai request timers a0Ca4, timers b0Cb2, uart0, uart1, a-d converter _________ l-level input to the dmareqi pin (only in the burst transfer mode) _________ change of the dmareqi input pins level from h to l a write of 1 to the software dmai request bit (each of bits 0C3 at address 69 16 ; refer to figure 13.2.5. ) when the interrupt request bit of each peripheral is set to 1 by the activity of peripherals (if 1 is written to any of these interrupt request bits by software, the dmai request bit does not change. also, whatever value within 0C7 an interrupt priority level takes, this does not affect dma requests.) (2) change of dmai request bit a read of the dmai request bits (each of bits 4C7 at address 68 16 ) indicates whether the corresponding channel (0C3) is generating its dma request or not. the dmai request bit changes synchronized with the falling edge of f 1 . table 13.3.3 lists the conditions for changing the dmai request bit. for the timing of changing the dmai request bit, refer to figures 13.3.2 and 13.3.3. table 13.3.3 conditions for changing dmai request bit dmai request bit mode is set to 1. (note) is cleared to 0. generation of dmai request (refer to table 13.3.2. ) generation of dmai request (l-level input to the _________ dmareqi pin) generation of dmai request (refer to table 13.3.2. ) ? normal termination ___ ? change of the tc pins input level from h to l during ___ dma transfer (when the tc pin is valid) ? h-level input to the _________ dmareqi pin ___ ? change of the tc pins input level from h to l (when ___ the tc pin is valid) ? a write of 0 to the dmai request bit ? a write of 0 to the dmai enable bit ? start of 1-unit transfer ___ ? change of the tc pins input level from h to l during ___ dma transfer (when the tc pin is valid) ? a write of 0 to the dmai request bit ? a write of 0 to the dmai enable bit cycle-steal transfer mode burst transfer mode edge sense level sense note: while the dmai enable bit is 0, the dmai request bit is not set to 1 even if a dma request is generated. when the dmai enable bit is cleared to 0, also the dmai request bit is cleared to 0. however, the dma request generated while the dmai enable bit = 0 is maintained; and when the dmai enable bit is set to 1, the dmai request bit is also set to 1, except for the burst transfer mode (level sense).
7721 group users manual 13-21 dma controller 13.3 control 13.3.3 channel priority levels when the dma enable bits of several channels are 1 and their dma request bits are set to 1, the request of the channel with the highest priority is accepted first. the fixed or rotating channel priority can be selected by the priority select bit (bit 0 at address 68 16 ). the priority levels themselves cannot be specified arbitrary. the channel priority levels are determined after the dma requests are determined. (1) fixed priority the fixed priority is selected when the priority select bit (bit 0 at address 68 16 ) = 0. in the fixed priority, the channel priority levels are as follows: channel 0 > channel 1 > channel 2 > channel 3. (2) rotating priority the rotating priority is selected when the priority select bit = 1. after reset, the priority levels are the same descending order as in the fixed priority: channel 0 > channel 1 > channel 2 > channel 3. then, after every normal termination of a dma transfer, the priority levels rotate in such a way that the lowest priority is given to the channel having been performed. when dma transfer is forced into termination, the channel priority levels does not rotate. figure 13.3.1 shows an example of determining the channel priority levels.
7721 group users manual 13-22 dma controller 13.3 control l priority level: fixed priority bus request sampling dma0 request bit dma1 request bit dma2 request bit dma3 request bit channel priority level : 0 > 1 > 2 > 3 dma transfer execution channel 12 0 13 (nothing) 021 1 03 aa aa aaaa aaaa aaa aaa aa aa aaa aaa aa aa aaaa aaaa aaaaa aaaaa aaaaaaa aaaaa 12 3 13 02 3 1 33 aa aa aaaa aaaa aaa aaa aa aa aaa aaa aa aa aaaa aaaa aaaaa aaaaa aaaaaaa aaaaa l priority level: rotating priority bus request sampling dma0 request bit dma1 request bit dma2 request bit dma3 request bit channel priority level dma transfer execution channel (nothing) 0 > 1 > 2 > 3 0 > 1 > 2 > 3 0 > 1 > 2 > 3 0 > 1 > 2 > 3 0 > 1 > 2 > 3 0 > 1 > 2 > 3 2 > 3 > 0 > 1 2 > 3 > 0 > 1 2 > 3 > 0 > 1 3 > 0 > 1 > 2 3 > 0 > 1 > 2 1 > 2 > 3 > 0 the above timing diagram applies on the following conditions: ?no dram refresh request, no hold request ?all of dmai enable bits are ?. fig. 13.3.1 example of determining channel priority levels
7721 group users manual 13-23 dma controller 13.3 control 13.3.4 processing from dma request until dma transfer execution dma requests are sampled at every falling edge of f 1 ; when requested, the dmai request bit is set to 1. then, the channel priority levels and bus use priority levels are determined, and bus request (dmac) goes 1 if any dram refresh request or hold request is not generated (note). bus request (dmac) signal is sampled while the bus request sampling signal is 1 and is accepted (dma request acceptance). figure 13.3.2 shows an example of timing from the determination of a dma request until the dma transfer execution. refer to section 13.9 dma transfer time for the time from dma request generation until the cpus regaining the right to use bus via dma transfer. note: in the following cases, bus request (dmac) does not go 1. however, the dmai request bit remains set to 1. accordingly, after completion of each state, the channel priority levels and bus use priority levels are determined, and bus request (dmac) goes 1 if any dram refresh request or hold request is not generated. l when a dma request is generated during a burst transfer or in an array state (however, if a dram refresh request or hold request is generated during this term, its bus request goes 1.) l when a dma request is not accepted with a dram refresh request or hold request generated
7721 group users manual 13-24 dma controller 13.3 control fig. 13.3.2 example of timing from determination of dma request until dma transfer execution the above timing diagram applies on the following conditions: ? single transfer mode, or repeat transfer mode ? 2-bus cycle transfer ? no wait ? dmaacki valid, tc valid ? external source (dmareqi) ? after dmai request occurs (l is input to the dmareqi pin.), the right to use bus is relinquished to dmac at the shortest time. f 1 ale e r/w address address/data dmai enable bit dmareqi dmai request bit bus request(dmac) bus request sampling dmaacki tc st1 st0 dmai interrupt request bit pc sar dar pc,pg sar dar data h 1 0 transition of right to use bus 1-unit transfer read cycle write cycle when dmai request is sampled at this point ] data when burst transfer mode (edge sense) selected when burst transfer mode (level sense) selected when cycle-steal transfer mode selected ] : channel priority level determination and bus use priority level determination (1.5 cycles of f )
7721 group users manual 13-25 dma controller 13.3 control 13.3.5 termination of dma transfer as the methods of terminating dma transfer, normal and forced termination are used. (1) normal termination all of the dmai transfers terminate and dmac stops. this method is used in the single transfer, array chain transfer, and link array chain transfer modes. in the repeat transfer mode, however, normal termination cannot be applied to terminating transfer; then, forced termination must be used. (refer to (2) forced termination of this section.) table 13.3.4 lists the states of dmac at normal termination. table 13.3.4 states of dmac at normal termination item state dmai interrupt request bit dmai request bit dmai enable bit ___ tc output channel priority levels 1 in the burst transfer mode (edge sense): 0 in the burst transfer mode (level sense): not changed in the cycle-steal transfer mode: not changed (note) 0 ___ outputs l (when the tc pin is valid) rotating (when the rotating priority is selected) note: in the cycle-steal transfer mode, the dmai request bit is cleared to 0 when a dma request is accepted. this bit is does not change at normal termination. at normal termination, the cpu regains the right to use bus after the terminate processing (3 cycles of f ) via the transition of the right to use bus (1 cycle of f ). figure 13.3.3 shows a timing example at normal termination.
7721 group users manual 13-26 dma controller 13.3 control the above timing diagram applies on the following conditions: ? dmaacki valid, tc valid ? external source (dmareqi) 1 ale e r/w address address/data dmai enable bit dmai request bit bus request (dmac) bus request sampling dmaacki tc st1 st0 dmai interrupt request bit transition of right to use bus sar 1 sar 1 l 0 0 when burst transfer mode (edge sense) selected when burst transfer mode (level sense) selected when cycle-steal transfer mode selected terminate processing fig. 13.3.3 timing example at normal termination
7721 group users manual 13-27 dma controller 13.3 control (2) forced termination the methods of terminating dmac other than normal termination are as follows: ___ ___ ? drives the tc pins input level from h to l during a dma transfer (when the tc pin is valid). ? writes 0 to the dmai enable bit. table 13.3.5 lists the states of dmac at forced termination. table 13.3.5 states of dmac at forced termination item state dmai interrupt request bit dmai request bit dmai enable bit ___ tc output channel priority levels not changed. 0 0 not changed. not changed. ___ ___ when the tc pin is used for forced termination, select tc pin valid (bit 1 at address 68 16 = 1). ___ forced termination by the tc input is valid in the following cases: ? during a dma transfer in the burst transfer mode (edge sense) ? during the term from the dma transfer start until the transfer completion of an entire batch of data in the burst transfer mode with the level sense selected. (it is also valid while the cpu has the right to use bus). ___ ? during a dma transfer in the cycle-steal transfer mode (forced termination by the tc input is invalid while the cpu has the right to use bus.) ___ the tc pins input is determined at the falling edge of f 1 , and dmac will relinquish the right to use bus to the cpu upon completion of the 1-unit transfer under execution at that time. _ at the forced termination by the dmai enable bit, 0 is written to this bit at the rising edge of e of a write cycle to the dmai enable bit. accordingly, dmai is disabled after this write.
7721 group users manual 13-28 dma controller 13.3 control 13.3.6 dma transfer restart after termination (1) restarting the same dma transfer as the previous one from the beginning at normal and forced termination, the latches of sari, dari, and tcri maintain their values written before the transfer start. (refer to figure 13.3.4-a. ) therefore, dma transfer must be restarted according to the following procedures: l in single or repeat transfer mode set the dmai enable bit to 1. it is not necessary to re-set the values of sari, dari, and tcri by software. (refer to figure 13.3.4-b. ) l in array chain or link array chain transfer mode re-set the values of sari and tcri. set the dmai enable bit to 1. (2) restarting transfer of data subsequent to one which has been transferred just before forced termination when reading values at the addresses of sari, dari, and tcri after forced termination, the values of these registers (counters) can be read. these read values are the transfer source address, the transfer destination address which were to be transferred subsequently, and the number of remaining bytes. when writing these read values to the addresses of sari, dari, and tcri respectively, the same values are also written to their latches. when setting the dmai enable bit to 1 under this condition, transfer of data subsequent to one which has been transferred just before forced termination is restarted. (refer to figure 13.3.4-c. ) l in single transfer mode the remaining data can be transferred by the following procedure: read the values at addresses of sari, dari and tcri. then, rewrite these values into these addresses. set the dmai enable bit to 1. l in repeat transfer, array chain transfer, and link array chain transfer modes the remaining data of the block that was interrupted by forced termination can be transferred by the following procedure: switch over the current mode to the single transfer mode. read the values at addresses of sari, dari and tcri. then, rewrite these values into these addresses. set the dmai enable bit to 1. (refer to figure 13.3.4-c. ) in order to transfer the next block, switch over the current mode to the previous mode after the above-mentioned transfer is normally terminated. then, re-set the values of sari, dari, and tcri. in the array chain or the link array chain transfer mode, information such as the next transfer parameters etc. cannot be read from each latch.
7721 group users manual 13-29 dma controller 13.3 control fig.13.3.4 states of sari, dari, tcri after forced termination previously written values latch register transfer source/destination address is specified. contents are updated by incrementer/decrementer and decrementer. a. state at forced termination b. when setting dmai enable bit to 1 without rewriting values at addresses of sari, dari, and tcri a value read from each latch is used by hardware only at the first 1-unit transfer. the contents updated by the incrementer/decrementer and the decrementer are loaded in each register. values are used by reading them from registers at the second and the following 1-unit transfers. latch register previously written values updated contents are written. c. when reading values at addresses of sari, dari, and tcri after forced termination and rewriting them latch register previously written values written by software read by software addresses which were to be transferred subsequently or the number of remaining bytes addresses which were to be transferred subsequently or the number of remaining bytes addresses which were to be transferred subsequently or the number of remaining bytes addresses which were to be transferred subsequently or the number of remaining bytes
7721 group users manual 13-30 dma controller 13.4 operation 13.4 operation operation of 1-unit transfer varies according to the data transfer method (2-bus cycle or 1-bus cycle transfer). in addition, how many units of transfer data are transferred for a dma request varies according to the transfer mode (burst transfer or cycle-steal transfer mode). these data transfer methods and modes are described below. 13.4.1 2-bus cycle transfer when the transfer method select bit (refer to figure 13.2.6. ) = 0, 2-bus cycle transfer is selected. 2- bus cycle transfer is the method used to transfer data between memories. since this method has a read and a write cycle, it consumes a minimum of 2 bus cycles for 1-unit transfer. figure 13.4.1 shows an example of connecting external memories in 2-bus cycle transfer. fig. 13.4.1 example of connecting external memories in 2-bus cycle transfer m37721 address bus e bhe ble r/w data bus d 8 Cd 15 data bus d 0 Cd 7 transfer source memory (even address) transfer source memory (odd address) transfer destination memory (even address) transfer destination memory (odd address) note. the external circuit such as an address latch is disregarded.
dma controller 7721 group users manual 13-31 13.4 operation incrementer/ decrementer (1) read cycle sari sari latch dari dari latch tcri tcri latch dma latch decrementer dmac memory (transfer source) transfer source address is specified by sari (note) . contents of tcri are updated by decrementer (note) ; when value read from tcri is 0, transfer of 1 data block is terminated. contents of sari are updated by incrementer/ decrementer. data is read from memory and maintained in dma latch. dmac ] when the transfer unit is 16 bits ? when an even address is accessed with 16-bit external data bus width, data can be read or written at 1-bus cycle. accordingly, the incrementer/decrementer and the decrementer increment or decrement by 2, and sequences through are performed once. ? when an odd address is accessed with 16-bit external data bus width or when 8 bits is used as external data bus width, data is read or written at 2-bus cycles, and sequences through or through are repeated twice. the incrementer/decrementer and the decrementer increment or decrement by 1 every time sequences through or through are performed once. note: in the single transfer mode and repeat transfer mode, only at the first transfer of the block, the values read from sari latch, dari latch, and tcri latch are used. (the results obtained by increment or decrement are written to sari, dari, and tcri. except for the first transfer of the block, the values read from sari, dari, and tcri are used.) (transfer destination) (2) write cycle memory sari sari latch dari dari latch tcri tcri latch dma latch incrementer/ decrementer decrementer (transfer source) (transfer destination) transfer destination address is specified by dari (note) . contents of dari are updated by incrementer/ decrementer. contents of dma latch are written to memory. (1) register operation in 2-bus cycle transfer figure 13.4.2 shows a basic operation of registers for 1-unit transfer in 2-bus cycle transfer. for register values to be specified, refer to section 13.5 single transfer mode through section 13.8 link array chain transfer mode. it is because that these values vary according to continuous transfer modes. in 2-bus cycle transfer, the data read at a read cycle is maintained temporarily in the dma latch, and the contents of this latch are written to a memory at a write cycle. fig. 13.4.2 basic operation of registers for 1-unit transfer in 2-bus cycle transfer
7721 group users manual 13-32 dma controller 13.4 operation read/write cycle (unit: f cycle) transfer unit 16 bits 8 bits 16 bits 8 bits external bus width 16 bits (including internal bus) 8 bits address directions fixed/forward backward fixed/forward/ backward fixed/forward/ backward fixed/forward/ backward even odd even odd even/odd even/odd even/odd datas start address dram area formula 1 + i 2 + 2i 2 + 2i 2 + i 1 + i 2 + 2i 1 + i no wait 2 (a) 4 (c) 4 (c) 3 (b) 2 (a) 4 (c) 2 (a) with wait 3 (d) 6 (f) 6 (f) 3 (d) 6 (f) 3 (d) address directions: refer to section 13.4.1 (3) address directions in 2-bus cycle transfer. _ i: a term of e = l in 1-bus cycle; i = 1 at no wait, and i = 2 at with wait or dram area. when ready function is used (refer to section 3.3 ready function. ), the number of cycles extended by ready must be added. ( ): indicates the corresponding waveform in figure 13.4.3. note: when a transfer destination applies to this condition, 2-bus cycle transfer cannot be performed. when a transfer source applies to this condition and a transfer destination is in the dram area, 2-bus cycle transfer cannot also be performed. (2) bus operation in 2-bus cycle transfer the time required for 1-unit transfer in 2-bus cycle transfer is given by the following formula: transfer time per 1-unit transfer = (read cycle) + (write cycle) since any area can be specified as a transfer source or a transfer destination, a read cycle varies with the conditions of a transfer source, and a write cycle with that of a transfer destination. table 13.4.1 lists the time required for a read or write cycle per 1-unit transfer in 2-bus cycle transfer, and figure 13.4.3 shows the bus-cycle operation waveforms in 2-bus cycle transfer. table 13.4.1 time required for a read or write cycle per 1-unit transfer in 2-bus cycle transfer 4 (e) 4 (e) (note)
dma controller 7721 group users manual 13-33 13.4 operation a/d e ale a/d e ale a/d e ale a/d e ale internal clock (a) a/d e ale (b) (c) a/d e ale (d) (e) (f) : read or write term per 1-unit transfer a d a d aC1 a a 1 d d a d aC1 a a 1 dd a d a: address, d : data fig. 13.4.3 bus-cycle operation waveforms in 2-bus cycle transfer
7721 group users manual 13-34 dma controller 13.4 operation (3) address directions in 2-bus cycle transfer in 2-bus cycle transfer, the address direction of a transfer source and that of a transfer destination each can be selected independently. (refer to figure 13.2.6. ) addresses move in the specified direction by the transfer unit. tables 13.4.2 through 13.4.4 list address directions in 2-bus cycle transfer and examples of transfer result. tables 13.4.2 address directions in 2-bus cycle transfer and examples of transfer result (1) high order high order transfer unit : 8 bits address direction transfer source fixed forward backward transfer unit : 16 bits transfer sequence data external data bus width : 16 bits or 8 bits ] transfer destination fixed fixed fixed data arrangement on transfer source memory data arrangement on transfer source memory data arrangement on transfer destination memory (transfer result) transfer sequence data arrangement on transfer destination memory (transfer result) data low order ] data low order high order high order ] ] data ] data low order data low order high order data low order high order data low order high order ] ] data data data data data data data ] ] data low order data low order high order data low order high order data low order high order ] ] data data data data data data data ] ] : transfer start address
dma controller 7721 group users manual 13-35 13.4 operation tables 13.4.3 address directions in 2-bus cycle transfer and examples of transfer result (2) note: the position relationship between low- order byte and high-order byte is not reversed. ] transfer unit : 8 bits address direction transfer source transfer unit : 16 bits transfer sequence external data bus width : 16 bits or 8 bits transfer destination data arrangement on transfer source memory data arrangement on transfer source memory data arrangement on transfer destination memory (transfer result) transfer sequence data arrangement on transfer destination memory (transfer result) forward fixed forward forward forward backward data 1 low order high order data 2 low order high order data 3 low order high order data 1C3 low order high order ] ] data 1 data 2 data 3 data 4 data 5 data 6 data 1C6 ] data 1 low order high order data 2 low order high order data 3 low order high order data 1 low order high order data 2 low order high order data 3 low order high order ]] ] ] data 1 data 2 data 3 data 4 data 5 data 6 data 1 data 2 data 3 data 4 data 5 data 6 ] data 1 data 2 data 3 data 4 data 5 data 6 ] data 6 data 5 data 4 data 3 data 2 data 1 data 1 data 2 data 3 ] low order high order low order high order low order high order data 3 data 2 data 1 ] low order high order low order high order low order high order ] : transfer start address
7721 group users manual 13-36 dma controller 13.4 operation tables 13.4.4 address directions in 2-bus cycle transfer and examples of transfer result (3) address direction transfer source transfer unit : 16 bits transfer sequence external data bus width : 16 bits or 8 bits transfer destination data arrangement on transfer source memory data arrangement on transfer source memory data arrangement on transfer destination memory (transfer result) transfer sequence data arrangement on transfer destination memory (transfer result) transfer unit : 8 bits backward fixed forward backward data 1 low order high order data 2 low order high order data 3 low order high order ] ] data 1C3 low order high order data 6 data 5 data 4 data 3 data 2 data 1 data 1C6 ] ] ] ] data 6 data 5 data 4 data 3 data 2 data 1 data 1 data 2 data 3 data 4 data 5 data 6 ] ] data 1 data 2 data 3 low order high order low order high order low order high order data 1 low order high order data 2 low order high order data 3 low order high order data 1 low order high order data 2 low order high order data 3 low order high order ] ] data 1 low order high order data 2 low order high order data 3 low order high order data 6 data 5 data 4 data 3 data 2 data 1 data 6 data 5 data 4 data 3 data 2 data 1 ] ] backward ] : transfer start address backward
dma controller 7721 group users manual 13-37 13.4 operation [precautions for 2-bus cycle transfer] when the 16-bit external data bus width = 16 bits and the transfer unit = 16 bits under the following conditions, 2-bus cycle transfer cannot be performed. (refer to table 13.4.1. ) ? conditions for transfer destination transfer destination = dram area, address direction = backward, datas start address = odd address ? conditions for transfer source and destination transfer source = dram area, address direction = backward, datas start address = odd address transfer destination = dram area
7721 group users manual 13-38 dma controller 13.4 operation 13.4.2 1-bus cycle transfer when the transfer method select bit (refer to figure 13.2.6. ) = 1, 1-bus cycle transfer is selected. 1-bus cycle transfer is the method used to transfer data between a memory and an i/o. in this method, a read and write of 1-tansfer-unit data are simultaneously performed during 1-bus cycle. the address bus, ____ ____ __ bhe , ble , and r/ w indicate the states of memory. figure 13.4.4 shows an example of connecting external memories and i/os in 1-bus cycle transfer. i/o m37721 address bus data bus (d 8 Cd 15 ) e bhe ble r/w dmaacki dmareqi i/o data bus (d 0 Cd 7 ) memory (odd address) memory (even address) note. the external circuit such as an address latch is disregarded. fig. 13.4.4 example of connecting external memories and i/os in 1-bus cycle transfer
dma controller 7721 group users manual 13-39 13.4 operation in 1-bus cycle transfer, the following considerations must be taken in designing the system: ? achieve the condition that 1-transfer-unit data can be accessed in 1-bus cycle. (refer to table 13.4.5. ) ? specify the transfer address direction and i/o connections. (refer to figure 13.2.7. ) ? compose the read and write signal generating circuit externally. (these signals are for i/os.) the m37721 outputs signals to the memory. accordingly, make sure to compose the circuit which generates write signals for i/os when the m37721 outputs read signals; which generates read signals for i/os when the m37721 outputs write signals. figure 13.4.5 shows an example of the circuit generating a write signal and a read signal for i/os. m37721 r/w dmaacki dmareqi e read write i/o generating circuit for read and write signals to i/os dma acknowledge dma request fig. 13.4.5 example of circuit generating write signal and read signal for i/os
7721 group users manual 13-40 dma controller 13.4 operation (1) register operation in 1-bus cycle transfer figure 13.4.6 shows a basic operation of registers for 1-unit transfer in 1-bus cycle transfer. for register values to be specified, refer to section 13.5 single transfer mode through section 13.8 link array chain transfer mode. it is because these values vary depending on each continuous transfer mode. in 1-bus cycle transfer, a read and write of 1-transfer-unit data are simultaneously performed during 1-bus cycle. fig. 13.4.6 basic operation of registers for 1-unit transfer in 1-bus cycle transfer transfer source address is specified by dari (note) . contents of tcri are updated by decrementer (note) ; when value read from tcri is 0, transfer of 1 data block is terminated. contents of dari are updated by incrementer/ decrementer. i/o is specified by dmaacki. data is output from i/o and is written to memory simultaneously (r/w = l level). transfer source address is specified by sari (note) . contents of tcri are updated by decrementer (note) ; when value read from tcri is 0, transfer of 1 data block is terminated. contents of sari are updated by incrementer/ decrementer. i/o is specified by dmaacki. data is output from memory and is written to i/o simultaneously (r/w = h level). l when transferring from memory to i/o sari sari latch dma latch dmac memory (transfer source) dmac i/o dmaacki i/o dari dari latch tcri tcri latch (transfer destination) incrementer/ decrementer decrementer l when transferring from i/o to memory memory sari sari latch dma latch dmaacki dari dari latch tcri tcri latch incrementer/ decrementer decrementer (transfer source) (transfer destination) ] when the transfer unit is 16 bits, the incrementer/decrementer and the decrementer increment or decrement by 2. note: in the single transfer mode and repeat transfer mode, only at the first transfer of the block, the values read from sari latch, dari latch, and tcri latch are used. (the results obtained by increment or decrement are written to sari, dari, and tcri. except for the first transfer of the block, the values read from sari, dari, and tcri are used.)
dma controller 7721 group users manual 13-41 13.4 operation (2) bus operation in 1-bus cycle transfer the time required for 1-unit transfer in 1-bus cycle transfer is given by the following formulas: ? transfer from memory to i/o: transfer time per 1-unit transfer = (read cycle of memory) ? transfer from i/o to memory: transfer time per 1-unit transfer = (write cycle of memory) in 1-bus cycle transfer, 1-transfer-unit data is accessed in 1-bus cycle, so that limitations are imposed on the transfer conditions to be applied. table 13.4.5 lists the conditions of 1-bus cycle transfer and the transfer time per 1-unit transfer, and figure 13.4.7 shows the bus-cycle operation waveforms in 1-bus cycle transfer. table 13.4.5 conditions of 1-bus cycle transfer and transfer time per 1-unit transfer transfer unit 16 bits 8 bits 16 bits 8 bits external bus width 16 bits (including internal bus) 8 bits address directions fixed/forward backward fixed/forward/ backward fixed/forward/ backward fixed/forward/ backward even odd even odd even/odd even/odd even/odd datas start address read/write cycle (unit: f cycle) formula 1 + i 2 + i 1 + i 1 + i no wait 2 (a) 3 (b) 2 (a) 2 (a) with wait 3 (c) 3 (c) 3 (c) dram area 4 (d) address directions: refer to section 13.4.2 (3) address directions in 1-bus cycle transfer. there is no address direction on the i/o side. _ i: a term of e = l in 1-bus cycle; i = 1 at no wait, and i = 2 at with wait or dram area. when ready function is used (refer to section 3.3 ready function. ), the number of cycles extended by ready must be added. ( ): indicates the corresponding waveform in figure 13.4.7. /: 1-bus cycle transfer cannot be performed. when the external data bus width = 16 bits and the transfer unit = 8 bits are selected, the data bus which the memory uses and the data bus to which i/o is connected may be different. in such a case, data is copied from the data bus of a transfer source to that of a transfer destination by using the dma latch. for the combination that data copy may occur, data copy delay time t d(data) must be taken into consideration. table 13.4.6 lists the data flows on the data bus in 1-bus cycle transfer, and table 13.4.7 lists the outputs of the address bus, the data bus, and the bus control signals in 1-bus cycle transfer.
7721 group users manual 13-42 dma controller 13.4 operation internal clock a/d e ale (a ) : transfer term per 1-unit transfer a d a d aC1 a d aC1 a d a : address, d : data a/d e ale (b) a/d e ale (c) a/d e ale (d) fig. 13.4.7 bus-cycle operation waveforms in 1-bus cycle transfer
dma controller 7721 group users manual 13-43 13.4 operation external data bus width i/o connection transfer unit read/write address of memory data flow 16 bits data bus d 0 Cd 7 and d 8 Cd 15 even address and odd address even address m37721 memory i/o i/o data bus d 8 Cd 15 data bus d 0 Cd 7 m37721 i/o m37721 i/o m37721 m37721 (note) note: data is copied from data bus d 0 Cd 7 to d 8 Cd 15 or from data bus d 8 Cd 15 to d 0 Cd 7 in the m37721s dmac. note the data copy delay time t d(data) . m37721 16 bits 16 bits 8 bits memory memory memory data bus d 8 Cd 15 data bus d 0 Cd 7 data bus d 8 Cd 15 data bus d 0 Cd 7 odd address i/o memory memory 16 bits 8 bits data bus d 0 Cd 7 data bus d 8 Cd 15 even address odd address (note) memory memory i/o data bus d 8 Cd 15 data bus d 0 Cd 7 note: data is copied from data bus d 0 Cd 7 to d 8 Cd 15 or from data bus d 8 Cd 15 to d 0 Cd 7 in the m37721s dmac. note the data copy delay time t d(data) . data bus d 8 Cd 15 data bus d 0 Cd 7 memory memory 8 bits 8 bits data bus d 0 Cd 7 data bus d 0 Cd 7 i/o memory even address and odd address note: when the memory is the internal memory or sfr, the above case for external data bus width = 16 bits applies. table 13.4.6 data flows on data bus in 1-bus cycle transfer
7721 group users manual 13-44 dma controller 13.4 operation external data bus width i/o connection transfer unit read/write address of memory output of address bus, data bus, and bus control signals 16 bits 16 bits data bus d 0 Cd 7 and d 8 Cd 15 data bus d 8 Cd 15 8 bits even address and odd address : when the memory is the internal memory or sfr, data is output. when the memory is the external memory, it enters a floating state. a 8 /d 8 Ca 15 /d 15 a 16 /d 0 Ca 23 /d 7 ble bhe l l transfer source address odd address data a 8 /d 8 Ca 15 /d 15 a 16 /d 0 Ca 23 /d 7 ble bhe h l invalid data ble bhe h l odd address data copy ble bhe h l ble bhe h l data h e r/w transferred from memory to i/o l l l h l invalid data h l i/o data h l h l transferred from i/o to memory 16 bits transfer source address even address data transfer destination address transfer destination address 16 bits 8 bits data bus d 0 Cd 7 even address odd address transfer source address transfer source address even address data transfer destination address transfer destination address a 8 /d 8 Ca 15 /d 15 a 16 /d 0 Ca 23 /d 7 transfer source address transfer source address transfer destination address transfer destination address copy transfer destination address transfer destination address copy i/o data a 8 /d 8 Ca 15 /d 15 a 16 /d 0 Ca 23 /d 7 transfer source address transfer source address copy even address data even address odd address a 8 /d 8 Ca 15 /d 15 a 16 /d 0 Ca 23 /d 7 transfer source address transfer source address odd address data invalid data invalid data transfer destination address transfer destination address 8 bits 8 bits data bus d 0 Cd 7 even address and odd address a 8 Ca 15 a 16 /d 0 Ca 23 /d 7 transfer source address transfer source address transfer destination address transfer destination address table 13.4.7 outputs of address bus, data bus, and bus control signals in 1-bus cycle transfer
dma controller 7721 group users manual 13-45 13.4 operation (3) address directions in 1-bus cycle transfer in 1-bus cycle transfer, the transfer source and destination address directions of memory are selectable. (refer to figure 13.2.6. ) addresses move in the specified direction by the transfer unit. tables 13.4.8 and 13.4.9 list address directions in 1-bus cycle transfer and examples of transfer results. table 13.4.8 address directions in 1-bus cycle transfer and examples of transfer results (1) fixed forward backward data low order data data data ] transfer unit : 8 bits address direction transfer source memory transfer unit : 16 bits transfer sequence external data bus width : 16 bits transfer destination i/o data arrangement on transfer source memory data arrangement on transfer source memory transfer destination i/o transfer sequence external data bus width : 16 bits or 8 bits transfer destination i/o ] ] high order low order high order data 1 low order high order data 2 low order high order data 3 low order high order ] data 1C3 low order high order ] data 1 data 2 data 3 data 4 data 5 data 6 data 1C6 data 3 data 2 data 1 low order high order low order high order low order high order ] data 1C3 low order high order ] data 1 data 2 data 3 data 4 data 5 data 6 data 1C6 ] : transfer start dd
7721 group users manual 13-46 dma controller 13.4 operation table 13.4.9 address directions in 1-bus cycle transfer and examples of transfer results (2) fixed forward data ] data transfer unit : 8 bits address direction transfer unit : 16 bits transfer sequence external data bus width : 16 bits transfer source i/o data arrangement on transfer destination memory (transfer result) transfer source i/o external data bus width : 16 bits or 8 bits transfer destination memory transfer sequence data arrangement on transfer destination memory (transfer result) transfer source i/o data ] data ] data data low order high order ] data low order high order data low order high order data data data data data data data ] data data data data data data data data data data data ] low order high order low order high order low order high order ] low order high order low order high order low order high order ] : transfer start dd backward low order high order
dma controller 7721 group users manual 13-47 13.4 operation [precautions for 1-bus cycle transfer] 1. the area that overlaps with internal ram and sfrs must not be assigned to an external memory. when the contents in the overlapped area are read, the data of internal ram or sfrs and that of external memory are simultaneously placed on the data bus; and they collide with each other. 2. for the system that transfers data with 16-bit external data bus width from an external memory to an 8-bit i/o, the external memory must be composed to be read in a unit of 8 bits. if the external memory cannot be read in a unit of 8 bits, the data read from the external memory at data copy collides with the copied data on the data bus. 3. under the following conditions, 1-bus cycle transfer cannot be performed. (refer to table 13.4.5. ): l external data bus width = 16 bits, transfer unit = 16 bits, address direction of memory = fixed or forward, datas start address of memory = odd l external data bus width = 16 bits, transfer unit = 16 bits, address direction of memory = backward, datas start address of memory = even l external data bus width = 16 bits, transfer unit = 16 bits, target memory of dma transfer = dram area, address direction of memory = backward, datas start address of memory = odd l external data bus width = 8 bits, transfer unit = 16 bits
7721 group users manual 13-48 dma controller 13.4 operation 13.4.3 burst transfer mode the burst transfer mode can operate in either edge sense or level sense mode. (1) burst transfer mode (edge sense) when the transfer mode select bit = 0 and the edge sense/level sense select bit = 0, this mode is selected. (refer to figures 13.2.6 and 13.2.8. ) in this mode, all of the dma request sources are available. figure 13.4.8 shows a transfer example in the burst transfer mode (edge sense). when once a dma request is accepted in this mode, an entire batch of data is transferred: the right to use bus is not returned to the cpu until the transfer is complete. during a burst transfer, any dma request (including that of other channels) cannot be accepted. however, the bus request signal is sampled basically at every completion of 1-unit transfer. (refer to table 13.2.3. ) when a dram refresh request or hold request is generated at this time, the right to use bus is not returned to the cpu, and the request is accepted. when the transfer of an entire batch of data is complete, the dmac relinquishes the right to use bus to the cpu. when the next dma request is generated, the right is once returned to the cpu to sample the dma request. (2) burst transfer mode (level sense) when the transfer mode select bit = 0 and the edge sense/level sense select bit = 1 , this mode is selected. (refer to figures 13.2.6 and 13.2.8. ) in this mode, only the external source is used as a dma request source. set the dma request source select bits to 0001 2 . (refer to figure 13.2.8. ) figure 13.4.9 shows a transfer example in the burst transfer mode (level sense). _________ when the dmareqi pins input level = l, the dmai request bit is cleared to 0; when this pins input level = l, the dmai request bit is set to 1. _________ therefore, when the dmareqi pins input level is l with the dmai enable bit = 1, a dma transfer _________ starts. when the dmareqi pins input level goes from l to h, the right to use bus will be returned _________ to the cpu at completion of 1-unit transfer under execution at that time. when the dmareqi pins input level goes l again, the dma transfer restarts at the next address. once a dmai transfer starts, any dma request (including that of other channels) cannot be accepted, _________ even if the dmareqi pins input level is h, until the transfer is terminated normally or forcibly. however, the bus request signal is sampled basically at every completion of 1-unit transfer. (refer to table 13.2.3. ) when a dram refresh request or hold request is generated at this time, the right to use bus is not returned to the cpu, and the request is accepted. when the transfer of an entire batch of data is complete, the dmac relinquishes the right to the cpu. if the next dma request is generated, the right is once returned to the cpu to sample the dma request.
dma controller 7721 group users manual 13-49 13.4 operation cpu dmareq0 dma0 request bit dma0 enable bit dmareq1 dma1 request bit dma1 enable bit dram refresh request right to use bus cpu dma1 dram refresh dma1 cpu dma0 cpu this example applies on the following conditions: ? channel priority level: fixed (channel 0 > channel 1) dmareq0 dma0 request bit dma0 enable bit dmareq1 dma1 request bit dma1 enable bit dram refresh request right to use bus cpu dma1 dram refresh dma1 cpu dma0 cpu channel 1 this example applies on the following conditions: ? both of dma0 and dma1 request sources are external sources. ? channel priority level: fixed (channel 0 > channel 1) entire data transfer entire data transfer channel 0 fig. 13.4.8 transfer example in the burst transfer mode (edge sense) fig. 13.4.9 transfer example in the burst transfer mode (level sense) channel 1 entire data transfer entire data transfer channel 0
7721 group users manual 13-50 dma controller 13.4 operation [precautions for burst transfer mode] 1. in the burst transfer mode (edge sense), the dmai request bit is cleared to 0 when the transfer of an entire batch of data is complete or the transfer is forced into termination. therefore, another dma request of the same channel i is invalid if generated during dmai transfer. fig. 13.4.10 timing when clearing dmai request bit to 0 in burst transfer mode 2. because interrupt priority levels are determined while the cpu fetches an operation code, interrupt requests are not accepted during a dma transfer. in the burst transfer mode (edge sense), therefore, interrupt requests cannot be accepted until the transfer of an entire batch of data is complete or the transfer is forced into termination. e transition of right to use bus (from dmac to cpu) 1-unit transfer termination processing dmai request bit is set to 0.
dma controller 7721 group users manual 13-51 13.4 operation 13.4.4 cycle-steal transfer mode when the transfer mode select bit = 1 and the edge sense/level sense select bit = 0, this mode is selected. (refer to figures 13.2.6 and 13.2.8. ) in this mode, all of the dma request sources are available. figure 13.4.11 shows a transfer example in the cycle-steal transfer mode 1-transfer-unit data is transferred for each dma request. the bus request signal is sampled basically at every completion of 1-unit transfer. (refer to table 13.2.3. ) when a dram refresh request or hold request is generated at this time, the right to use bus is not returned to the cpu, and the request is accepted. when several dma requests are generated, the request of the channel which has the highest priority among them is accepted, and dma transfer is performed without returning the right to use bus to the cpu. when any request is not generated, the cpu gains the right. cpu dma1 dram refresh cpu cpu dma0 dma1 dma0 dma1 dma1 dmareq0 dma0 request bit dma0 enable bit dmareq1 dma1 request bit dma1 enable bit dram refresh request right to use bus this example applies on the following conditions: ?both of dma0 and dma1 request sources are external sources ?channel priority level: fixed (channel 0 > channel 1) fig. 13.4.11 transfer example in cycle-steal transfer mode
7721 group users manual 13-52 dma controller 13.4 operation [precautions for cycle-steal transfer mode] 1. when dma transfers of the same channel are continuously performed in the cycle-steal transfer mode, the dmai request bit is cleared to 0 in every 1-unit transfer. also, it takes 1.5 cycles of f from the generation of a dma request until that of a bus request (dmac). therefore, if another dma request of the same channel i is generated during a dmai transfer in the cycle- steal transfer mode, any one of the following three cases occurs depending on the timing of request generation: ? the dma request becomes invalid. ? the dma transfer continues without returning the right to use bus. ? after returning the right to use bus to the cpu, the dmac regains the right and restarts the dma transfer. fig. 13.4.12 conditions for performing dma transfers of the same channel continuously 1-unit transfer ?f e dma transfers are continuously performed if dmai request bit becomes 1 during this term (on condition that dmai request bit becomes 1 at the timing satisfying t su(drq C f 1 ) ). after returning the right to use bus to cpu, dmac regains the right and restarts dma transfer if dmai request bit becomes 1 during this term. when a dmai request is generated at the following timings, it is not in time to the next bus request sampling ( ] ). therefore, dmac returns the right to use bus to the cpu. then, dmac regains the right and restarts the dma transfer. ? except for the last 1-unit transfer, 1-bus cycle transfer is selected without wait. ? except for the last 1-unit transfer, 1-bus cycle transfer is selected with wait. in addition, a time of 0.5 cycle of f is less than t su(drq C f 1 ) . dmai request is invalid even when dmai request bit becomes 1. bus request sampling ( ] ) dmai request bit is cleared to 0 during this term.
dma controller 7721 group users manual 13-53 13.4 operation 2. when a dma transfer of another channel is subsequently performed in the cycle-steal transfer mode, it takes 1.5 cycles of f from the generation of a dma request until that of a bus request (dmac). therefore, if a dma request of another channel is generated during a dmai transfer in the cycle-steal mode, either one of the following two cases occurs depending on its timing of request generation: ? the dmac performs the dma transfer subsequently without returning the right to use bus. ? after returning the right to use bus to the cpu once, the dmac regains the right and performs the dma transfer. fig. 13.4.13 conditions for performing dma transfers of another channel subsequently bus request sampling 1-unit transfer f e when a dma request is generated at the following timing, it is not in time to the next bus request sampling ( ] ). therefore, dmac returns the right to use bus to the cpu. then, the dmac regains the right and restarts dma transfer. ? except for the last 1-unit transfer is selected without wait. in addition, a time of 0.5 cycle of f is less than t su(drq C f 1) . ( ] ) dma transfer is subsequently performed if dmai request bit of another channel becomes 1 during this term (on condition that dmai request bit of another channel becomes 1 at the timing satisfying t su(drq C f 1 ) ). after returning the right to use bus to cpu once, dmac regains the right and restarts dma transfer if dmai request bit of another channel becomes 1 during this term.
13-54 dma controller 13.5 single transfer mode 7721 group users manual 13.5 single transfer mode this mode is used to transfer a block of data once. table 13.5.1 lists the specifications of the single transfer mode, and figure 13.5.1 shows the register structures of sari, dari, and tcri in this mode. table 13.5.1 specifications of single transfer mode performance specifications not required. tcri = 0 ___ l falling edge of the tc pins input from h to l ___ (when the tc pin validity bit =1) l write 0 to the dmai enable bit at normal termination sari latch: indicates the transfer start address of data block at the transfer source. sari: indicates the address of the next transfer source. dari latch: indicates the transfer start address of data block at the transfer destination. dari: indicates the address of the next transfer destination. tcri latch: indicates the number of transfer bytes. tcri: indicates the number of remaining transfer bytes. item transfer parameter memory condition of normal termination conditions of forced termination interrupt request generation timing functions of registers ___ tc pin validity bit: bit 1 at address 68 16
13-55 dma controller 13.5 single transfer mode 7721 group users manual b7 b0 b15 b8 source address register 0 (addresses 1fc2 16 to 1fc0 16 ) (sar0) source address register 1 (addresses 1fd2 16 to 1fd0 16 ) (sar1) source address register 2 (addresses 1fe2 16 to 1fe0 16 ) (sar2) source address register 3 (addresses 1ff2 16 to 1ff0 16 ) (sar3) functions bit at reset rw 23 to 0 [write] set the transfer start address of the source. these bits can be set to ?00000 16 ?to ?fffff 16 . [read] the read value indicates the source address of data which is next transferred. undefined rw note: when writing to this register, write to all 24 bits. b23 b16 b7 b0 b15 b8 destination address register 0 (addresses 1fc6 16 to 1fc4 16 ) (dar0) destination address register 1 (addresses 1fd6 16 to 1fd4 16 ) (dar1) destination address register 2 (addresses 1fe6 16 to 1fe4 16 ) (dar2) destination address register 3 (addresses 1ff6 16 to 1ff4 16 ) (dar3) functions bit at reset rw 23 to 0 [write] set the transfer start address of the destination. these bits can be set to ?00000 16 ?to ?fffff 16 . [read] the read value indicates the destination address of data which is next transferred. undefined rw note: when writing to this register, write to all 24 bits. b23 b16 b7 b0 b15 b8 transfer counter register 0 (addresses 1fca 16 to 1fc8 16 ) (tcr0) transfer counter register 1 (addresses 1fda 16 to 1fd8 16 ) (tcr1) transfer counter register 2 (addresses 1fea 16 to 1fe8 16 ) (tcr2) transfer counter register 3 (addresses 1ffa 16 to 1ff8 16 ) (tcr3) functions bit at reset rw 23 to 0 [write] set the byte number of the transfer data. these bits can be set to ?00001 16 ?to ?fffff 16 . [read] the read value indicates remaining byte number of the transfer data. undefined rw note: when writing to this register, write to all 24 bits. do not set this register to ?00000 16 . b23 b16 fig. 13.5.1 register structures of sari, dari, and tcri in single transfer mode
13-56 dma controller 13.5 single transfer mode 7721 group users manual 13.5.1 setting of single transfer mode figures 13.5.2 through 13.5.4 show an initial setting example for registers relevant to the single transfer mode. in addition, when timer a, timer b, uart, or the a-d converter is selected as a dma request source, the setting for the peripheral is required. for details of the setting, refer to the chapter of each peripheral function. when a dmai interrupt is used, the setting for enabling the interrupt is also required. for details, refer to chapter 7. interrupts. fig. 13.5.2 initial setting example for registers relevant to single transfer mode (1) when external dma source is selected when internal dma source is selected aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa setting interrupt priority level b7 b0 dmai interrupt control register (i = 0 to 3) (addresses 6c 16 to 6f 16 ) interrupt priority level select bits when using interrupts, set these bits to one of levels 1 to 7. when disabling interrupts, set these bits to level 0. continue to ?igure 13.5.3 on next page. aaaaaaaaaaaaa aaaaaaaaaaaaa aaaaaaaaaaaaa aaaaaaaaaaaaa aaaaaaaaaaaaa aaaaaaaaaaaaa aaaaaaaaaaaaa b7 b0 port p9 direction register (address 15 16 ) setting port p9 direction register dmareq0 pin dmareq1 pin dmareq2 pin clear the corresponding bit to ?. dmareq3 pin
13-57 dma controller 13.5 single transfer mode 7721 group users manual b7 b0 aaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaa selection of transfer mode and each function b7 b0 0 b7 b0 0 0 0 0 from preceding figure 13.5.2 b7 b0 b0 b0 b7 b7 (b23) (b8) (b16)(b15) set the transfer start address of transfer source. these bits can be set to ?00000 16 ?to ?fffff 16 . b7 b0 b0 b0 b7 b7 (b23) (b8) (b16)(b15) b7 b0 b0 b0 b7 b7 (b23) (b8) (b16)(b15) dma0 mode register l (address 1fcc 16 ) dma1 mode register l (address 1fdc 16 ) dma2 mode register l (address 1fec 16 ) dma3 mode register l (address 1ffc 16 ) number-of-unit-transfer-bits select bit 0 : 16 bits 1 : 8 bits transfer method select bit 0 : 2-bus cycle transfer 1 : 1-bus cycle transfer transfer mode select bit 0 : burst transfer mode 1 : cycle-steal transfer mode transfer source address direction select bits 0 0 : fixed 0 1 : forward 1 0 : backward 1 1 : do not select. transfer destination address direction select bits 0 0 : fixed 0 1 : forward 1 0 : backward 1 1 : do not select. dma0 mode register h (address 1fcd 16 ) dma1 mode register h (address 1fdd 16 ) dma2 mode register h (address 1fed 16 ) dma3 mode register h (address 1ffd 16 ) transfer direction select bit (used in 1-bus cycle transfer) 0 : from memory to i/o 1 : from i/o to memory i/o connection select bit (valid in 1-bus cycle transfer) 0 : data bus d 0 ? 7 or d 0 ? 15 1 : data bus d 8 ? 15 transfer source wait bit (valid in dma transfer) 0 : wait 1 : no wait transfer destination wait bit (valid in dma transfer) 0 : wait 1 : no wait selection of single transfer mode source address register 0 (addresses 1fc2 16 to 1fc0 16 ) (sar0) source address register 1 (addresses 1fd2 16 to 1fd0 16 ) (sar1) source address register 2 (addresses 1fe2 16 to 1fe0 16 ) (sar2) source address register 3 (addresses 1ff2 16 to 1ff0 16 ) (sar3) destination address register 0 (addresses 1fc6 16 to 1fc4 16 ) (dar0) destination address register 1 (addresses 1fd6 16 to 1fd4 16 ) (dar1) destination address register 2 (addresses 1fe6 16 to 1fe4 16 ) (dar2) destination address register 3 (addresses 1ff6 16 to 1ff4 16 ) (dar3) set the transfer start address of destination. these bits can be set to ?00000 16 ?to ?fffff 16 . transfer counter register 0 (addresses 1fca 16 to 1fc8 16 ) (tcr0) transfer counter register 1 (addresses 1fda 16 to 1fd8 16 ) (tcr1) transfer counter register 2 (addresses 1fea 16 to 1fe8 16 ) (tcr2) transfer counter register 3 (addresses 1ffa 16 to 1ff8 16 ) (tcr3) set the byte number of transfer data. these bits can be set to ?00001 16 ?to ?fffff 16 . notes 1: when writing to these registers, write to all 24 bits. 2: do not write ?00000 16 ?to tcri. note 3: when data is transferred from memory to i/o in 1-bus cycle transfer, it is unnecessary to set dari. when data is transferred form i/o to memory in 1-bus cycle transfer, it is unnecessary to set sari. dma0 control register (address 1fce 16 ) dma1 control register (address 1fde 16 ) dma2 control register (address 1fee 16 ) dma3 control register (address 1ffe 16 ) 0 0 0 0 : do not select. 0 0 0 1 : external source (dmareqi) 0 0 1 0 : software dma source 0 0 1 1 : timer a0 0 1 0 0 : timer a1 0 1 0 1 : timer a2 0 1 1 0 : timer a3 0 1 1 1 : timer a4 1 0 0 0 : timer b0 1 0 0 1 : timer b1 1 0 1 0 : timer b2 1 0 1 1 : uart0 receive 1 1 0 0 : uart0 transmit 1 1 0 1 : uart1 receive 1 1 1 0 : uart1 transmit 1 1 1 1 : a-d conversion edge sense/level sense select bit (note) 0 : edge sense 1 : level sense dmaacki validity bit 0 : invalid 1 : valid note: when an external source (dmareqi) is selected or when the cycle-steal transfer mode is selected, set this bit to ?.? continue to ?igure 13.5.4 on next page. dma request source select bits fig. 13.5.3 initial setting example for registers relevant to single transfer mode (2)
13-58 dma controller 13.5 single transfer mode 7721 group users manual fig. 13.5.4 initial setting example for registers relevant to single transfer mode (3) dma transfer starts aaa aaa aaa aaaaaaaaaaaaa aaaaaaaaaaaaa aaaaaaaaaaaaa aaaaaaaaaaaaa aaaaaaaaaaaaa b7 b0 aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa b7 b0 00 00 0 : no request aaaaaaaaaaaaa aaaaaaaaaaaaa aaaaaaaaaaaaa aaaaaaaaaaaaa aaaaaaaaaaaaa aaaaaaaaaaaaa aaaaaaaaaaaaa aaaaaaaaaaaaa b7 b0 aaaaa aaaaa aaaaa aaaaa aaaaa aaaaa when selecting external dma source from preceding ?igure 13.5.3 priority select bit 0 : fixed 1 : rotating dmac control register l (address 68 16 ) tc pin validity bit 0 : invalid (p10 3 pin functions as a programmable i/o port.) 1 : valid (p10 3 pin functions as tc pin.) dma0 request bit dma1 request bit dma2 request bit dma3 request bit selection of priority level and tc pin, and setting dmai request bit to ?? software dmai request bit (valid in software dma source selected) bit 0 : channel 0 bit 1 : channel 1 bit 2 : channel 2 bit 3 : channel 3 0 : disabled 1 : enabled dmac control register h (address 69 16 ) dma0 enable bit dma1 enable bit dma2 enable bit dma3 enable bit when selecting internal dma source when selecting internal dma source except software inputting dma request signal to dmareqi pin interrupt request of each peripheral function occurs dmac control register h (address 69 16 ) software dma0 request bit software dma1 request bit software dma2 request bit software dma3 request bit 0 : no request 1 : requested when selecting software dma request when writing ?,?dma request is generated.
13-59 dma controller 13.5 single transfer mode 7721 group users manual 13.5.2 operation in single transfer mode figure 13.5.5 shows the operation flowchart of the single transfer mode, and figure 13.5.6 shows a timing diagram of the single transfer mode (burst transfer mode). for the cycle-steal transfer mode, refer to the following: ? all transfers except for the last 1-unit transfer: figure 13.8.12 ? last 1-unit transfer: figure 13.8.14 also, refer to section 13.2.1 bus access control circuit for the bus request sampling during transfer. dmai request bit ? 0 1-unit transfer transfer completion of 1 block ? tc l output (note) dmai interrupt request bit ? 1 dmai enable bit ? 0 (only in cycle-steal transfer mode) (refer to section 13.4 operation. ) n y note: when tc pin validity bit is 1 1 burstedge : in burst transfer mode (edge sense) burstlevell : in burst transfer mode (level sense) with dmareqi pins input level = l burstlevelh : in burst transfer mode (level sense) with dmareqi pins input level = h cycle-stealrequested : in cycle-steal transfer mode with any request of dma0C3 cycle-stealno request h no request of dma0C3 dmai request bit ? 0 (only burstedge) dmai request bit ? burstlevelh cycle-stealno request 0 burstedge burstlevell cycle-stealrequested fig. 13.5.5 operation flowchart of single transfer mode : in cycle-steal transfer mode wit
13-60 dma controller 13.5 single transfer mode 7721 group users manual fig. 13.5.6 timing diagram of single transfer mode (burst transfer mode) f ale e r/w a 0 Ca 7 a 8 /d 8 Ca 15 /d 15 a 16 /d 0 Ca 23 /d 7 bus request sampling dmaacki tc st1, st0 read cycle 1-unit transfer transition of right to use bus terminate processing pc l sar l dar l (sar+2) l (dar+2) l (sar+4) l (dar+4) l (sar+6) l pc l pc h sar m dar m (sar+2) m (sar+6) m pc h pg sar h dar h (sar+2) h (sar+6) l pg memory data 0 data 1 data 2 l h l h l h dar dar+5 transfer sar sar+5 1, 0 (dmac) 1, 1 (cpu) write cycle l this example applies on the following conditions: external data bus width : 16 bits transfer unit : 16 bits transfer method : 2-bus cycle transfer transfer mode : burst transfer source address direction : forward transfer destination address direction : forward transfer source wait : no transfer destination wait : no sar : the value which is set to sari (even) dar : the value which is set to dari (even) tcr set value : 6 right to use bus : cpu ? dmac ? cpu l the bus request caused by dram refresh or hold is sampled while the bus request sampling signal is 1, and is accepted. transition of right to use bus data 0 h data 0 l data 0 h data 0 l (dar+2) m (dar+2) h data 1 h data 1 l data 1 h data 1 l (sar+4) m (sar+4) h data 2 h data 2 l (dar+4) m (dar+4) h data 2 h data 2 l
13-61 dma controller 13.6 repeat transfer mode 7721 group users manual 13.6 repeat transfer mode this mode is used to transfer one block of data repeatedly. table 13.6.1 lists the specifications of the repeat transfer mode, and figure 13.6.1 shows the register structures of sari, dari, and tcri in this mode. table 13.6.1 specifications of repeat transfer mode item transfer parameter memory condition of normal termination conditions of forced termination interrupt request generation timing functions of registers performance specifications not required (no normal termination) ___ l falling edge of the tc pins input from h to l ___ (when the tc pin validity bit = 1) l write 0 to the dmai enable bit no request is generated. sari latch: indicates the transfer start address of data block at the transfer source. sari: indicates the address of the next transfer source. dari latch: indicates the transfer start address of data block at the transfer destination. dari: indicates the address of the next transfer destination. tcri latch: indicates the number of transfer bytes. tcri: indicates the number of remaining bytes being transferred. ___ tc pin validity bit: bit 1 at address 68 16
dma controller 13-62 13.6 repeat transfer mode 7721 group users manual b7 b0 b15 b8 source address register 0 (addresses 1fc2 16 to 1fc0 16 ) (sar0) source address register 1 (addresses 1fd2 16 to 1fd0 16 ) (sar1) source address register 2 (addresses 1fe2 16 to 1fe0 16 ) (sar2) source address register 3 (addresses 1ff2 16 to 1ff0 16 ) (sar3) functions bit at reset rw 23 to 0 undefined rw note: when writing to this register, write to all 24 bits. b23 b16 b7 b0 b15 b8 destination address register 0 (addresses 1fc6 16 to 1fc4 16 ) (dar0) destination address register 1 (addresses 1fd6 16 to 1fd4 16 ) (dar1) destination address register 2 (addresses 1fe6 16 to 1fe4 16 ) (dar2) destination address register 3 (addresses 1ff6 16 to 1ff4 16 ) (dar3) functions bit at reset rw 23 to 0 [write] set the transfer start address of the destination. these bits can be set to ?00000 16 ?to ?fffff 16 . [read] the read value indicates the destination address of data which is next transferred. undefined rw note: when writing to this register, write to all 24 bits. b23 b16 b7 b0 b15 b8 transfer counter register 0 (addresses 1fca 16 to 1fc8 16 ) (tcr0) transfer counter register 1 (addresses 1fda 16 to 1fd8 16 ) (tcr1) transfer counter register 2 (addresses 1fea 16 to 1fe8 16 ) (tcr2) transfer counter register 3 (addresses 1ffa 16 to 1ff8 16 ) (tcr3) functions bit at reset rw 23 to 0 [write] set the byte number of transfer data. these bits can be set to ?00001 16 ?to ?fffff 16 . [read] the read value indicates the remaining byte number of the block which is being transferred. undefined rw note: when writing to this register, write to all 24 bits. do not write ?00000 16 ?to this register. b23 b16 [write] set the transfer start address of the source. these bits can be set to ?00000 16 ?to ?fffff 16 . [read] the read value indicates the source address of data which is next transferred. fig. 13.6.1 register structures of sari, dari, and tcri in repeat transfer mode
13-63 dma controller 13.6 repeat transfer mode 7721 group users manual 13.6.1 setting of repeat transfer mode figures 13.6.2 through 13.6.4 show an initial setting example for registers relevant to the repeat transfer mode. in addition, when timer a, timer b, uart, or the a-d converter is selected as a dma request source, the setting for the peripheral is required. for details of the setting, refer to the chapter of each peripheral function. in this mode, only the forced termination can terminate the dma transfer. (refer to section 13.3.5 (2) forced termination. therefore, in the burst transfer mode (edge sense selected), be sure to validate the ___ tc pin. when external dma source is selected when internal dma source is selected continue to ?igure 13.6.3 on next page. aaaaaaaaaaaaa aaaaaaaaaaaaa aaaaaaaaaaaaa aaaaaaaaaaaaa aaaaaaaaaaaaa aaaaaaaaaaaaa aaaaaaaaaaaaa b7 b0 port p9 direction register (address 15 16 ) setting port p9 direction register dmareq0 pin dmareq1 pin dmareq2 pin clear the corresponding bit to ?. dmareq3 pin fig. 13.6.2 initial setting example for registers relevant to repeat transfer mode (1)
dma controller 13-64 13.6 repeat transfer mode 7721 group users manual b7 b0 aaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaa selection of transfer mode and each function b7 b0 0 b7 b0 0 0 1 0 from preceding figure 13.6.2 b7 b0 b0 b0 b7 b7 (b23) (b8) (b16)(b15) set the transfer start address of transfer source. these bits can be set to ?00000 16 ?to ?fffff 16 . b7 b0 b0 b0 b7 b7 (b23) (b8) (b16)(b15) b7 b0 b0 b0 b7 b7 (b23) (b8) (b16)(b15) dma0 mode register l (address 1fcc 16 ) dma1 mode register l (address 1fdc 16 ) dma2 mode register l (address 1fec 16 ) dma3 mode register l (address 1ffc 16 ) number-of-unit-transfer-bits select bit 0 : 16 bits 1 : 8 bits transfer method select bit 0 : 2-bus cycle transfer 1 : 1-bus cycle transfer transfer mode select bit 0 : burst transfer mode 1 : cycle-steal transfer mode transfer source address direction select bits 0 0 : fixed 0 1 : forward 1 0 : backward 1 1 : do not select. transfer destination address direction select bits 0 0 : fixed 0 1 : forward 1 0 : backward 1 1 : do not select. dma0 mode register h (address 1fcd 16 ) dma1 mode register h (address 1fdd 16 ) dma2 mode register h (address 1fed 16 ) dma3 mode register h (address 1ffd 16 ) transfer direction select bit (used in 1-bus cycle transfer) 0 : from memory to i/o 1 : from i/o to memory i/o connection select bit (valid in 1-bus cycle transfer) 0 : data bus d 0 ? 7 or d 0 ? 15 1 : data bus d 8 ? 15 transfer source wait bit (valid in dma transfer) 0 : wait 1 : no wait transfer destination wait bit (valid in dma transfer) 0 : wait 1 : no wait selection of repeat transfer mode source address register 0 (addresses 1fc2 16 to 1fc0 16 ) (sar0) source address register 1 (addresses 1fd2 16 to 1fd0 16 ) (sar1) source address register 2 (addresses 1fe2 16 to 1fe0 16 ) (sar2) source address register 3 (addresses 1ff2 16 to 1ff0 16 ) (sar3) destination address register 0 (addresses 1fc6 16 to 1fc4 16 ) (dar0) destination address register 1 (addresses 1fd6 16 to 1fd4 16 ) (dar1) destination address register 2 (addresses 1fe6 16 to 1fe4 16 ) (dar2) destination address register 3 (addresses 1ff6 16 to 1ff4 16 ) (dar3) set the transfer start address of destination. these bits can be set to ?00000 16 ?to ?fffff 16 . transfer counter register 0 (addresses 1fca 16 to 1fc8 16 ) (tcr0) transfer counter register 1 (addresses 1fda 16 to 1fd8 16 ) (tcr1) transfer counter register 2 (addresses 1fea 16 to 1fe8 16 ) (tcr2) transfer counter register 3 (addresses 1ffa 16 to 1ff8 16 ) (tcr3) set the byte number of transfer data. these bits can be set to ?00001 16 ?to ?fffff 16 . notes 1: when writing to these registers, write to all 24 bits. 2: do not write ?00000 16 ?to tcri. note 3: when data is transferred from memory to i/o in 1-bus cycle transfer, it is unnecessary to set dari. when data is transferred form i/o to memory in 1-bus cycle transfer, it is unnecessary to set sari. dma0 control register (address 1fce 16 ) dma1 control register (address 1fde 16 ) dma2 control register (address 1fee 16 ) dma3 control register (address 1ffe 16 ) 0 0 0 0 : do not select. 0 0 0 1 : external source (dmareqi) 0 0 1 0 : software dma source 0 0 1 1 : timer a0 0 1 0 0 : timer a1 0 1 0 1 : timer a2 0 1 1 0 : timer a3 0 1 1 1 : timer a4 1 0 0 0 : timer b0 1 0 0 1 : timer b1 1 0 1 0 : timer b2 1 0 1 1 : uart0 receive 1 1 0 0 : uart0 transmit 1 1 0 1 : uart1 receive 1 1 1 0 : uart1 transmit 1 1 1 1 : a-d conversion edge sense/level sense select bit (note) 0 : edge sense 1 : level sense dmaacki validity bit 0 : invalid 1 : valid note: when an external source (dmareqi) is selected or when the cycle-steal transfer mode is selected, set this bit to ?.? continue to ?igure 13.6.4 on next page. dma request source select bits fig. 13.6.3 initial setting example for registers relevant to repeat transfer mode (2)
13-65 dma controller 13.6 repeat transfer mode 7721 group users manual fig. 13.6.4 initial setting example for registers relevant to repeat transfer mode (3) dma transfer starts aaa aaa aaa aaaaaaaaaaaaa aaaaaaaaaaaaa aaaaaaaaaaaaa aaaaaaaaaaaaa aaaaaaaaaaaaa b7 b0 aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa b7 b0 00 00 0 : no request aaaaaaaaaaaaa aaaaaaaaaaaaa aaaaaaaaaaaaa aaaaaaaaaaaaa aaaaaaaaaaaaa aaaaaaaaaaaaa aaaaaaaaaaaaa b7 b0 aaaaa aaaaa inputting dma request signal to dmareqi pin aaaa aaaa when selecting external dma source from preceding ?igure 13.6.3 priority select bit 0 : fixed 1 : rotating dmac control register l (address 68 16 ) tc pin validity bit 0 : invalid (p10 3 pin functions as a programmable i/o port.) 1 : valid (p10 3 pin functions as tc pin.) dma0 request bit dma1 request bit dma2 request bit dma3 request bit software dmai request bit (valid in software dma source selected) bit 0 : channel 0 bit 1 : channel 1 bit 2 : channel 2 bit 3 : channel 3 0 : disabled 1 : enabled dmac control register h (address 69 16 ) dma0 enable bit dma1 enable bit dma2 enable bit dma3 enable bit when selecting internal dma source when selecting internal dma source except software interrupt request of each peripheral function occurs dmac control register h (address 69 16 ) software dma0 request bit software dma1 request bit software dma2 request bit software dma3 request bit 0 : no request 1 : requested when selecting software dma request when writing ?,?dma request is generated. note: when the burst transfer mode (edge sense) is selected, set bit 1 to ?. selection of priority level and tc pin, and setting dmai request bit to ??
dma controller 13-66 13.6 repeat transfer mode 7721 group users manual 13.6.2 operation in repeat transfer mode figure 13.6.5 shows the operation flowchart of the repeat transfer mode, and figure 13.6.6 shows a timing diagram of the repeat transfer mode (burst transfer mode). for the cycle-steal transfer mode, refer to the following: ? all transfers except for the last 1-unit transfer: figure 13.8.12 ? last 1-unit transfer: figure 13.8.13 also, refer to section 13.2.1 bus access control circuit for the bus request sampling during transfer. dmai request bit ? 0 1-unit transfer (only in cycle-steal transfer mode) (refer to section 13.4 operation. ) 1 burstedge : in burst transfer mode (edge sense) burstlevell : in burst transfer mode (level sense) with dmareqi pins input level = l burstlevelh : in burst transfer mode (level sense) with dmareqi pins input level = h cycle-stealrequested : in cycle-steal transfer mode with any request of dma0C3 cycle-stealno request : in cycle-steal transfer mode wit h no request of dma0C3 dmai request bit ? burstlevelh cycle-stealno request burstedge burstlevell cycle-stealrequested 0 fig. 13.6.5 operation flowchart of repeat transfer mode
13-67 dma controller 13.6 repeat transfer mode 7721 group users manual fig. 13.6.6 timing diagram of repeat transfer mode (burst transfer mode) f ale e r/w a 0 Ca 7 a 8 /d 8 Ca 15 /d 15 a 16 /d 0 Ca 23 /d 7 bus request sampling dmaacki tc st1, st0 transfer of entire batch of data (first) pc l sar dar (sar+4) (dar+4) (sar+6) sar dar pc h sar (sar+6) dar pg sar (sar+6) dar h 1, 0 (dmac) 1-unit transfer transition of right to use bus transfer of entire batch of data (second) memory data 0 data 1 data 2 l h l h l h dar dar+5 transfer sar sar+5 l this example applies on the following conditions: external data bus width : 16 bits transfer unit : 16 bits transfer method : 2-bus cycle transfer transfer mode : burst transfer source address direction : forward transfer destination address direction : forward transfer source wait : no transfer destination wait : no sar : the value which is set to sari (even) dar : the value which is set to dari (even) tcr set value : 6 right to use bus : cpu ? dmac l the bus request caused by dram refresh or hold is sampled while the bus request sampling signal is 1, and is accepted. l m h l l l l m l l l m h data0 h data0 l dar m dar h data0 h data0 l (sar+4) m (sar+4) h data2 h data2 l (dar+4) m (dar+4) h data2 h data2 l sar m sar h data0 h data0 l
dma controller 13-68 13.7 array chain transfer mode 7721 group users manual 13.7 array chain transfer mode this mode is used to transfer several blocks of data. according to the information of each block stored in memory area (note) , several blocks of data are transferred. all of the transfer parameters must be located in series. table 13.7.1 lists the specifications of the array chain transfer mode, and figure 13.7.1 shows the register structures of sari, dari, and tcri in this mode. note: each of the following information is called transfer parameter: transfer start addresses of transfer source and destination, and transfer datas byte number. table 13.7.1 specifications of array chain transfer mode item transfer parameter memory condition of normal termination conditions of forced termination interrupt request generation timing functions of registers performance specifications required. l in 2-bus cycle transfer: 12 bytes per one block (transfer sources transfer start address, transfer destinations transfer start address, transfer datas byte number) l in 1-bus cycle transfer: 8 bytes per one block (from memory to i/o: transfer sources transfer start address, transfer datas byte number) (from i/o to memory: transfer destinations transfer start address, transfer datas byte number) tcri latch = 0 and tcri = 0 ___ l falling edge of the tc pins input from h to l ___ (when the tc pin validity bit = 1) l write 0 to the dmai enable bit at normal termination sari latch: indicates the transfer parameter memorys start address of the next block. sari: indicates the address of the next transfer source. dari latch: not used. dari: indicates the address of the next transfer destination. tcri latch: indicates the number of remaining transfer blocks. tcri: indicates the number of remaining transfer bytes. ___ tc pin validity bit: bit 1 at address 68 16
dma controller 13-69 13.7 array chain transfer mode 7721 group users manual b7 b0 b15 b8 source address register 0 (addresses 1fc2 16 to 1fc0 16 ) (sar0) source address register 1 (addresses 1fd2 16 to 1fd0 16 ) (sar1) source address register 2 (addresses 1fe2 16 to 1fe0 16 ) (sar2) source address register 3 (addresses 1ff2 16 to 1ff0 16 ) (sar3) functions bit at reset rw 23 to 0 [write] set the start address of transfer parameter memory. these bits can be set to ?00000 16 ?to ?fffff 16 . [read] ?after a value is written to this register and until transfer starts, the read value indicates the written value (the start address of the transfer parameter memory). ?after transfer starts, the read value indicates the source address of data which is next transferred. undefined rw note: when writing to this register, write to all 24 bits. b23 b16 b7 b0 b15 b8 destination address register 0 (addresses 1fc6 16 to 1fc4 16 ) (dar0) destination address register 1 (addresses 1fd6 16 to 1fd4 16 ) (dar1) destination address register 2 (addresses 1fe6 16 to 1fe4 16 ) (dar2) destination address register 3 (addresses 1ff6 16 to 1ff4 16 ) (dar3) functions bit at reset rw 23 to 0 need not to be set. [read] after transfer starts, the read value indicates the destination address of data which is next transferred. undefined rw b23 b16 b7 b0 b15 b8 transfer counter register 0 (addresses 1fca 16 to 1fc8 16 ) (tcr0) transfer counter register 1 (addresses 1fda 16 to 1fd8 16 ) (tcr1) transfer counter register 2 (addresses 1fea 16 to 1fe8 16 ) (tcr2) transfer counter register 3 (addresses 1ffa 16 to 1ff8 16 ) (tcr3) functions bit at reset rw 23 to 0 [write] set the number of transfer blocks. these bits can be set to ?00001 16 ?to ?fffff 16 . [read] ?after a value is written to this register and until transfer starts, the read value indicates the written value (the transfer block number) . ?after transfer starts, the read value indicates the remaining byte number of the block which is being transferred. undefined rw note: when writing to this register, write to all 24 bits. do not write ?00000 16 ?to this register. b23 b16 fig. 13.7.1 register structures of sari, dari, and tcri in array chain transfer mode
dma controller 13-70 13.7 array chain transfer mode 7721 group users manual 13.7.1 transfer parameter memory in array chain transfer mode the transfer parameters required for each transfer method are described below. these parameters must be located in series starting at an even addresses. figure 13.7.2 shows a transfer parameter memory map in the array chain transfer mode. (1) in 2-bus cycle transfer all of the following transfer parameters are required for each block of data; that is, a transfer parameter memory consumes 12 bytes for each block. ? transfer sources transfer start address (24 bits) + dummy data (8 bits) ? transfer destinations transfer start address (24 bits) + dummy data (8 bits) ? transfer datas byte number (24 bits) + dummy data (8 bits) (2) in 1-bus cycle transfer from memory to i/o all of the following transfer parameters are required for each block of data; that is, a transfer parameter memory consumes 8 bytes for each block. ? transfer sources transfer start address (24 bits) + dummy data (8 bits) ? transfer datas byte number (24 bits) + dummy data (8 bits) (3) in 1-bus cycle transfer from i/o to memory all of the following transfer parameters are required for each block of data; that is, a transfer parameter memory consumes 8 bytes for each block. ? transfer destinations transfer start address (24 bits) + dummy data (8 bits) ? transfer datas byte number (24 bits) + dummy data (8 bits)
dma controller 13-71 13.7 array chain transfer mode 7721 group users manual (1) 2-bus cycle transfer ] the above applies when 4-block transfer is performed. transfer sources transfer start address 1 transfer destinations transfer start address 1 transfer datas byte number 1 transfer sources transfer start address 2 transfer destinations transfer start address 2 transfer datas byte number 2 transfer sources transfer start address 3 transfer destinations transfer start address 3 transfer datas byte number 3 transfer sources transfer start address 4 transfer destinations transfer start address 4 transfer datas byte number 4 l m h l m h l m h transfer datas byte number dummy data even address 4 bytes 4 bytes 4 bytes transfer sources transfer start address transfer destinations transfer start address dummy data dummy data even address even address transfer parameters for 1 block (2) 1-bus cycle transfer 4 bytes 4 bytes transfer sources transfer start address 1 transfer datas byte number 1 transfer sources transfer start address 2 transfer datas byte number 2 transfer sources transfer start address 3 transfer datas byte number 3 transfer sources transfer start address 4 transfer datas byte number 4 transfer datas byte number dummy data transfer sources transfer start address dummy data l m h l m h even address even address transfer parameters for 1 block ] the above applies on the following conditions: ?when data is transferred from memory to i/o (when transferring from i/o to memory, replace all the above mentioned transfer sources transfer start address with transfer destinations transfer start address.) ?4-block transfer fig. 13.7.2 transfer parameter memory map in array chain transfer mode
dma controller 13-72 13.7 array chain transfer mode 7721 group users manual 13.7.2 setting of array chain transfer mode figures 13.7.3 through 13.7.5 show an initial setting example for registers relevant to the array chain transfer mode. in addition, when timer a, timer b, uart, or the a-d converter is selected as a dma request source, the setting for the peripheral is required. for details of the setting, refer to the chapter of each peripheral function. when a dmai interrupt is used, the setting for enabling the interrupt is also required. for details, refer to chapter 7. interrupts. fig. 13.7.3 initial setting example for registers relevant to array chain transfer mode (1) when external dma source is selected when internal dma source is selected aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa setting interrupt priority level b7 b0 dmai interrupt control register (i = 0 to 3) (addresses 6c 16 to 6f 16 ) interrupt priority level select bits when using interrupts, set these bits to one of levels 1 to 7. when disabling interrupts, set these bits to level 0. continue to ?igure 13.7.4 on next page. aaaaaaaaaaaaa aaaaaaaaaaaaa aaaaaaaaaaaaa aaaaaaaaaaaaa aaaaaaaaaaaaa aaaaaaaaaaaaa aaaaaaaaaaaaa b7 b0 port p9 direction register (address 15 16 ) setting port p9 direction register dmareq0 pin dmareq1 pin dmareq2 pin clear the corresponding bit to ?. dmareq3 pin
dma controller 13-73 13.7 array chain transfer mode 7721 group users manual b7 b0 aaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaa selection of transfer mode and each function b7 b0 0 b7 b0 0 0 0 1 from preceding figure 13.7.3 b7 b0 b0 b0 b7 b7 (b23) (b8) (b16)(b15) set the start address of transfer parameter memory. these bits can be set to ?00000 16 ?to ?fffff 16 . b7 b0 b0 b0 b7 b7 (b23) (b8) (b16)(b15) dma0 mode register l (address 1fcc 16 ) dma1 mode register l (address 1fdc 16 ) dma2 mode register l (address 1fec 16 ) dma3 mode register l (address 1ffc 16 ) number-of-unit-transfer-bits select bit 0 : 16 bits 1 : 8 bits transfer method select bit 0 : 2-bus cycle transfer 1 : 1-bus cycle transfer transfer mode select bit 0 : burst transfer mode 1 : cycle-steal transfer mode transfer source address direction select bits 0 0 : fixed 0 1 : forward 1 0 : backward 1 1 : do not select. transfer destination address direction select bits 0 0 : fixed 0 1 : forward 1 0 : backward 1 1 : do not select. dma0 mode register h (address 1fcd 16 ) dma1 mode register h (address 1fdd 16 ) dma2 mode register h (address 1fed 16 ) dma3 mode register h (address 1ffd 16 ) transfer direction select bit (used in 1-bus cycle transfer) 0 : from memory to i/o 1 : from i/o to memory i/o connection select bit (valid in 1-bus cycle transfer) 0 : data bus d 0 ? 7 or d 0 ? 15 1 : data bus d 8 ? 15 transfer source wait bit (valid in dma transfer) 0 : wait 1 : no wait transfer destination wait bit (valid in dma transfer) 0 : wait 1 : no wait selection of array chain transfer mode source address register 0 (addresses 1fc2 16 to 1fc0 16 ) (sar0) source address register 1 (addresses 1fd2 16 to 1fd0 16 ) (sar1) source address register 2 (addresses 1fe2 16 to 1fe0 16 ) (sar2) source address register 3 (addresses 1ff2 16 to 1ff0 16 ) (sar3) transfer counter register 0 (addresses 1fca 16 to 1fc8 16 ) (tcr0) transfer counter register 1 (addresses 1fda 16 to 1fd8 16 ) (tcr1) transfer counter register 2 (addresses 1fea 16 to 1fe8 16 ) (tcr2) transfer counter register 3 (addresses 1ffa 16 to 1ff8 16 ) (tcr3) set the number of transfer blocks. these bits can be set to ?00001 16 ?to ?fffff 16 . notes 1: when writing to these registers, write to all 24 bits. 2: do not write ?00000 16 ?to tcri. dma0 control register (address 1fce 16 ) dma1 control register (address 1fde 16 ) dma2 control register (address 1fee 16 ) dma3 control register (address 1ffe 16 ) 0 0 0 0 : do not select. 0 0 0 1 : external source (dmareqi) 0 0 1 0 : software dma source 0 0 1 1 : timer a0 0 1 0 0 : timer a1 0 1 0 1 : timer a2 0 1 1 0 : timer a3 0 1 1 1 : timer a4 1 0 0 0 : timer b0 1 0 0 1 : timer b1 1 0 1 0 : timer b2 1 0 1 1 : uart0 receive 1 1 0 0 : uart0 transmit 1 1 0 1 : uart1 receive 1 1 1 0 : uart1 transmit 1 1 1 1 : a-d conversion edge sense/level sense select bit (note) 0 : edge sense 1 : level sense dmaacki validity bit 0 : invalid 1 : valid note: when an external source (dmareqi) is selected or when the cycle-steal transfer mode is selected, set this bit to ?.? continue to ?igure 13.7.5 on next page. dma request source select bits fig. 13.7.4 initial setting example for registers relevant to array chain transfer mode (2)
dma controller 13-74 13.7 array chain transfer mode 7721 group users manual aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa dma transfer starts aaaa aaaa aaaa aaaaaaaaaaaa aaaaaaaaaaaa aaaaaaaaaaaa aaaaaaaaaaaa aaaaaaaaaaaa b7 b0 tc pin validity bit 0 : invalid (p10 3 pin functions as a programmable i/o port.) 1 : valid (p10 3 pin functions as tc pin.) b7 b0 00 00 0 : no request aaaaaaaaaaaa aaaaaaaaaaaa aaaaaaaaaaaa aaaaaaaaaaaa aaaaaaaaaaaa aaaaaaaaaaaa aaaaaaaaaaaa b7 b0 aaaaa aaaaa aaaa aaaa when selecting external dma source from preceding ?igure 13.7.4 priority select bit 0 : fixed 1 : rotating dmac control register l (address 68 16 ) dma0 request bit dma1 request bit dma2 request bit dma3 request bit selection of priority level and tc pin, and setting dmai request bit to ?? software dmai request bit (valid in software dma source selected) bit 0 : channel 0 bit 1 : channel 1 bit 2 : channel 2 bit 3 : channel 3 0 : disabled 1 : enabled dmac control register h (address 69 16 ) dma0 enable bit dma1 enable bit dma2 enable bit dma3 enable bit when selecting internal dma source when selecting internal dma source except software inputting dma request signal to dmareqi pin interrupt request of each peripheral function occurs dmac control register h (address 69 16 ) software dma0 request bit software dma1 request bit software dma2 request bit software dma3 request bit 0 : no request 1 : requested when selecting software dma request when writing ?,?dma request is generated. fig. 13.7.5 initial setting example for registers relevant to array chain transfer mode (3)
dma controller 13-75 13.7 array chain transfer mode 7721 group users manual 13.7.3 operation in array chain transfer mode figure 13.7.6 shows the operation flowchart of the array chain transfer mode, and figures 13.7.7 and 13.7.8 show timing diagrams of the array chain transfer mode (burst transfer mode). for the cycle-steal transfer mode, refer to the following: ? transfer of transfer parameters in an array state: figures 13.8.10 and 13.8.11 ? all transfers except in an array state and except the last 1-unit transfer of each block: figure 13.8.12 ? last 1-unit transfer of each block except the last block: figure 13.8.13 ? last 1-unit transfer of the last block: figure 13.8.14 the processing performed in the array chain transfer mode consists of an array state and a transfer state. (1) array state in an array state, transfer parameters are read from the transfer parameter memory in a unit of 2 bytes and transferred to registers sari, dari, and tcri and their latches. as shown in figure 13.7.2, a transfer parameter consists of 4 bytes (24 bits of data + 8 bits of dummy data). one bus cycle always consumes 3 cycles of f . _________ during an array state, the dmaacki pin outputs h level. for the bus request sampling in an array state, refer to section 13.2.1 bus access control circuit. (2) transfer state data is transferred in a transfer state. for the bus request sampling in a transfer state, refer to section 13.2.1 bus access control circuit.
dma controller 13-76 13.7 array chain transfer mode 7721 group users manual fig. 13.7.6 operation flowchart of array chain transfer mode burstlevelh cycle-stealno request note: when tc pin validity bit is 1 first of 1 block ? sari ? transfer parameter (note) (transfer sources transfer start address) dari ? transfer parameter (note) (transfer destinations transfer start address) tcri ? transfer parameter (byte number of transfer data) tcri latch ? tcri latch C 1 n y 1 0 first on and after second transfer completion of all blocks ? tcri latch = 0 ? y. completion 1 n dmai request bit ? 0 1-unit transfer transfer completion of 1 block ? (only in cycle-steal transfer mode) (refer to section 13.4 operation. ) tc l output (note) dmai interrupt request bit ? 1 dmai enable bit ? 0 dmai request bit ? 0 (only in burst transfer mode (edge sense)) dmai request bit ? burstlevelh cycle-stealno request 0 burstedge : in burst transfer mode (edge sense) burstlevell : in burst transfer mode (level sense) with dmareqi pin = l burstlevelh : in burst transfer mode (level sense) with dmareqi pin = h cycle-stealrequested : in cycle-steal transfer mode with any request of dma0C3 cycle-stealno request : in cycle-steal transfer mode wit h no request of dma0C3 sari latch indicates the start address of the transfer param eter memory of the next block. tcri latch indicates the number of remaining transfer blocks . note: the above figure applies when 2-bus cycle transfer is perfor med. when data is transferred from memory to i/o in 1-bus cycle t ransfer, there is no dari ? transfer parameter. when data is transferred from i/o to memory in 1-bus cycle t ransfer, there is no sari ? transfer parameter. burst?edge burstlevell cycle-stealrequested dmai request bit ? burstedge burstlevell cycle-stealrequested
dma controller 13-77 13.7 array chain transfer mode 7721 group users manual fig. 13.7.7 timing diagram of array chain transfer mode (burst transfer mode) (1) transfer of transfer parameters 1-unit transfer 1, 0 (dmac) h h transfer of 1 transfer parameter transfer of data transfer state array state first block transfer memory sa1 da1 m sa2 da2 n tp tp+4 tp+8 tp+12 tp+16 tp+20 first block? transfer parameters sa1 sa1+m? sa1+m sa2+n? sa2+n sa2 pc l tp l (tp+2) l (tp+4) l (tp+6) l (tp+8) l (tp+10) l sa1 l da1 l pc h tp m sa1 m dummy data da1 pg tp h sa1 l sa1 h da1 dummy data da1 h m m m l m h sa1 m data h da1 m data h sa1 h data l da1 h data l h f 1 ale e r/w a 0 ? 7 a 8 /d 8 ? 15 /d 15 a 16 /d 0 ? 23 /d 7 bus request sampling dmaacki tc st1, st0 dummy data transition of right to use bus l this example applies on the following conditions: external data bus width : 16 bits transfer unit : 16 bits transfer method : 2-bus cycle transfer transfer mode : burst transfer source address direction : forward transfer destination address direction : forward transfer source wait : no transfer destination wait : no sa1, sa2, da1, da2 : transfer parameters (even) tp : start address of first block? transfer parameter memory tcr set value : 6 right to use bus : cpu ? dmac ? cpu l the bus request caused by dram refresh or hold is sampled while the bus request sampling signal is ?,?and is accepted. second block? transfer parameters memory second block transfer memory da1 da1+m? da1+m da2+n? da2+n da2 continue to ?igure 13.7.8 on next page. l m (tp+2) m (tp+2) h (tp+4) m (tp+4) h (tp+6) m (tp+6) h (tp+8) m (tp+8) h (tp+10) m (tp+10) h (tp+12) m (tp+12) h (tp+12) l
dma controller 13-78 13.7 array chain transfer mode 7721 group users manual fig. 13.7.8 timing diagram of array chain transfer mode (burst transfer mode) (2) transfer of data transfer state transition of right to use bus terminate processing transfer state array state 1, 0 (dmac) (da1+mC2) l (sa1+m) l (tp+12) l (tp+22) l (tp+24) (da2+nC2) l data h dummy data (sa2+n) l pc l sa2 (sa1+m) m sa2 m data h data h (sa2+n) m pc h data l n h (sa1+m) h sa2 l data l data l (sa2+n) h pg 1, 1 (cpu) from proceeding figure 13.7.7 f 1 ale e r/w a 0 Ca 7 a 8 /d 8 Ca 15 /d 15 a 16 /d 0 Ca 23 /d 7 bus request sampling dmaacki tc st1, st0 l l (tp+12) m (tp+12) h (tp+24) m (tp+24) h sa2 m sa2 h
dma controller 13-79 13.7 array chain transfer mode 7721 group users manual [precautions for array chain transfer mode] if the following two conditions are satisfied when the transfer unit is 16 bits and the address direction of transfer source or destination is fixed, the array chain transfer mode can be used: ? the external data bus width = 16 bits or the internal memory is used. ? the transfer start address on the address-direction-fixed side is an even address.
dma controller 13-80 13.8 link array chain transfer mode 7721 group users manual 13.8 link array chain transfer mode this mode is used to transfer several blocks of data. according to the information of each block stored in memory area (note) , several blocks of data are transferred. transfer parameters can be located in separate memory locations, in a unit of one blocks parameters. table 13.8.1 lists the specifications of the link array chain transfer mode, and figure 13.8.1 shows the register structures of sari, dari, and tcri in this mode. note: each of the following information is called transfer parameter: transfer start addresses of transfer source and destination, and transfer datas byte number. table 13.8.1 specifications of link array chain transfer mode item transfer parameter memory condition of normal termination conditions of forced termination interrupt request generation timing functions of registers performance specifications required. l in 2-bus cycle transfer: 16 bytes per one block (transfer sources transfer start address, transfer destinations transfer start address, transfer datas byte number, next transfer parameter memorys start address) l in 1-bus cycle transfer: 12 bytes per one block (from memory to i/o: transfer sources transfer start address, transfer datas byte number, next transfer parameter memorys start address) (from i/o to memory: transfer destinations transfer start address, transfer datas byte number, next transfer parameter memorys start address) sari latch = 0 and tcri = 0 ___ l falling edge of tc pins input from h to l ___ (when the tc pin validity bit = 1) l write 0 to the dmai enable bit at normal termination sari latch: indicates the transfer parameter memorys start address of the next block. sari: indicates the address of the next transfer source. dari latch: not used. dari: indicates the address of the next transfer destination. tcri latch: not used. tcri: indicates the number of remaining bytes being transferred. ___ tc pin validity bit: bit 1 at address 68 16
dma controller 13.8 link array chain transfer mode 13-81 7721 group users manual b7 b0 b15 b8 source address register 0 (addresses 1fc2 16 to 1fc0 16 ) (sar0) source address register 1 (addresses 1fd2 16 to 1fd0 16 ) (sar1) source address register 2 (addresses 1fe2 16 to 1fe0 16 ) (sar2) source address register 3 (addresses 1ff2 16 to 1ff0 16 ) (sar3) functions bit at reset rw 23 to 0 [write] set the start address of transfer parameter memory of block which is first transferred. these bits can be set to 000000 16 to ffffff 16 . [read] ? after a value is written to this register and until transfer starts, the read value indicates the written value (the start address of the transfer parameter memory of block which is first transferred). ? after transfer starts, the read value indicates the source address of data which is next transferred. undefined rw note: when writing to this register, write to all 24 bits. b23 b16 b7 b0 b15 b8 destination address register 0 (addresses 1fc6 16 to 1fc4 16 ) (dar0) destination address register 1 (addresses 1fd6 16 to 1fd4 16 ) (dar1) destination address register 2 (addresses 1fe6 16 to 1fe4 16 ) (dar2) destination address register 3 (addresses 1ff6 16 to 1ff4 16 ) (dar3) functions bit at reset rw 23 to 0 need not to be set. [read] after transfer starts, the read value indicates the destination address of data which is next transferred. undefined rw b23 b16 b7 b0 b15 b8 transfer counter register 0 (addresses 1fca 16 to 1fc8 16 ) (tcr0) transfer counter register 1 (addresses 1fda 16 to 1fd8 16 ) (tcr1) transfer counter register 2 (addresses 1fea 16 to 1fe8 16 ) (tcr2) transfer counter register 3 (addresses 1ffa 16 to 1ff8 16 ) (tcr3) functions bit at reset rw 23 to 0 [write] set the dummy data. these bits can be set to 000001 16 to ffffff 16 . [read] ? after a value is written to this register and until transfer starts, the read value indicates the written value (dummy data). ? after transfer starts, the read value indicates the remaining byte number of the block which is being transferred. undefined rw note: when writing to this register, write to all 24 bits. do not write 000000 16 to this register. b23 b16 fig. 13.8.1 register structures of sari, dari, and tcri in link array chain transfer mode
dma controller 13-82 13.8 link array chain transfer mode 7721 group users manual 13.8.1 transfer parameter memory in link array chain transfer mode the transfer parameters required for each transfer method are described below. these parameters can be located in separate memory locations, in a unit of one blocks parameters. however, these parameters must be located starting at an even address. figure 13.8.2 shows a transfer parameter memory map in the link array chain transfer mode. (1) in 2-bus cycle transfer all of the following transfer parameters are required for each block of data; that is, a transfer parameter memory consumes 16 bytes for each block. ? transfer sources transfer start address (24 bits) + dummy data (8 bits) ? transfer destinations transfer start address (24 bits) + dummy data (8 bits) ? transfer datas byte number (24 bits) + dummy data (8 bits) ? start address of next transfer parameter memory (24 bits) (note) + dummy data (8 bits) (2) in 1-bus cycle transfer from memory to i/o all of the following transfer parameters are required for each block of data; that is, a transfer parameter memory consumes 12 bytes for each block. ? transfer sources transfer start address (24 bits) + dummy data (8 bits) ? transfer datas byte number (24 bits) + dummy data (8 bits) ? start address of next transfer parameter memory (24 bits) (note) + dummy data (8 bits) (3) in 1-bus cycle transfer from i/o to memory all of the following transfer parameters are required for each block of data; that is, a transfer parameter memory consumes 12 bytes for each block. ? transfer destinations transfer start address (24 bits) + dummy data (8 bits) ? transfer datas byte number (24 bits) + dummy data (8 bits) ? start address of next transfer parameter memory (24 bits) (note) + dummy data (8 bits) note: for the last block of data, write 000000 16 as the start address of the next transfer parameter memory.
dma controller 13.8 link array chain transfer mode 13-83 7721 group users manual fig. 13.8.2 transfer parameter memory map in link array chain transfer mode ] the above applies on the following conditions: ?hen data is transferred from memory to i/o (when transferring from i/o to memory, replace all the above mentioned ?ransfer source? transfer start address?with ?ransfer destination? transfer start address. ?-block transfer ] the above figure applies when 4-block transfer is performed. dummy data transfer parameter address 1 (1) 2-bus cycle transfer (2) 1-bus cycle transfer 4 bytes transfer source? transfer start address 1 transfer destination? transfer start address 1 transfer data? byte number 1 next transfer parameter memory? start address 2 transfer source? transfer start address 4 transfer destination? transfer start address 4 transfer data? byte number 4 ?00000 16 transfer source? transfer start address 3 transfer destination? transfer start address 3 transfer data? byte number 3 next transfer parameter memory? start address 4 transfer source? transfer start address 2 transfer destination? transfer start address 2 transfer data? byte number 2 next transfer parameter memory? start address 3 transfer parameter address 4 (last block) transfer parameter address 3 transfer parameter address 2 dummy data transfer data? byte number transfer source? transfer start address l m h l m h l m h l m h even address transfer parameters for 1 block dummy data dummy data even address even address even address transfer destination? transfer start address next transfer parameter memory? start address 4 bytes transfer source? transfer start address 1 transfer data? byte number 1 next transfer parameter memory? start address 2 transfer source? transfer start address 3 transfer data? byte number 3 next transfer parameter memory? start address 4 transfer source? transfer start address 2 transfer data? byte number 2 next transfer parameter memory? start address 3 transfer source? transfer start address 4 transfer data? byte number 4 ?00000 16 transfer parameter address 1 transfer parameter address 3 transfer parameter address 2 transfer parameter address 4 (last block) dummy data transfer data? byte number transfer source? transfer start address l m h l m h l m h even address transfer parameters for 1 block dummy data dummy data even address even address next transfer parameter memory? start address
dma controller 13-84 13.8 link array chain transfer mode 7721 group users manual 13.8.2 setting of link array chain transfer mode figures 13.8.3 through 13.8.5 show an initial setting example for registers relevant to the link array chain transfer mode. in addition, when timer a, timer b, uart, or the a-d converter is selected as a dma request source, the setting for the peripheral is required. for details of the setting, refer to the chapter of each peripheral function. when a dmai interrupt is used, the setting for enabling the interrupt is also required. for details, refer to chapter 7. interrupts. fig. 13.8.3 initial setting example for registers relevant to link array chain transfer mode (1) when external dma source is selected when internal dma source is selected aaaaaaaaaaaaa aaaaaaaaaaaaa aaaaaaaaaaaaa aaaaaaaaaaaaa aaaaaaaaaaaaa setting interrupt priority level b7 b0 dmai interrupt control register (i = 0 to 3) (addresses 6c 16 to 6f 16 ) interrupt priority level select bits when using interrupts, set these bits to one of levels 1 to 7. when disabling interrupts, set these bits to level 0. continue to ?igure 13.8.4 on next page. aaaaaaaaaaaa aaaaaaaaaaaa aaaaaaaaaaaa aaaaaaaaaaaa aaaaaaaaaaaa aaaaaaaaaaaa b7 b0 port p9 direction register (address 15 16 ) setting port p9 direction register dmareq0 pin dmareq1 pin dmareq2 pin clear the corresponding bit to ?. dmareq3 pin
dma controller 13.8 link array chain transfer mode 13-85 7721 group users manual b7 b0 selection of transfer mode and each function b7 b0 0 b7 b0 0 0 1 1 from preceding figure 13.8.3 b7 b0 b0 b0 b7 b7 (b23) (b8) (b16)(b15) b7 b0 b0 b0 b7 b7 (b23) (b8) (b16)(b15) dma0 mode register l (address 1fcc 16 ) dma1 mode register l (address 1fdc 16 ) dma2 mode register l (address 1fec 16 ) dma3 mode register l (address 1ffc 16 ) number-of-unit-transfer-bits select bit 0 : 16 bits 1 : 8 bits transfer method select bit 0 : 2-bus cycle transfer 1 : 1-bus cycle transfer transfer mode select bit 0 : burst transfer mode 1 : cycle-steal transfer mode transfer source address direction select bits 0 0 : fixed 0 1 : forward 1 0 : backward 1 1 : do not select. transfer destination address direction select bits 0 0 : fixed 0 1 : forward 1 0 : backward 1 1 : do not select. dma0 mode register h (address 1fcd 16 ) dma1 mode register h (address 1fdd 16 ) dma2 mode register h (address 1fed 16 ) dma3 mode register h (address 1ffd 16 ) transfer direction select bit (used in 1-bus cycle transfer) 0 : from memory to i/o 1 : from i/o to memory i/o connection select bit (valid in 1-bus cycle transfer) 0 : data bus d 0 Cd 7 or d 0 Cd 15 1 : data bus d 8 Cd 15 transfer source wait bit (valid in dma transfer) 0 : wait 1 : no wait transfer destination wait bit (valid in dma transfer) 0 : wait 1 : no wait selection of link array chain transfer mode source address register 0 (addresses 1fc2 16 to 1fc0 16 ) (sar0) source address register 1 (addresses 1fd2 16 to 1fd0 16 ) (sar1) source address register 2 (addresses 1fe2 16 to 1fe0 16 ) (sar2) source address register 3 (addresses 1ff2 16 to 1ff0 16 ) (sar3) transfer counter register 0 (addresses 1fca 16 to 1fc8 16 ) (tcr0) transfer counter register 1 (addresses 1fda 16 to 1fd8 16 ) (tcr1) transfer counter register 2 (addresses 1fea 16 to 1fe8 16 ) (tcr2) transfer counter register 3 (addresses 1ffa 16 to 1ff8 16 ) (tcr3) notes 1: when writing to these registers, write to all 24 bits. 2: do not write 000000 16 to tcri. dma0 control register (address 1fce 16 ) dma1 control register (address 1fde 16 ) dma2 control register (address 1fee 16 ) dma3 control register (address 1ffe 16 ) 0 0 0 0 : do not select. 0 0 0 1 : external source (dmareqi) 0 0 1 0 : software dma source 0 0 1 1 : timer a0 0 1 0 0 : timer a1 0 1 0 1 : timer a2 0 1 1 0 : timer a3 0 1 1 1 : timer a4 1 0 0 0 : timer b0 1 0 0 1 : timer b1 1 0 1 0 : timer b2 1 0 1 1 : uart0 receive 1 1 0 0 : uart0 transmit 1 1 0 1 : uart1 receive 1 1 1 0 : uart1 transmit 1 1 1 1 : a-d conversion edge sense/level sense select bit (note) 0 : edge sense 1 : level sense dmaacki validity bit 0 : invalid 1 : valid note: when an external source (dmareqi) is selected or when the cycle steal transfer mode is selected, set this bit to 0. continue to figure 13.8.5 on next page. dma request source select bits set the start address of transfer parameter memory of block which is first transferred. these bits can be set to 000000 16 to ffffff 16 . set the dummy data. these bits can be set to 000001 16 to ffffff 16 . fig. 13.8.4 initial setting example for registers relevant to link array chain transfer mode (2)
dma controller 13-86 13.8 link array chain transfer mode 7721 group users manual fig. 13.8.5 initial setting example for registers relevant to link array chain transfer mode (3) dma transfer starts aaa aaa aaa aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa b7 b0 aaaaaaaaaaaaaa aaaaaaaaaaaaaa aaaaaaaaaaaaaa aaaaaaaaaaaaaa aaaaaaaaaaaaaa aaaaaaaaaaaaaa aaaaaaaaaaaaaa aaaaaaaaaaaaaa selection of priority level and tc pin, and setting dmai request bit to ?? tc pin validity bit 0 : invalid (p10 3 pin functions as a programmable i/o port.) 1 : valid (p10 3 pin functions as tc pin.) b7 b0 00 00 0 : no request aaaaaaaaaaaa aaaaaaaaaaaa aaaaaaaaaaaa aaaaaaaaaaaa aaaaaaaaaaaa aaaaaaaaaaaa b7 b0 aaaaa aaaaa inputting dma request signal to dmareqi pin aaaa aaaa when selecting external dma source from preceding ?igure 13.8.4 priority select bit 0 : fixed 1 : rotating dmac control register l (address 68 16 ) dma0 request bit dma1 request bit dma2 request bit dma3 request bit software dmai request bit (valid in software dma source selected) bit 0 : channel 0 bit 1 : channel 1 bit 2 : channel 2 bit 3 : channel 3 0 : disabled 1 : enabled dmac control register h (address 69 16 ) dma0 enable bit dma1 enable bit dma2 enable bit dma3 enable bit when selecting internal dma source when selecting internal dma source except software interrupt request of each peripheral function occurs dmac control register h (address 69 16 ) software dma0 request bit software dma1 request bit software dma2 request bit software dma3 request bit 0 : no request 1 : requested when selecting software dma request when writing ?,?dma request is generated.
dma controller 13.8 link array chain transfer mode 13-87 7721 group users manual 13.8.3 operation in link array chain transfer mode figure 13.8.6 shows the operation flowchart of the link array chain transfer mode, and figures 13.8.7 and 13.8.8 show timing diagrams of the link array chain transfer mode (burst transfer mode). in addition, figure 13.8.9 shows the conditions necessary for timings shown in figures 13.8.7, 13.8.8, and 13.8.10 through 13.8.14. for the cycle-steal transfer mode, refer to the following: ? transfer of transfer parameters in an array state: figures 13.8.10 and 13.8.11 ? all transfers except for that in an array state and except for the last 1-unit transfer of each block: figure 13.8.12 ? last 1-unit transfer of each block except for the last block: figure 13.8.13 ? last 1-unit transfer of the last block: figure 13.8.14 the processing performed in the link array chain transfer mode consists of an array state and a transfer state. (1) array state in an array state, transfer parameters are read from the transfer parameter memory in a unit of 2 bytes and transferred to registers sari, dari, and tcri and their latches. as shown in figure 13.8.2, a transfer parameter consists of 4 bytes (24 bits of data + 8 bits of dummy data). one bus cycle always consumes 3 cycles of f . _________ during an array state, the dmaacki pin outputs h level. for the bus request sampling in an array state, refer to section 13.2.1 bus access control circuit. (2) transfer state data is transferred in a transfer state. for the bus request sampling in a transfer state, refer to section 13.2.1 bus access control circuit.
dma controller 13-88 13.8 link array chain transfer mode 7721 group users manual note: when tc pin validity bit is ? first of each block ? sari ? transfer parameter (note) (transfer source? transfer start address) dari ? transfer parameter (note) (transfer destination? transfer start address) tcri ? transfer parameter (byte number of transfer data) sari latch ? transfer parameter (start address of next transfer parameter memory) n y 1 0 first on and after second transfer completion of all blocks ? sari latch = 0 ? y. completion 1 tc ??output (note) dmai interrupt request bit ? 1 dmai enable bit ? 0 n dmai request bit ? 0 1-unit transfer transfer completion of 1 block ? (only in cycle-steal transfer mode) (refer to section ?3.4 operation. ) dmai request bit ? 0 (only in burst transfer mode (edge sense)) dmai request bit ? burst?evel? cycle-steal?o request 0 burst?dge : in burst transfer mode (edge sense) burst?evel? : in burst transfer mode (level sense) with dmareqi pin? input level = l burst?evel? : in burst transfer mode (level sense) with dmareqi pin? input level = h cycle-steal?equested : in cycle-steal transfer mode with any request of dma0? cycle-steal?o request : in cycle-steal transfer mode with no request of dma0? sari latch indicates the start address of the transfer parameter memory of the next block. note: the above figure applies when 2-bus cycle transfer is performed. when data is transferred from memory to i/o in 1-bus cycle transfer, there is no ?ari ? transfer parameter. when data is transferred from i/o to memory in 1-bus cycle transfer, there is no ?ari ? transfer parameter. burst?dge burst?evel? cycle-steal?equested burst?evel? cycle-steal?o request dmai request bit ? burst?dge burst?evel? cycle-steal?equested fig. 13.8.6 operation flowchart of link array chain transfer mode
dma controller 13.8 link array chain transfer mode 13-89 7721 group users manual fig. 13.8.7 timing diagram of link array chain transfer mode (burst transfer mode) (1) f 1 ale e r/w a 0 ? 7 a 8 /d 8 ? 15 /d 15 a 16 /d 0 ? 23 /d 7 bus request sampling dmaacki tc st1, st0 array state transfer of transfer parameters pc l tp1 l (tp1+2) l (tp1+4) l (tp1+6) l (tp1+8) l pc h tp1 m sa1 m dummy data da1 pg tp1 h sa1 l sa1 h da1 h h h (tp1+10) l dummy data m m m l m h tp2 m tp2 l (tp1+12) l 1, 0 (dmac) continue to ?igure 13.8.8. (tp1+14) l dummy data tp2 h transfer of 1 transfer parameter transition of right to use bus l the bus request caused by dram refresh or hold is sampled while the bus request sampling signal is ?,?and is accepted. dummy data l m (tp1+2) m (tp1+2) h (tp1+4) m (tp1+4) h (tp1+6) m (tp1+6) h (tp1+8) m (tp1+8) h (tp1+10) m (tp1+10) h (tp1+12) m (tp1+12) h (tp1+14) m (tp1+14) h da1 h
dma controller 13-90 13.8 link array chain transfer mode 7721 group users manual fig. 13.8.8 timing diagram of link array chain transfer mode (burst transfer mode) (2) transfer state transfer of data tp2 l sa1 l (da1+m-2) l (sa1+m) l tp2 l tp2 m tp2 h sa1 h 1,0 (dmac) (tp2+14) l sa2 m 00 16 dummy data sa2 h sa2 m sa2 h 1-unit transfer sa2 l array state array state transfer state terminate processing transition of right to use bus sa1 m da1 l (sa1+m) m (sa1+m) h 00 16 00 16 00 16 (da2+n?) l (sa2+n) l (sa2+n) m (sa2+n) h pc l pc h pg 1, 1 (cpu) f 1 ale e r/w a 0 ? 7 a 8 /d 8 ? 15 /d 15 a 16 /d 0 ? 23 /d 7 bus request sampling dmaacki tc st1, st0 from preceding figure 13.8.7 data h data l data h data l data h data l data h data l data h data l da1 m da1 h tp2 m tp2 h
dma controller 13.8 link array chain transfer mode 13-91 7721 group users manual figure 13.8.9 shows the conditions necessary for timings shown in figures 13.8.7, 13.8.8, and 13.8.10 through 13.8.14. fig. 13.8.9 conditions necessary for timings shown in figures 13.8.7, 13.8.8, and 13.8.10 through 13.8.14 memory sa1 da1 m tp2 sa2 da2 n 000000 16 tp1 tp1+4 tp1+8 tp1+12 tp2 tp2+4 tp2+8 tp2+12 external data bus width : 16 bits transfer unit : 16 bits transfer method : 2-bus cycle transfer transfer mode : burst ( ?igure 13.8.7 and ?igure 13.8.8 ) : cycle-steal ( ?igure 13.8.10 through ?igure 13.8.14 ) transfer source address direction : forward transfer destination address direction : forward transfer source wait : no transfer destination wait : no sa1, sa2, da1, da2 : transfer parameter (even) tp1 : start address of first block? transfer parameter memory transfer block? number : 2 right to use bus : cpu ? dmac ? cpu memory first block transfer first block? transfer parameter sa1 sa1+m? sa1+m sa2+n? sa2+n sa2 second block? transfer parameter second block transfer memory da1 da1+m? da1+m da2+n? da2+n da2
dma controller 13-92 13.8 link array chain transfer mode 7721 group users manual transfer of transfer parameters transition of right to use bus 1 ale e r/w a 0 Ca 7 a 8 /d 8 Ca 15 /d 15 a 16 /d 0 Ca 23 /d 7 bus request sampling dmaacki tc st1, st0 pc l tp1 l (tp1+2) l (tp1+4) l (tp1+6) l (tp1+8) l pc h tp1 m sa1 m (tp1+2) m dummy data (tp1+4) m da1 m (tp1+6) m pg tp1 h sa1 l (tp1+2) h sa1 h (tp1+4) h da1 l (tp1+6) h h h h dummy data da1 h (tp1+8) m (tp1+8) h m m m l array state l the above figure is the example of initial term for processing the first block in figure 13.8.9. l the bus request caused by dram refresh or hold is sampled while the bus request sampling signal is 1, and is accepted. l the bus request caused by dma is sampled while the bus request sampling signal ( ] 1) is 1 in the transition of the right to use bus, and is accepted. the dma requests of the other channels are not accepted in an array state. continue to figure 13.8.11. ] 1 l initial term for processing each block in array chain and link array chain transfer modes the operation from an array state to the first 1-unit transfer is continuously performed by one dmai request. 1, 0 (dmac) fig. 13.8.10 timing diagram of cycle-steal transfer mode (1)
dma controller 13.8 link array chain transfer mode 13-93 7721 group users manual transfer of transfer parameters array state (tp1+14) l tp2 h sa1 l (tp1+14) m dummy data tp2 m data h da1 m (tp1+14) h tp2 h tp2 l data l sa1 h da1 h 1, 0 (dmac) first 1-unit transfer ] 2 transition of right to use bus sa1 m da1 l data h data l pc l pc h pg 1, 1 (cpu) h (tp1+12) l (tp1+10) l (tp1+12) m tp2 m (tp1+10) m dummy data (tp1+12) h tp2 l (tp1+10) h m h ] 1 from preceding figure 13.8.10 1 ale e r/w a 0 Ca 7 a 8 /d 8 Ca 15 /d 15 a 16 /d 0 Ca 23 /d 7 bus request sampling dmaacki tc st1, st0 l the above figure is the example of initial term for processing the first block in figure 13.8.9. when the array chain transfer mode is selected, there is not the term of ] 2. l the bus request caused by dram refresh or hold is sampled while the bus request sampling signal is 1, and is accepted. l the bus request caused by dma is sampled while the bus request sampling signal ( ] 1) is 1 in transition of the right to use bus, and is accepted. the dma requests of the other channels are not accepted in an array state. fig. 13.8.11 timing diagram of cycle-steal transfer mode (2)
dma controller 13-94 13.8 link array chain transfer mode 7721 group users manual fig. 13.8.12 timing diagram of cycle-steal transfer mode (3) (sa1+2) l 1, 0 (dmac) 1-unit transfer transition of right to use bus data h data l pc l pc h pg h pc l pc h pg (da1+2) l data h data l (sa1+2) m (sa1+2) h (da1+2) m (da1+2) h 1, 1 (cpu) l 1-unit transfer 1-unit transfer is performed with a dmai request on the following conditions: ? single transfer mode (except for the last 1-unit transfer) ? repeat transfer mode (except for the last 1-unit transfer of block) ? array chain transfer mode (except for the first and last 1-unit transfers of each block) ? link array chain transfer mode (except for the first and last 1-unit transfers of each block) 1 ale e r/w a 0 Ca 7 a 8 /d 8 Ca 15 /d 15 a 16 /d 0 Ca 23 /d 7 bus request sampling dmaacki tc st1, st0 transition of right to use bus l the above figure is the example of the second 1-unit transfer for processing the first block in figure 13.8.9. l the bus request caused by dram refresh, hold, or dma is sampled while the bus request sampling signal is h, and is accepted.
dma controller 13.8 link array chain transfer mode 13-95 7721 group users manual fig. 13.8.13 timing diagram of cycle-steal transfer mode (4) (sa1+mC2) l 1, 0 (dmac) 1-unit transfer h data l pc l pc h pg h pc l pc h pg (da1+mC2) l data h l (sa1+m-2) m (sa1+m-2) h (da1+m-2) m (da1+m-2) h 1, 1 (cpu) transition of right to use bus (sa1+m) l (sa1+m) m (sa1+m) h 1 ale e r/w a 0 Ca 7 a 8 /d 8 Ca 15 /d 15 a 16 /d 0 Ca 23 /d 7 bus request sampling dmaacki tc st1, st0 l the above figure is the example of the last term for processing the first block in figure 13.8.9. l the bus request caused by dram refresh, hold, or dma is sampled while the bus request sampling signal is h, and is accepted. transition of right to use bus l last transfer of each block at the last term (except for the last block) for processing of each block in the repeat, array chain, and link array chain transfer modes, 1-unit transfer is performed with one dmai request, and the right to use bus is relinquished after 3 cycles of . data data
dma controller 13-96 13.8 link array chain transfer mode 7721 group users manual 1 ale e r/w a 0 Ca 7 a 8 /d 8 Ca 15 /d 15 a 16 /d 0 Ca 23 /d 7 bus request sampling dmaacki tc st1, st0 (sa2+n-2) l 1, 0 (dmac) 1-unit transfer h data l pc l pc h pg h pc l pc h pg (da2+n-2) l data h l (sa2+n-2) m (sa2+n-2) h (da2+n-2) m (da2+n-2) h 1, 1 (cpu) (sa2+n) l (sa2+n) m (sa2+n) h terminate processing l last transfer of last block at the last term for processing the last block in the single, array chain, and link array chain transfer modes, 1-unit transfer and terminate processing are subsequently performed with one dmai request. transition of right to use bus l the above figure is the example of the last term for processing the second block in figure 13.8.9. l the bus request caused by dram refresh, hold, or dma is sampled while the bus request sampling signal is h, and is accepted. transition of right to use bus fig. 13.8.14 timing diagram of cycle-steal transfer mode (5) data data
dma controller 13.8 link array chain transfer mode 13-97 7721 group users manual [precautions for link array chain transfer mode] if the following two conditions are satisfied when the transfer unit is 16 bits and the address direction of transfer source or destination is fixed, the link array chain transfer mode can be used: ? the external data bus width = 16 bits or the internal memory is used. ? the transfer start address on the address-direction-fixed side is an even address.
dma controller 13-98 13.9 dma transfer time 7721 group users manual 13.9 dma transfer time calculation of time from the cpus relinquishing the right to use bus until its regaining the right under the following conditions is described with reference to cycles of f : ? a dmai request is generated while the cpu holds the right to use bus. ? the above right is returned to the cpu after completion of dma transfer for one dma request. for the time per 1-unit transfer, refer to section 13.4.1 (2) bus operation in 2-bus cycle transfer and section 13.4.2 (2) bus operation in 1-bus cycle transfer. also, for the time from dma request generation until the start of the dma transfer, refer to section 13.3.4 processing from dma request until dma transfer execution: and for that from issuing instructions for forced termination until returning the right to use bus to the cpu, refer to section 13.3.5 (2) forced termination. 13.9.1 cycle-steal transfer mode (1) 1-unit transfer in the following cases, 1-unit transfer is performed at one dmai transfer. (refer to figure 13.8.12. ) ? single transfer mode: except for the last 1-unit transfer ? repeat transfer mode: except for the last 1-unit transfer of a block ? array chain transfer mode: except for the first and last 1-unit transfers of each block ? link array chain transfer mode: except for the first and last 1-unit transfers of each block right to use bus transfer cpu dmac cpu a transition transition fig. 13.9.1 1-unit transfer transition of the right to use bus from cpu to dmac: 1 cycle dma transfer per 1-transfer unit: ? in 2-bus cycle transferread cycle + write cycle (add a value which satisfies the read/write conditions. refer to table 13.4.1. ) ? in 1-bus cycle transferrefer to table 13.4.5. a transition of the right to use bus from dmac to cpu: 1 cycle [example] 2-bus cycle transfer, transfer unit =16 bits, external data bus width = 16 bits, and under the following conditions: ? transfer source: address direction = forward, start address of data = even, with wait ? transfer destination: address direction = backward, start address of data = even, without wait + + a = 1 + (3 + 4) + 1 = 9 cycles
7721 group users manual 13-99 dma controller 13.9 dma transfer time (2) last transfer of each block in the following cases, 1-unit transfer and the processing for 3 cycles are performed sequentially. (refer to figures 13.8.13 and 13.8.14. ) ? single transfer mode: the last 1-unit transfer ? repeat transfer mode: the last 1-unit transfer of a block ? array chain transfer mode: the last 1-unit transfer of each block (including the last block) ? link array chain transfer mode: the last 1-unit transfer of each block (including the last block) termination etc. right to use bus cpu dmac cpu transfer transition a ? transition fig. 13.9.2 last transfer of each block transition of the right to use bus from cpu to dmac: 1 cycle dma transfer per 1-unit transfer: ? in 2-bus cycle transferread cycle + write cycle (add a value which satisfies the read/write conditions. refer to table 13.4.1. ) ? in 1-bus cycle transferrefer to table 13.4.5. a terminate processing or the last processing of each block: 3 cycles ? transition of the right to use bus from dmac to cpu: 1 cycle [example] 2-bus cycle transfer, transfer unit =16 bits, external data bus width = 16 bits, and under the following conditions: ? transfer source: address direction = forward, start address of data = even, with wait ? transfer destination: address direction = backward, start address of data = even, without wait + + a + ? = 1 + (3 + 4) + 3 + 1 = 12 cycles
dma controller 13-100 13.9 dma transfer time 7721 group users manual (3) transfer of array state in the following cases, the processing in an array state and the first 1-unit transfer are performed sequentially. (refer to figures 13.8.10 and 13.8.11. ) ? array chain transfer mode: the first transfer of each block ? link array chain transfer mode: the first transfer of each block right to use bus array state cpu dmac cpu transfer a transition ? transition fig. 13.9.3 transfer of array state transition of the right to use bus from cpu to dmac: 1 cycle array state: the number of transfer parameters the number of reads of a transfer parameter the number of bus cycles for a read + 1 cycle (refer to table 13.9.1. ) a dma transfer per 1-unit transfer: ? in 2-bus cycle transferread cycle + write cycle (add a value which satisfies the read/write conditions. refer to table 13.4.1. ) ? in 1-bus cycle transferrefer to table 13.4.5. ? transition of the right to use bus from dmac to cpu: 1 cycle [example] link array chain transfer mode, external data bus width = 16 bits, 2-bus cycle transfer, transfer unit =16 bits, and under the following conditions: ? transfer source: address direction = forward, start address of data = even, with wait ? transfer destination: address direction = backward, start address of data =odd, with wait + + a + ? = 1 + 25 + (3 + 4) + 1 = 34 cycles table 13.9.1 time required for processing in array state external data bus width mode transfer method array chain transfer mode 16 bits (including internal bus) 8 bits 8 bits 16 bits (including internal bus) link array chain transfer mode 2-bus cycle transfer 1-bus cycle transfer 2-bus cycle transfer 1-bus cycle transfer 2-bus cycle transfer 1-bus cycle transfer 2-bus cycle transfer 3 2 3 2 4 3 4 3 1-bus cycle transfer 2 2 4 4 2 2 4 4 3 2 3 + 1 = 19 2 2 3 + 1 = 13 3 4 3 + 1 = 37 2 4 3 + 1 = 25 4 2 3 + 1 = 25 3 2 3 + 1 = 19 4 4 3 + 1 = 49 3 4 3 + 1 = 37 time required for processing in array state (unit: f cycle) number of reads of a transfer parameter number of transfer parameters
7721 group users manual 13-101 dma controller 13.9 dma transfer time 13.9.2 burst transfer mode (1) single transfer mode right to use bus cpu dmac cpu transfer ? transition transition termination a fig. 13.9.4 single transfer mode (burst transfer mode selected) transition of the right to use bus from cpu to dmac: 1 cycle dma transfer per an entire batch of data: ? in 2-bus cycle transfer(read cycle + write cycle h 1 ) the number of transfers h 2 h 1: add a value which satisfies the read/write conditions. refer to table 13.4.1. h 2: when the transfer unit is 16 bits, the number of transfers = the number of transfer bytes/2 when the transfer unit is 8 bits, the number of transfers = the number of transfer bytes ? in 1-bus cycle transferrefer to table 13.4.5. a terminate processing: 3 cycles ? transition of the right to use bus from dmac to cpu: 1 cycle [example] external data bus width = 16 bits, 2-bus cycle transfer, transfer unit =16 bits, the number of the transfer bytes = 10 bytes, and under the following conditions: ? transfer source: address direction = forward, start address of data = even, with wait ? transfer destination: address direction = backward, start address of data = even, without wait + + a + ? = 1 + 5 (3 + 4) + (3 + 1) = 40 cycles
dma controller 13-102 13.9 dma transfer time 7721 group users manual (2) repeat transfer mode in the repeat transfer mode of burst transfer (edge sense), the method of terminating dma transfer ___ is only the forced termination by the tc input. therefore, the time from the cpus relinquishing the ___ right to use bus until regaining the right depends on the timing of the tc input. transfer right to use bus cpu dmac cpu a tc input 1 block transfer a transfer ? a transition ? transition fig. 13.9.5 repeat transfer mode (burst transfer mode and edge sense selected) transition of the right to use bus from cpu to dmac: 1 cycle dma transfer per 1 block: ? in 2-bus cycle transfer(read cycle + write cycle h 1 ) the number of transfers h 2 h 1: add a value which satisfies the read/write conditions. refer to table 13.4.1. h 2: when the transfer unit is 16 bits, the number of transfers = the number of transfer bytes/2 when the transfer unit is 8 bits, the number of transfers = the number of transfer bytes ? in 1-bus cycle transferrefer to table 13.4.5. a terminate processing: 3 cycles ___ ? dma transfer of the block at the tc input: above the number of transfers is assumed to be up to the dma transfer of 1-unit transfer which was in ___ progress at the tc input. ? transition of the right to use bus from dmac to cpu: 1 cycle [example] external data bus width = 16 bits, 2-bus cycle transfer, transfer unit =16 bits, the number of the transfer bytes = 10 bytes, and under the following conditions: ? transfer source: address direction = forward, start address of data = even, with wait ? transfer destination: address direction = backward, start address of data = even, without wait ___ ? tc is input when the mth byte (m = even) of the nth block is in transfer. + (n C 1) ( + a ) + ? + ? = 1 + (n C 1){5(3 + 4) + 3} + m/2 + 1 = 38n + m/2 C 36 cycles
7721 group users manual 13-103 dma controller 13.9 dma transfer time a cpu dmac cpu right to use bus 1 block array state transfer ? array state transfer ? ? transition termination a a transition (3) array chain transfer mode and link array chain transfer mode fig 13.9.6 array chain transfer mode and link array chain transfer mode transition of the right to use bus from cpu to dmac: 1 cycle array state: the number of transfer parameters the number of reads of a transfer parameter the number of bus cycles for a read + 1 cycle (refer to table 13.9.1. ) a dma transfer per an entire batch of data: ? in 2-bus cycle transfer(read cycle + write cycle h 1 ) the number of transfers h 2 h 1: add a value which satisfies the read/write conditions. refer to table 13.4.1. h 2: when the transfer unit is 16 bits, the number of transfers = the number of transfer bytes/2 when the transfer unit is 8 bits, the number of transfers = the number of transfer bytes ? in 1-bus cycle transferrefer to table 13.4.5. ? last processing of each block: 3 cycles ? terminate processing: 3 cycles ? transition of the right to use bus from dmac to cpu: 1 cycle [example] array chain transfer mode, external data bus width = 16 bits, 2-bus cycle transfer, transfer unit =16 bits, the number of transfer blocks = 3, and under the following conditions: ? transfer source: address direction = forward, without wait ? transfer destination: address direction = backward, without wait ? first block: transfer sources data start address = even, transfer destinations data start address = even, the number of transfer bytes =10 bytes ? second block: transfer sources data start address = even, transfer destinations data start address =odd, the number of transfer bytes =12 bytes ? third block: transfer sources data start address =odd, transfer destinations data start address =odd, the number of transfer bytes =14 bytes + + a + ? + + a + ? + + a + ? + ? = 1 + 19 + 5(2 + 4) + 3 + 19 + 6(2 + 3) + 3 + 19 + 7(4 + 3) + 3 + 1 = 177 cycles
dma controller 13-104 13.9 dma transfer time 7721 group users manual memorandum
chapter 14 dram controller 14.1 overview 14.2 block description 14.3 setting for dramc 14.4 dramc operation 14.5 precautions for dramc
14-2 7721 group users manual dram controller 14.1 overview table 14.1.1 lists the performance specifications of dram controller (hereafter called dramc). table 14.1.1 performance specifications of dramc 14.1 overview, 14.2 block description item dram area refreshing method refresh timer multiplexed address pins performance specifications 0 to 15 mbytes; programmable in a unit of 1 mbyte ____ ____ cas before ras; dispersive refreshing 8 bits 10 14.2 block description figure 14.2.1 shows the block diagram of dramc. registers relevant to dramc are described below. bus access controller ras and cas generating circuit address comparator address multiplexer refresh timer 1/(n+1) dram control register address bits 0? a 20 ? 23 a 0 ? 20 f(x in ) 1/16 f 16 ras cas ma 0 ?a 9 refresh request fig. 14.2.1 block diagram of dramc
14-3 7721 group users manual dram controller 14.2.1 dram control register figure 14.2.2 shows the structure of the dram control register. 14.2 block description fig. 14.2.2 structure of dram control register 0 0 0 0 : no dram area 0 0 0 1 : f00000 16 ?fffff 16 (1 mbyte) 0 0 1 0 : e00000 16 ?fffff 16 (2 mbytes) 0 0 1 1 : d00000 16 ?fffff 16 (3 mbytes) 0 1 0 0 : c00000 16 ?fffff 16 (4 mbytes) 0 1 0 1 : b00000 16 ?fffff 16 (5 mbytes) 0 1 1 0 : a00000 16 ?fffff 16 (6 mbytes) 0 1 1 1 : 900000 16 ?fffff 16 (7 mbytes) 1 0 0 0 : 800000 16 ?fffff 16 (8 mbytes) 1 0 0 1 : 700000 16 ?fffff 16 (9 mbytes) 1 0 1 0 : 600000 16 ?fffff 16 (10 mbytes) 1 0 1 1 : 500000 16 ?fffff 16 (11 mbytes) 1 1 0 0 : 400000 16 ?fffff 16 (12 mbytes) 1 1 0 1 : 300000 16 ?fffff 16 (13 mbytes) 1 1 1 0 : 200000 16 ?fffff 16 (14 mbytes) 1 1 1 1 : 100000 16 ?fffff 16 (15 mbytes) bit bit name functions at reset rw 0 1 3 6 to 4 7 dram area select bits dram validity bit (note) 0 0 0 : invalid (p10 4 ?10 7 pins function as programmable input ports. a 0 a 7 pins function as address output pins. refresh timer stops counting.) 1 : valid (p10 4 ?10 7 pins function as cas, ras, ma 8 , and ma 9 . a 0 ? 7 function as ma 0 ?a 7 . refresh timer starts counting.) 0 dram control register (address 64 16 ) b1 b0 b2 b3 b4 b5 b6 b7 rw 0 rw nothing is assigned. the value is ??at reading. 2 0 rw b3 b2 b1 b0 rw 0 rw note: set the refresh timer (address 66 16 ) before setting this bit to ?.
14-4 7721 group users manual dram controller st0, st1 st0, st1 st0, st1 ([0,0] is output.) st0, st1 st0, st1 p10 6 /ma 8 , p10 7 /ma 9 ma 8 , ma 9 ma 8 , ma 9 ma 8 , ma 9 p10 6 , p10 7 14.2 block description (1) dram area select bits (bits 0 to 3) these 4 bits specify a dram area of 15 mbytes maximum in a unit of 1 mbyte. figure 14.2.3 shows setting examples of dram areas. 1 mbyte 000000 16 000000 16 000000 16 000000 16 100000 16 800000 16 c00000 16 ffffff 16 f00000 16 ffffff 16 ffffff 16 ffffff 16 4 mbytes dram area (0001 2 ) dram area select bits (bits 3C0) (0100 2 ) (1000 2 ) (1111 2 ) minimum maximum 8 mbytes 15 mbytes fig. 14.2.3 setting examples of dram areas (2) dram validity bit (bit 7) when this bit is set to 1, pin functions for dram control become valid, and the refresh timer starts counting. table 14.2.1 lists the pin functions for dram control. table 14.2.1 pin functions for dram control pins a 0 /ma 0 Ca 7 /ma 7 ma 0 Cma 7 a 0 Ca 7 a 0 Ca 7 a 0 Ca 7 _______ p10 4 /cas, _______ p10 5 /ras _______ _______ cas, ras _______ _______ cas, ras _______ _______ cas, ras p10 4 ,p10 5 a 16 /d 0 Ca 23 /d 7 , a 8 /d 8 Ca 15 /d 15 , ___ __ _______ _______ r/w, e, ble, bhe a 16 /d 0 Ca 23 /d 7 , a 8 /d 8 Ca 15 /d 15 , ___ __ _______ ________ r/w, e, ble, bhe a 16 /d 0 Ca 23 /d 7 , a 8 /d 8 Ca 15 /d 15 ___ __ _______ ________ r/w, e, ble, bhe a 16 /d 0 Ca 23 /d 7 , a 8 /d 8 Ca 15 /d 15 , ___ __ _______ ________ r/w, e, ble, bhe a 16 /d 0 Ca 23 /d 7 , a 8 /d 8 Ca 15 /d 15 ___ __ _______ ________ r/w, e, ble, bhe operation dram validity bit accessing dram area dram refresh other than the above 1 0
14-5 7721 group users manual dram controller 14.2 block description 14.2.2 refresh timer the refresh timer is an 8-bit timer with a reload register and is used to generate refresh requests for dram data. assuming that the set value of the refresh timer = n, the refresh timer counts f 16 (n + 1) times. figure 14.2.4 shows the structure of the refresh timer, and the following formula gives the value to be written to the refresh timer. n = {m [ s] 5 } C 1 n: a set value of the refresh timer (n = 01 16 Cff 16 ) m: a refresh interval examples of m: an average of 15.625 s for 512 refresh cycles at 8-ms intervals an average of 125 s for 512 refresh cycles at 64-ms intervals fig. 14.2.4 structure of refresh timer b7 b0 refresh timer (address 66 16 ) functions bit at reset rw 7 to 0 these bits can be set to ?1 16 ?to ?f 16 . assuming that the set value = n, this register divides f 16 by (n + 1). undefined wo note: use the ldm or sta instruction for writing to this register. do not set this register to ?0 16 . f(x in ) 16
14-6 7721 group users manual dram controller row address column address row address column address 14.2 block description 14.2.3 address comparator the address comparator examines whether the address to be accessed is within the dram area. when ____ ____ this address is within dram area, control signals are sent to the ras and cas generating circuit and the address multiplexer. ____ ____ 14.2.4 ras and cas generating circuit ____ ____ the ras signal (a timing signal to latch a row address) and the cas signal (a timing signal to latch a column address) are generated by a control signal from the address comparator. 14.2.5 address multiplexer address data is time-shared by the control signal from the address comparator and is output to the ma 0 C ma 9 pins. the time-sharing method depends on the external bus width. table 14.2.2 lists the time-sharing method for the address at dram access. when the 8-bit external bus width is selected, a 0 Ca 19 are time- shared and are output; when the 16-bit external bus width is selected, a 1 Ca 20 are time-shared and are output. table 14.2.2 time-sharing method for address at dram access pin name p10 7 /ma 9 a 1 /ma 1 a 2 /ma 2 a 3 /ma 3 a 4 /ma 4 a 5 /ma 5 a 7 /ma 7 p10 6 /ma 8 a 0 /ma 0 a 1 a 9 a 1 a 9 a 2 a 10 a 2 a 10 a 3 a 11 a 3 a 11 a 4 a 12 a 4 a 12 a 5 a 13 a 5 a 13 a 6 a 14 a 6 a 14 a 7 a 15 a 7 a 15 a 16 a 17 a 18 a 17 a 18 a 19 a 20 a 19 output signal 8-bit external bus width 16-bit external bus width a 0 a 8 a 16 a 8 a 6 /ma 6
14-7 7721 group users manual dram controller dram area setting and dram validity selection b7 b0 dram area select bits b3 b2 b1 b0 ?during dram area access, cas, ras, and ma 0 Cma 9 are output. ?each time an underflow of the refresh timer occurs, cas and ras for refresh are output. ?during refresh, st0 and st1 output l level. division ratio setting for refresh timer b7 b0 can be set to 00 16 to ff 16 (n). refresh timer divides f 16 by (n+1). refresh timer (address 66 16 ) dram control register [address 64 16 ] 1 0 0 0 0: no dram area 0 0 0 1: addresses f00000 16 Cffffff 16 (1 mbyte) 0 0 1 0: addresses e00000 16 Cffffff 16 (2 mbytes) 0 0 1 1: addresses d00000 16 Cffffff 16 (3 mbytes) 0 1 0 0: addresses c00000 16 Cffffff 16 (4 mbytes) 0 1 0 1: addresses b00000 16 Cffffff 16 (5 mbytes) 0 1 1 0: addresses a00000 16 Cffffff 16 (6 mbytes) 0 1 1 1: addresses 900000 16 Cffffff 16 (7 mbytes) 1 0 0 0: addresses 800000 16 Cffffff 16 (8 mbytes) 1 0 0 1: addresses 700000 16 Cffffff 16 (9 mbytes) 1 0 1 0: addresses 600000 16 Cffffff 16 (10 mbytes) 1 0 1 1: addresses 500000 16 Cffffff 16 (11 mbytes) 1 1 0 0: addresses 400000 16 Cffffff 16 (12 mbytes) 1 1 0 1: addresses 300000 16 Cffffff 16 (13 mbytes) 1 1 1 0: addresses 200000 16 Cffffff 16 (14 mbytes) 1 1 1 1: addresses 100000 16 Cffffff 16 (15 mbytes) dram is valid. (p10 4 Cp10 7 pins function as cas,ras, ma 8 , and ma 9 . a 0 Ca 7 function as ma 0 Cma 7 when accessing the dram area. refresh timer starts counting.) 14.3 setting for dramc figure 14.3.1 shows an initial setting example for registers relevant to dramc. 14.3 setting for dramc fig. 14.3.1 initial setting example for registers relevant to dramc
14-8 7721 group users manual dram controller 14.4 dramc operation 14.4 dramc operation 14.4.1 waveform example of dram control signals figure 14.4.1 shows a waveform example of the dram control signals. when dram is accessed, the bus __ cycle is always with wait (the low-level width of e is equivalent to 2 cycles of f ). it is not affected by the wait bit, the wait bit of the transfer source, and the wait bit of the transfer destination. (1) read cycle ____ ____ in the read cycle, the cas signal falls with a delay of 0.5 cycle of f after the ras signal has changed from h to l. the address bus signal changes from row address to column address within a ____ ____ period from a fall of ras until a fall of cas. pins a 16 /d 0 Ca 23 /d 7 and a 8 /d 8 Ca 15 /d 15 output addresses and input data in the same way as in reading external devices other than dram. (2) write cycle ____ ____ in the write cycle, the cas signal falls with a delay of 1 cycle of f after the ras signal has changed from h to l. the address bus signal changes row address to column address within a period ____ ____ from a fall of ras until a fall of cas. pins a 16 /d 0 Ca 23 /d 7 and a 8 /d 8 Ca 15 /d 15 output addresses and data in the same way as in writing external devices other than dram. (3) refresh cycle ____ ____ in the refresh cycle, the ras signal falls with a delay of 0.5 cycle of f after the cas signal has changed from h to l. __ r/w is undefined. one refresh request requires 5 cycle of f , including the time for passing the right to use buses.
14-9 7721 group users manual dram controller 14.4 dramc operation fig. 14.4.1 waveform example of dram control signals column address e ras cas r/w (a) at reading row address column address address data read cycle (1 bus cycle) ma 0 Cma 9 a 16 /d 0 Ca 23 /d 7 a 8 /d 8 Ca 15 /d 15 e ras cas r/w ma 0 Cma 9 a 16 /d 0 Ca 23 /d 7 a 8 /d 8 Ca 15 /d 15 (c) at refresh undefined refresh cycle undefined undefined floating transition of right to use bus e ras cas r/w ma 0 Cma 9 a 16 /d 0 Ca 23 /d 7 a 8 /d 8 Ca 15 /d 15 (b) at writing row address address data write cycle (1 bus cycle) undefined transition of right to use bus
14-10 7721 group users manual dram controller dmac cpu 14.4.2 refresh request when the dram validity bit is set to 1, the refresh timer starts counting down. the count source is f 16 . when the contents of the refresh timer reach 00 16 , a refresh request occurs. the refresh timer reloads the contents of address 66 16 and continues counting. a refresh requests are sampled as bus requests (dramc) by using the bus access controller. as soon as a refresh request is acknowledged by sampling, the following ? is performed because dram refresh has the highest priority in using the bus. however, when the cpu or dmac uses the bus, no bus request is sampled until the cpu or dmac releases the bus. therefore, in a period from when a refresh request occurs until dram refresh is performed, the delay listed in table 14.4.1 occurs depending on the refresh request generating timing. figures 14.4.2 and 14.4.3 show refresh delay time examples when cpu is operating and during dma transfer. for a bus request, refer to 13.2.1 bus access control circuit. ? when the refresh request is accepted, the right to use the bus is passed to dram refresh (1 cycle of f ). both of the output levels of st1 and st0 are l. (the bus status is indicated as [0, 0].) ____ ____ ? the ras and the cas signals are output and the dram data is refreshed (refresh cycle: 3 cycles of f ). ? the right to use the bus is passed to the cpu, dram or hold (1 cycle of f ). the outputs of st1 and st0 change. note: in stop or wait mode, dram refresh is not performed because no refresh request occurs. table 14.4.1 delay time from when refresh request occurs until dram refresh is performed 14.4 dramc operation hold maximum (with wait) maximum (no wait) minimum 1.5 1.5 1.5 4.5 8.5 11.5 6.5 1.5 6.5 12.5 15.5 6.5 1.5 source of using bus array state transfer (a unit of 1 transfer) transfer (a unit of 1 transfer) + complete cycle delay time (unit: f cycle) note: the above is applied when ready is not used. the delay time includes the time for passing the right to use buses to dram refresh (1 cycle).
14-11 7721 group users manual dram controller 14.4 dramc operation fig. 14.4.2 refresh delay time example when cpu is operating e r/w refresh request bus request (dramc) bus request sampling st1,st0 11 (cpu) 00 (refresh) refresh cycle delay time (max.): 6.5 cycles of 00 refresh cycle transition of right to use bus the following are internal signals: ?refresh request ?bus request (dramc) ?bus request sampling refresh request becomes 0 at an underflow of the refresh timer. delay time (min.): 1.5 cycles of transition of right to use bus transition of right to use bus transition of right to use bus 10 (dmac) 00 (refresh) refresh cycle delay time (max.): 12.5 cycles of e r/w refresh request bus request (dramc) bus request sampling st1,st0 the following are internal signals: ?refresh request ?bus request (dramc) ?bus request sampling refresh request becomes 0 at an underflow of the refresh timer. transition of right to use bus fig. 14.4.3 refresh delay time example during dma transfer
14-12 7721 group users manual dram controller 14.5 precautions for dramc 14.5 precautions for dramc 1. set the refresh timer (address 66 16 ) to any of 01 16 Cff 16 . 2. when a dram refresh request occurs during hold state, a refresh cycle is activated regardless of the bus state. it is because a bus request is always sampled during hold state. therefore, in order to use the dramc together with the hold function, an external circuit which is controlled depending on the states of st0 and st1 is required. 3. dram refresh is not performed in stop or wait mode.
chapter 15 watchdog timer 15.1 block description 15.2 operation description 15.3 precautions for watchdog timer
watchdog timer 7721 group users manual 15C2 15.1 block description watchdog functions as follows: l detects a program runaway. l measures a certain time from when oscillation starts owing to terminating stop mode. (refer to section 5.3 stop mode. ) 15.1 block description figure 15.1.1 shows the block diagram of watchdog timer. fig. 15.1.1 block diagram of watchdog timer 2v cc detection circuit ?ff 16 ? is set. writing to watchdog timer register (address 60 16 ) stp instruction bus request (hold) watchdog timer interrupt request reset s q r f 32 watchdog timer cpu wait request f 512 bus request (dramc) bus request (dmac)
watchdog timer 7721 group users manual 15C3 15.1.1 watchdog timer watchdog timer is a 12-bit counter where the count source which is selected with the watchdog timer frequency select bit (bit 0 at address 61 16 ) is counted down. a value fff 16 is automatically set in watchdog timer in the cases listed below. an arbitrary value cannot be set to watchdog timer. l when dummy data is written to the watchdog timer register (refer to figure 15.1.2. ) l when the most significant bit of watchdog timer becomes 0 l when the stp instruction is executed (refer to section 5.3 stop mode. ) l at reset 15.1 block description fig. 15.1.2 structure of watchdog timer register 15.1.2 watchdog timer frequency select register this is used to select a watchdog timers count source. figure 15.1.3 shows the structure of the watchdog timer frequency select register. fig. 15.1.3 structure of watchdog timer frequency select register b7 b0 watchdog timer register (address 60 16 ) bit initializes watchdog timer. when dummy data is written to this register, watchdog timer? value is initialized to ?ff 16 .?(dummy data: 00 16 to ff 16 ) at reset undefined rw functions 7 to 0 0 : f 512 1 : f 32 at reset undefined 0 rw functions b7 b6 b5 b4 b3 b2 b1 b0 watchdog timer frequency select register (address 61 16 ) bit nothing is assigned. watchdog timer frequency select bit bit name 0 7 to 1 rw
watchdog timer 7721 group users manual 15C4 15.2 operation description 15.2 operation description 15.2.1 basic operation watchdog timer starts counting down from fff 16 . when the watchdog timers most significant bit becomes 0 (counted 2048 times), a watchdog timer interrupt request occurs. (refer to table 15.2.1. ) a when the interrupt request occurs at above , a value fff 16 is set to watchdog timer. the watchdog timer interrupt is a non-maskable interrupt. when the watchdog timer interrupt request is accepted, the processor interrupt priority level (ipl) is set to 111 2 . table 15.2.1 occurrence interval of watchdog timer interrupt request f(x in ) = 25 mhz occurrence interval 41.94 ms 2.62 ms count source f 512 f 32 watchdog timer frequency select bit 0 1
watchdog timer 7721 group users manual 15C5 write dummy data to the watchdog timer register (address 60 16 ) before the most significant bit of watchdog timer becomes 0. when watchdog timer is used to detect a program runaway, a watchdog timer interrupt request occurs if writing to address 60 16 is not performed owing to a program runaway and the most significant bit of watchdog timer becomes 0. this means that a program runaway has occurred. in order to reset the microcomputer when a program runaway is detected, write 1 to the software reset bit (bit 3 at address 5e 16 ) in the watchdog timer interrupt routine. 15.2 operation description rti main routine watchdog timer interrupt routine watchdog timer register (address 60 16 ) 8-bit dummy data watchdog timer interrupt request occur (program runaway detected) watchdog timer initialized value of watchdog timer : ?ff 16 ?( note 1 ) software reset bit (address 5e 16 , b3) ??( note 2 ) reset microcomputer notes 1: initialize watchdog timer before the most significant bit of watchdog timer becomes ?.?(write dummy data to address 60 16 before a watchdog timer interrupt request occurs). 2: when a program runaway occurs, values of the data bank register (dt), direct page register (dpr), etc., may be changed. when ??is written to the software reset bit by the addressing mode using dt, dpr, etc., set values to dt and dpr again. fig. 15.2.1 example of program runaway detection by watchdog timer
watchdog timer 7721 group users manual 15C6 15.2.2 stop period watchdog timer stops operation in the following period: hold state (refer to section 3.4 hold function. ) during dmac operation (refer to chapter 13. dma controller. ) a during dram refresh (refer to chapter 14. dram controller. ) ? stop mode when states to a are terminated, watchdog timer restarts counting from the state before it stops operation. for watchdog timers operation when state ? is terminated, refer to section 15.2.3 operation in stop mode. 15.2.3 operation in stop mode in stop mode, watchdog timer stops operation. immediately after stop mode is terminated, watchdog timer operates as follows. (refer to section 5.3 stop mode. ) (1) when stop mode is terminated by hardware reset supply of f and f cpu starts immediately after stop mode is terminated, and the microcomputer performs operation after reset. (refer to chapter 4. reset. ) the watchdog timer frequency select bit becomes 0, and watchdog timer starts counting of f 512 from fff 16 . (2) when stop mode is terminated by interrupt request occurrence immediately after stop mode is terminated, watchdog timer starts counting of f 32 from fff 16 regardless of the contents of watchdog timer frequency select bit (bit 0 at address 61 16 ). supply of f and f cpu starts when watchdog timers most significant bit becomes 0. ( at this time, a watchdog timer interrupt request does not occur.) when supply of f cpu starts, the microcomputer executes the routine of the interrupt which is used to terminate stop mode. watchdog timer restarts counting of the count source (f 32 or f 512 ), which was counted immediately before executing the stp instruction, from fff 16 . 15.2 operation description
watchdog timer 7721 group users manual 15C7 15.3 precautions for watchdog timer 15.3 precautions for watchdog timer 1. when dummy data is written to address 60 16 with the 16-bit data length, writing to address 61 16 is simultaneously performed. accordingly, when the user does not want to change a value of the watchdog timer frequency select bit (bit 0 at address 61 16 ), write the previous value to the bit simultaneously with writing to address 60 16 . 2. when the stp instruction is executed, watchdog timer stops. (refer to section 5.3 stop mode. ) 3. watchdog timer stops during dram refresh, hold state, and dmac operation. (for watchdog timers structure, refer to figure 15.1.1. ) accordingly, when a bus request is changed in the period which is shorter than 1 cycle of the count source (note) , watchdog timers count may gain. (refer to figure 15.3.1. ) note: f 32 or f 512 , which is selected by the watchdog timer frequency select bit fig. 15.3.1 count source for watchdog timer f 32 or f 512 bus request count source which is actually counted by watchdog timer i n case the bus request is changed in a period which is shorter than 1 cycle of f 32 or f 512
watchdog timer 7721 group users manual 15C8 15.3 precautions for watchdog timer memorandum
chapter 16 application 16.1 memory connection 16.2 examples of using dma controller 16.3 comparison of sample program execution rate
application 7721 group users manual 16C2 16.1 memory connection this chapter describes application. application shown here is just examples. the user shall modify them according to the actual application and test them. 16.1 memory connection this section shows examples for memory and i/o connection. refer to chapter 3. connection with external devices for details about the functions and operations of used pins when connecting a memory or i/o. refer to section appendix 11. electrical characteristics for timing requirements of the microcomputer. 16.1.1 memory connection model for the m37721, the level of the external data bus width select signal makes it possible to select the memory connection model from the four models listed in table 16.1.1. (1) minimum model this is a connection model of which external data bus width is 8 bits and access space is expanded up to 64 kbytes. it is unnecessary to connect the address latch externally, so this model gives priority to cost and is most suitable when connecting the memory of which data bus width is 8 bits. (2) medium model a this is a connection model of which external data bus width is 8 bits and access space is expanded up to 16 mbytes. in this model, the high-order 8 bits of the external address bus (a 16 to a 23 ) are multiplexed with the external data bus. therefore, an n-bit (n 8) address latch is required for latching n bits of the address in a 16 to a 23 . (3) medium model b this is a connection model of which external data bus width is 16 bits and access space is expanded up to 64 kbytes. this model gives priority to rate performance. in this model, the middle-order 8 bits of the external address bus (a 8 to a 15 ) are multiplexed with the external data bus. therefore, an 8- bit address latch is required for latching a 8 to a 15 . (4) maximum model this is a connection model of which external data bus width is 16 bits and access space is expanded up to 16 mbytes. in this model, the high- and middle-order 16 bits of the external address bus (a 8 to a 23 ) are multiplexed with the external data bus. therefore, an 8-bit address latch for latching a 8 to a 15 and an n-bit (n 8) address latch for latching n bits of a 16 to a 23 are required.
application 7721 group users manual 16C3 16.1 memory connection table 16.1.1 memory connection model byte byte m37721 byte m37721 byte m37721 a 0 Ca 15 16 d 0 Cd 7 8 a 0 Ca 15 e d 0 Cd 15 8 16 16 dq a 0 Ca 15+n d 0 Cd 7 8 16+n e n dq latch e a 0 Ca 15+n d 0 Cd 15 8 16 n 16+n dq e dq a 0 Ca 7 ale bhe m37721 ale ale bhe 8-bit width; byte = h notes 1 : refer to chapter 3. connection with external devices for details about the functions and operations of used pins when connecting a memory. refer to section appendix 11. electrical characteristics for timing requirements. 2 : because the address bus can be expanded up to 24 bits when connecting a memory, strengthen the m37721s vss and vcc lines on the system. (refer to section appendix 8. countermeasure against noise. ) external data bus width 16-bit width; byte = l access space maximum 64 kbytes maximum 16 mbytes memory connection model minimum model latch memory connection model medium model b memory connection model medium model a latch latch memory connection model maximum model a 8 Ca 15 a 16 /d 0 Ca 23 /d 7 a 0 Ca 7 a 8 Ca 15 a 16 /d 0 Ca 23 /d 7 a 0 Ca 7 a 8 /d 8 Ca 15 /d 15 a 16 /d 0 Ca 23 /d 7 ble a 0 Ca 7 a 8 /d 8 Ca 15 /d 15 a 16 /d 0 Ca 23 /d 7 ble
application 7721 group users manual 16C4 16.1 memory connection 16.1.2 how to calculate timing timings at which data is read or written when connecting a memory and precautions when connecting a memory are described below. for timing requirements of the memory and detailed account except limits described below, also refer to the memorys data book etc. when using bus buffers, various logical circuits, etc., be sure to consider the propagation delay time etc. (1) timing for reading data when reading data, the external data bus is placed in a floating state, and data is read from the _ external memory. this floating state is maintained after the falling edge of the e signal until an _ interval of t pzx(eCdlz/dhz) has passed after the rising edge of the e signal. satisfy t su(dl/dh-e) when inputting data read from the external memory. the following are described below: ?timing for reading data from the flash memory, sram, and dram ?calculation formulas for the external memorys access time, which are for t su(dl/dh-e) to be satisfied ___ __ the memory output enable signal (oe) is assumed to be generated from the e signal. l timing for reading data from flash memory and sram fig. 16.1.1 timing for reading data from flash memory and sram external memory data output ] 1: this applies when the external data bus has a width of 16 bits (byte = l). external memory output enable signal (read signal) oe e external memory chip select signal ce, s ] 2: if data is output from the external memory before the falling edge of e, there is a possi bility that the tail of address collides wit t h the head of data. of collides wi h the head of . ? refer to section (3) precautions on memory connection. ] 3: if one of the external memorys specifications is greater than t pzx (e-dlz/dhz) , there is a possibility that the tail ? refer to section (3) precautions on memory connection. address output and data input a 8 / d 8 Ca 15 /d 15 a 16 /d 0 Ca 23 /d 7 ] 1 t en (oe) address t pzx (e-dlz/dhz) t su (dl/dh-e) : specifications of the m37721 (the others are specifications of external memory.) t a (oe) t df , t dis (oe) ] 2 ] 3 t w(el) data t en (ce) , t en (s) address t a (ce) , t a (s) t a (ad) , t su (a-dl/dh) note: t su(a-dl/dh) : t su(a-dl) or t su(a-dh) t pzx(e-dlz/dhz) : t pzx(e-dlz) or t pzx(e-dhz) t su(dl/dh-e) : t su(dl-e) or t su(dh-e) data address
application 7721 group users manual 16C5 16.1 memory connection address access time : t a(ad) t su(a-dl/dh) C address latch delay time ] 1 ___ oe access time : t a(oe) t w(el) C t su(dl/dh-e) chip select access time : t a(s) t su(a-dl/dh) C (address decode time ] 2 + address latch delay time ] 1 ) address latch delay time ] 1 : delay time required when latching address (unnecessary in minimum model) address decode time ] 2 : time required for validating chip select signal after decoding address table 16.1.2 lists the calculation formulas and values for each parameter in figure 16.1.1. figure 16.1.2 shows the relationship between t su(a-dl/dh) and f(x in ). table 16.1.2 calculation formulas and values for each parameter in figure 16.1.1 (unit : ns) 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 0 100 200 300 400 500 600 700 644 555 485 430 384 346 314 287 263 242 224 207 193 180 168 157 147 138 130 358 305 263 230 202 180 160 144 130 117 106 96 87 80 72 66 60 55 50 [ns] [mhz] external clock input frequency f(x in ) data setup time with address stabilized t su(a?l/dh) wait no wait calculation formulas and values no wait wait t w(el) t su(a-dl) t su(a-dh) t pzx(e-dlz) t pzx(e-dhz) t su(dl-e) t su(dh-e) 2 5 10 9 f(x in ) 3 5 10 9 f(x in ) C25 4 5 10 9 f(x in ) 5 5 10 9 f(x in ) C25 C70 C70 1 5 10 9 f(x in ) C20 30 fig. 16.1.2 relationship between t su(a-dl/dh) and f(x in )
application 7721 group users manual 16C6 16.1 memory connection l timing for reading data from dram fig. 16.1.3 timing for reading data from dram ____ cas access time : t cac t w(el) C t d(e-casl) C t su(dl/dh-e) ____ ras access time : t rac t w(el) C t d(e-rasl) C t su(dl/dh-e) column address access time : t aa t w(el) C t d(e-ca) C t su(dl/dh-e) ___ oe access time : t oea t w(el) C t su(dl/dh-e) table 16.1.3 lists the calculation formula and value for each parameter in figure 16.1.3. figure 16.1.4 shows the relationship between t cac , t rac , t aa and f(x in ). t w(el) t d(e-rasl) t d(e-ca) address t oea t rac t clz t cac t oez ] 2 t d(e-casl) row address column address e ras cas address output (ma 0 Cma 7 ) address output and data i/o t aa t su(dl/dh-e) a 8 /d 8 Ca 15 /d 15 a 16 /d 0 Ca 23 /d 7 ] 1 dram data output data : specifications of the m37721 (the others are specifications of dram.) ] 1 this applies when the external data bus has a width of 16 bits (byte = l). ] 2 if one of drams specifications is greater than t pzx(eCdlz/dhz) , there is a possibility that the tail of data collides with the head of address. ? refer to section (3) precautions on memory connection. note: t pzx(e-dlz/dhz) : t pzx(e-dlz) or t pzx(e-dhz) t su(dl/dh-e) : t su(dl-e) or t su(dh-e) oe dram output enable signal (read signal) t pzx(eCdlz/dhz)
application 7721 group users manual 16C7 16.1 memory connection table 16.1.3 calculation formula and value for each parameter in figure 16.1.3 (unit : ns) calculation formula and value t w(el) t d(e-rasl) t d(e-casl) t d(e-ca) t pzx(e-dlz) t pzx(e-dhz) t su(dl-e) t su(dh-e) 1 5 10 9 f(x in ) 30 4 5 10 9 f(x in ) C 25 30 + 37.5 1 5 10 9 f(x in ) + 25 1 5 10 9 f(x in ) C 20 note: when accessing dram, wait is always inserted regardless of the contents of the wait bit, sources wait bit, and destinations wait bit. fig. 16.1.4 relationship between t cac , t rac , t aa and f(x in ) 7 8 9 10 11 12 137.5 13 14 15 16 17 18 19 20 21 22 23 24 25 0 50 100 150 200 250 300 350 400 450 500 451 380 324 280 243 213 187 165 146 130 115 102 90 80 70 61 53 46 40 486 415 359 315 278 248 222 181 165 150 137 125 115 105 96 88 81 75 335.5 282.5 240.5 207.5 179.5 157.5 94.5 83.5 73.5 64.5 57.5 49.5 43.5 37.5 32.5 27.5 column address access time : t aa ras access time : t rac cas access time : t cac access time [ns] external clock input frequency f(x in ) [mhz] 107.5 121.5 200
application 7721 group users manual 16C8 16.1 memory connection (2) timing for writing data when writing data, the output data is stabilized when an interval of t d(e-dlq/dhq) has passed after the _ falling edge of the e signal. this data is continuously output until when an interval of t h(e-dlq/dhq) has _ passed after the rising edge of the e signal. data to be written to an external memory must satisfy the data set up time (t su(d) ) (for dram, the data hold time (t dh )) of the external memory. the following are described below: ?timing for writing data to flash memory, sram, and dram ?calculation formulas which are for t su(d) and t dh to be satisfied l timing for writing data to flash memory and sram t su (d) t h (d) address data e w external memory chip select signals ce, s t w(el) t h (e-dlq/dhq) (the others are specifications of external memory.) : specifications of the m37721 ] this applies when the external data bus has a width of 16 bits (byte = ??. t d (e?lq/dhq) a 8 /d 8 ? 15 /d 15 a 16 /d 0 ? 23 /d 7 ] address output and data input external memory write signal address fig. 16.1.5 timing for writing data to flash memory and sram data setup time : t su(d) t w(el) C t d(e-dlq/dhq) table 16.1.4 lists the calculation formulas and values for each parameter in figure 16.1.5, figure 16.1.6 shows the relationship between t su(d) and f(x in ).
application 7721 group users manual 16C9 16.1 memory connection table 16.1.4 calculation formulas and values for each parameter in figure 16.1.5 (unit : ns) calculation formulas and values no wait wait t w(el) t d(e-dlq) t d(e-dhq) t h(e-dlq) t h(e-dhq) 2 5 10 9 f(x in ) C25 4 5 10 9 f(x in ) C25 1 5 10 9 f(x in ) C22 35 fig. 16.1.6 relationship between t su(d) and f(x in ) 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 0 100 200 300 400 500 600 506 435 379 335 298 268 242 220 201 185 170 157 145 135 125 116 108 101 95 220 185 157 135 116 101 88 77 68 60 52 46 40 35 30 25 21 18 15 no wait wait external clock input frequency f(x in ) data setup time t su(d) [mhz] [ns]
application 7721 group users manual 16C10 16.1 memory connection l timing for writing data to dram fig. 16.1.7 timing for writing data to dram data hold time : t dh t w(el) C t d(e-casl) + t h(e-dlq/dhq) table 16.1.5 lists the calculation formula and value for each parameter in figure 16.1.7. figure 16.1.8 shows the relationship between t dh and f(x in ). dram write signal w t w(el) t d(e-casl) row address column address address data t d(e-dlq/dhq) t dh t h(e-dlq/dhq) ] this applies when the external data bus has a width of 16 bits (byte = ??. e ras cas address output (ma 0 ?a 7 ) address output and data i/o a 8 /d 8 ? 15 /d 15 a 16 /d 0 ? 23 /d 7 : specifications of the m37721 (the others are specifications of dram.) ]
application 7721 group users manual 16C11 16.1 memory connection table 16.1.5 calculation formula and value for each parameter in figure 16.1.7 (unit : ns) calculation formula and value t w(el) t d(e-casl) t d(e-dlq) t d(e-dhq) t h(e-dlq) t h(e-dhq) 4 5 10 9 f(x in ) C25 80 to 115 1 5 10 9 f(x in ) C22 35 note: when accessing dram, wait is always inserted regardless of the contents of the wait bit, sources wait bit, and destinations wait bit. fig. 16.1.8 relationship between t dh and f(x in ) 0 100 200 300 400 500 7 8 9 101112131415161718192021 22232425 486.5 415.5 359.5 315.5 278.5 248.5 222.5 200.5 181.5 165.5 150.5 137.5 125.5 115.5 105.5 96.5 88.5 81.5 75.5 data hold time t dh [ns] external clock input frequency f(x in ) [mhz]
application 7721 group users manual 16C12 16.1 memory connection (3) precautions on memory connection as described in to a below, if specifications of the external memory do not match those of the m37721, some considerations must be incorporated into circuit design: when using an external memory that requires a long access time _ when data is output from an external memory before falling edge of the e signal a when using an external memory that outputs data for more than t pzx(e-dlz/dhz) after rising edge of _ the e signal when using external memory that requires long access time if the m37721s t su(dl/dh-e) cannot be satisfied because the external memory requires a long access time, try to carry out the following: l lower f(x in ). l select software wait is inserted. (refer to section 3.2 software wait. ) l use ready function. (refer to section 3.3 ready function. ) figure 16.1.9 shows an example of using ready function (no software wait). figure 16.1.10 shows an example of using ready function (software wait). ready function is valid for the internal areas, so that the circuits in figures 16.1.9 and 16.1.10 use ___ ___ the chip select signal (cs 2 ) to specify areas where ready function is valid. in these cases, the cs 2 signal is externally generated.
application 7721 group users manual 16C13 16.1 memory connection m37721 a 8 Ca 23 (d 0 Cd 15 ) a 0 Ca 7 rdy e 1 address decode circuit d ck q ac74 ac32 ac32 data bus cs 1 cs 2 address bus ac04 1 validate ready function only for areas accessed by cs 2 . circuit conditions : f(x in ) 15.7 mhz, no software wait ] 1 to ] 3 : make sure that the sum of propagation delay time is within 15 ns. ] 3 to ] 5 : make sure that the sum of propagation delay time is within 72 ns. ] 5 ] 4 ready request is accepted at a . termination request for ready state is accepted at b . a , b : judgement timing of rdy pins input level 1 t c t d(e- 1) 1 e cs 2 q rdy t su(rdy- 1) ac32(t phl ) ] a b ] 3 ] 2 ] 1 address latch circuit : e (l level) stopped by ready function ] the condition satisfy t su(rdyC 1 ) 3 55 ns is t c 3 63.5 ns. (this applies when ac32s propagation delay time is within 8.5 ns.) accordingly, when f(x in ) 15.7 mhz, this circuit example satisfies t su(rdyC 1 ) 3 55 ns. fig. 16.1.9 example of using ready function (no software wait)
application 7721 group users manual 16C14 16.1 memory connection fig. 16.1.10 example of using ready function (software wait) m37721 1d 1ck 1q ac74 ac32 ac32 ac04 2d 2ck 2q clr ac04 1 1 e cs 2 2q rdy t su(rdy- 1) ac04 + ac74 + ac32s propagation delay time t h( 1-rdy) 1q a b a 8 Ca 23 (d 0 Cd 15 ) a 0 Ca 7 rdy e 1 address decode circuit address latch circuit data bus cs 1 cs 2 address bus validate ready function only for areas accessed by cs 2 . ] 1 to ] 3 : make sure that the sum of propagation delay time is within 25 ns. circuit conditions : f(x in ) 25 mhz, software wait ] 3 ] 2 ] 1 ready request is accepted at a . termination request for ready state is accepted at b . a , b : judgement timing of rdy pins input level : e (l level) stopped by ready function : e (l level) stopped by software wait
application 7721 group users manual 16C15 16.1 memory connection _ when data is output from external memory before falling edge of e signal _ because the external memory outputs data before the falling edge of the e signal, there is a possibility that the tail of address collides with the head of data. in such a case, generate the __ _ external memory read signal (oe) by using e. (refer to figure 16.1.11. ) fig. 16.1.11 example of making data output timing delayed a when using external memory that outputs data for more than t pzx(e-dlz/dhz) after rising edge of _ e signal because the external memory outputs data for more than t pzx(e-dlz/dhz) after the rising edge of the _ e signal, there is a possibility that the tail of data collides with the head of address. in such a case, try to carry out the following: l cut the tail of data output from the memory by using, for example, a bus buffer. l use the mitsubishis memory chips that can be connected without a bus buffer. figures 16.1.12 to 16.1.15 show examples of using bus buffers and the timing charts. table 16.1.6 lists the mitsubishis memory chips that can be connected without a bus buffer. when using one of these memory chips, timing parameters t df and t dis(oe) listed below are guaranteed. accordingly, ___ no bus buffer is necessary for the system where the external memorys read signal (oe) goes high _ within t pzx(e-dlz/dhz) -t df (or t dis(oe) ) [ns] after the rising edge of the e signal. table 16.1.6 mitsubishis memory chips that can be connected without bus buffers note: make sure that d 3 0 is satisfied when generating the external memory read signal (oe). external memory output enable signal (read signal) address t a(oe) e oe address output external memory data output specifications of external memory d t en(oe) address data memory flash memory sram type m5m28f101ap, fp, j, vp, rv-85, -10 m5m28f102afp, j, vp-85, -10 m5m5256dp, fp, kp, vp, rv-45ll, -45xl, -55ll, -55xl, -70ll, -70xl m5m5278dp, j-12 m5m5278dp, fp, j-15, -15l m5m5278dp, fp, j-20, -20l t df /t dis(oe) (maximum) 15 ns (guaranteed as kit.) (note) 6 ns 7 ns 8 ns note: t df or t dis(oe) listed above is guaranteed when these memory chips are connected with the m37721. when the user wants specifications of these memory chips, add a comment t df /t dis(oe) = 15 ns, microcomputer and kit.
application 7721 group users manual 16C16 16.1 memory connection m37721 cnvss a 0 ? 7 byte ale a 8 /d 8 ? 15 /d 15 e r/w bhe ble x in x out a 16 /d 0 ? 23 /d 7 rd wo we dq le oe dq le oe ab dir oc ab dir oc ac245 ac245 ac573 ac573 ac32 ac04 ac32 25 mhz data bus (odd) address bus data bus (even) ] 2 ] 2 ] 3 ] 1 ] 4 circuit condition: software wait ] 1: make sure that the propagation delay time is within 20 ns. ] 2, ] 3: make sure that the sum of output disable time in ] 2 and propagation delay time in ] 3 is within 20 ns. ] 4: make sure that the propagation delay time is within 15 ns. fig. 16.1.12 example of using bus buffers (1)
application 7721 group users manual 16C17 16.1 memory connection a a d ac245 (t phz /t plz ) ac245 (t pzh /t pzl ) ac32(t phl ) ac32(t plh ) t w(el) = 135 (min.) t pzx(e-dlz/dhz) = 20 (min.) e a 8 /d 8 Ca 15 /d 15 a 16 /d 0 Ca 23 /d 7 oc(ac245), rd e a 8 /d 8 Ca 15 /d 15 a 16 /d 0 Ca 23 /d 7 oc(ac245), wo, we a a d ac245 (t phz /t plz ) ac245 (t phl /t plh ) ac32(t phl ) ac32(t plh ) t d(e-dlq/dhq) = 35 (max.) t w(el) = 135 (min.) d (unit : ns) data output a from external memory (ac245) data output b from external memory (ac245) fig. 16.1.13 timing chart for circuit example using bus buffers (1)
application 7721 group users manual 16C18 16.1 memory connection m37721 cnvss a 0 Ca 7 byte ale a 8 /d 8 Ca 15 /d 15 e r/w bhe ble x in x out a 16 /d 0 Ca 23 /d 7 address bus ab dir oc ab dir oc ac245 dq le oe ac573 dq le oe ac573 rd wo we ac32 ac04 ac32 25 mhz 1d 1q 1t 2d 2t 2q ac04 ac74 1 1 ac245 data bus (even) data bus (odd) ] 2 ] 2 these circuits make the occurrence of the write signals rising edge earlier by 1/2 1 , so that the write hold time is extended. circuit condition : software wait ] 1: make sure that the propagation delay time is within 20 ns. ] 2: make sure that the output disable time is within 20 ns. ] 1 fig. 16.1.14 example for using bus buffers (2) (connecting with memory requiring long data hold time for writing)
application 7721 group users manual 16C19 16.1 memory connection a a d ac245 (t phz /t plz ) ac245 (t pzh /t pzl ) ac32(t phl ) ac32(t plh ) t w(el) = 135 (min.) t pzx(e-dlz/dhz) = 20 (min.) e, oc (ac245) a 8 /d 8 Ca 15 /d 15 a 16 /d 0 Ca 23 /d 7 rd e, oc (ac245) a 8 /d 8 Ca 15 /d 15 a 16 /d 0 Ca 23 /d 7 a d ac245 (t phl /t plh ) 35 (max.) d ac245 (t phz /t plz ) ac32 5 2(t plh ) ac04(t plh ) + ac74(t plh ) 1 1 1q (ac74) 2q (ac74) wo, we data output a from external memory (ac245) (unit : ns) write hold time t w(el) = 135(min.) data output b from external memory (ac245) fig. 16.1.15 timing chart for circuit example using bus buffers (2)
application 7721 group users manual 16C20 16.1 memory connection 16.1.3 example of memory connection examples of the flash memory, sram, and dram connection and the timing charts are described as follows. (1) example of flash memory connection (minimum model) m37721 a 0 Ca 15 byte ac04 d 0 Cd 7 bhe ble e r/w address bus a 0 Ca 15 data bus d 0 Cd 7 a 0 Ca 15 d 0 Cd 7 we ce oe m5m28f101afp-10 0000 16 0080 16 0480 16 1fc0 16 2000 16 ffff 16 x in x out 25 mhz open open ] : make sure that the propagation delay time is within 25 ns. ] sfr area internal ram area external rom area (m5m28f101afp) memory map sfr area external rom area (m5m28f101afp) circuit condition : software wait fig. 16.1.16 example of flash memory connection (minimum model)
application 7721 group users manual 16C21 16.1 memory connection e, oe a 16 /d 0 ? 23 /d 7 rw external rom data output ce t pzx(e-dlz) = 20 (min.) aa d t h(e-r/w) = 18 (max.) t w(el) = 135 (min.) t su(dl-e) 3 30 t a(oe) ] t a(ce) ] t df ] = 15 (max.) (guaranteed as kit.) ac04 (t plh ) t d(r/w-e) = 20 (min.) t a (ad) ] , t su (a-dl) = 130 (max.) ac04 (t phl ) t d(ah-e) = 15 (min.) ] : specifications of m5m28f101afp-10 the others are specifications of m37721. fig. 16.1.17 timing chart for flash memory connection example (minimum model)
application 7721 group users manual 16C22 16.1 memory connection (2) example of flash memory and sram connection (maximum model) sfr area internal ram area external rom area (m5m28f102afp) 0000 16 0080 16 0480 16 1fc0 16 2000 16 1ffff 16 memory map external ram area (m5m5256dp 5 2) 20000 16 2ffff 16 circuit condition : software wait m37721 a 1 ? 7 byte ale a 8 /d 8 ? 15 /d 15 e r/w bhe ble x in x out a 16 /d 0 ? 18 /d 2 address bus data bus (odd) rd we wo dq e e dq ac573 ac573 ac04 ] 3 a y0 b y1 ac139 a 0 ? 14 m5m5256dp-70ll dq 1 ?q 8 s oe a 0 ? 14 m5m5256dp-70ll dq 1 ?q 8 s a 0 ? 15 m5m28f102afp -10 d 0 ? 15 ce oe we ac32 ] 4 ac32 ] 5 d 3 ? 7 ] 1 a 8 ? 16 a 1 ? 15 d 8 ? 15 a 1 ? 15 d 0 ? 7 a 1 ? 16 d 0 ? 15 a 18 a 17 25 mhz ] 1 ] 2 w oe w sfr area external rom area (m5m28f102afp) ] 1, ] 2: make sure that the sum of propagation delay time is within 30 ns. ] 3, ] 4: make sure that the sum of propagation delay time is within 20 ns. ] 5: make sure that the propagation delay time is within 5 ns. data bus (even) fig. 16.1.18 example of flash memory and sram connection (maximum model)
application 7721 group users manual 16C23 16.1 memory connection we, wo t h(e-dlq/dhq) = 18 (min.) (unit : ns) e a 1 ? 7 s aa t w(el) = 135 (min.) ac32(t plh ) ac573(t phl )+ac139(t phl ) t su (d) ]] 3 30 t d(al-e) = 15 (min.) a 8 /d 8 ? 15 /d 15 a 16 /d 0 ? 18 /d 2 d 3 ? 7 a a ac32(t phl ) d t d (e-dlq/dhq) = 35 (max.) ] : specifications of m5m28f102afp-10 ] ] : specifications of m5m5256dp-70ll the others are specifications of m37721. e a 1 ? 7 ce, s external memory data output oe a 8 /d 8 ? 15 /d 15 a 16 /d 0 ? 18 /d 2 d 3 ? 7 aa d t w(el) = 135 (min.) t su(dl/dh-e) 3 30 t a(oe) ]] t su(a-dl/dh) = 130 (max.) t a(ad) ]] +ac573(t phl /t plh ) t df ] /t dis(oe) ]] = 15 (max.) (guaranteed as kit.) ac32(t plh ) ac573(t phl /t plh )+ac139(t phl ) t d(al-e) = 15 (min.) t pzx(e-dlz/dhz) = 20 (min.) aa t a(ce) ] , t a(s) ]] ac32(t phl ) ] ] fig. 16.1.19 timing chart for example of flash memory and sram connection (maximum model)
application 7721 group users manual 16C24 16.1 memory connection (3) example of dram connection (external bus width = 8 bits) dq 1 dq 2 dq 3 dq 4 dq 5 dq 6 dq 7 dq 8 m5m44800cj-7 ma 0 ma 1 ma 2 ma 3 ma 4 ma 5 ma 6 ma 7 ma 8 ma 9 ras cas r/w e a 16 /d 0 a 17 /d 1 a 18 /d 2 a 19 /d 3 a 20 /d 4 a 21 /d 5 a 22 /d 6 a 23 /d 7 byte a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 a 9 ras cas w oe m37721 x in x out 25 mhz ac32 ] 000000 16 000080 16 00047f 16 001fc0 16 001fff 16 f00000 16 ffffff 16 f7ffff 16 sfr area internal ram area dram area (m5m44800cj) memory map circuit condition : dram area select bits (bits 3 to 0 at address 64 16 ) = ?001 2 ] : make sure that the propagation delay time is within 80 ns. sfr area not used not used not used fig. 16.1.20 example of m5m44800cj (512k 5 8 bits) connection (external bus width = 8 bits)
application 7721 group users manual 16C25 16.1 memory connection t w(el) = 135 (min) t w(rasl) = 120 (min) t w(casl) = 92.5 (min) t d(ras-cas) = 28 (min) t w(rash) = 60 (min) t d(e-rasl) = 30 (max) t d(ra-ras) = 5 (min) t d(e-ca) = 60 (max) input data address t oea ] = 20 (max) t rac ] = 70 (max) t clz ] = 5 (min) t cac ] = 20 (max) t su(dl-e) 3 30 t oez ] = 0?0 t pzx(e-dlz) = 20 (min) t d(ca-cas) = 5 (min) t d(e-casl) = 77.5 (max) row address column address e (oe) ras cas ma 0 ?a 9 a 16 /d 0 a 23 /d 7 t aa ] = 35 (max) t w(el) = 135 (min) t w(rasl) = 120 (min) t w(casl) = 55 (min) t w(rash) = 60 (min) t d(r/w-e) = 20 (min) t d(e-casl) = 80?15 e ras cas ma 0 ?a 9 a 16 /d 0 a 23 /d 7 ] : specifications of m5m44800cj-7 the others are specifications of m37721. address data ac32(t phl ) t wcs ] = 0 (min) t wch ] = 15 (min) t d(ra-ras) = 5 (min) t h(ras-ra) = 18 (min) ac32(t phl ) t h(cas-ca) = 60 (min) t d(ca-cas) = 10 (min) t dh ] = 15 (min) t h(e-dlq) = 18 (min) r/w w row address column address (unit : ns) fig. 16.1.21 timing chart for example of m5m44800cj (512k 5 8 bits) connection (external bus width = 8 bits)
application 7721 group users manual 16C26 16.1 memory connection (4) example of dram connection (external bus width = 8 bits) fig. 16.1.22 example of m5m417800cj (2m 5 8 bits) connection (external bus width = 8 bits) 000000 16 000080 16 00047f 16 001fc0 16 001fff 16 e00000 16 ffffff 16 dq 1 dq 2 dq 3 dq 4 dq 5 dq 6 dq 7 dq 8 m5m417800cj-7 ma 0 ma 1 ma 2 ma 3 ma 4 ma 5 ma 6 ma 7 ma 8 ma 9 ras cas r/w e a 16 /d 0 a 17 /d 1 a 18 /d 2 a 19 /d 3 a 20 /d 4 a 21 /d 5 a 22 /d 6 a 23 /d 7 ale a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 a 9 a 10 ras cas oe m37721 x in x out 25 mhz ac32 byte d0 d1 d2 d3 d4 d5 d6 d7 ac573 le oe q4 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 ] 1 ] 2 8 w sfr area internal ram area dram area (m5m417800cj) memory map circuit condition : dram area select bits (bits 3 to 0 at address 64 16 ) = ?010 2 ] 1 : make sure that the propagation delay time is within 80 ns. ] 2 : make sure that the propagation delay time is within 15 ns. sfr area not used not used
application 7721 group users manual 16C27 16.1 memory connection a 10 t asr = 0 (min) ac573 (m5m417800aj) t w(el) = 135 (min) t w(rasl) = 120 (min) t w(casl) = 92.5 (min) t d(ras-cas) = 28 (min) t w(rash) = 60 (min) t d(e-rasl) = 30 (max) t d(ra-ras) = 5 (min) t d(e-ca) = 60 (max) input data address t oea ] = 20 (max) t rac ] = 70 (max) t clz ] = 5 (min) t cac ] = 20 (max) t oez ] = 0C15 t pzx(e-dlz) = 20 (min) t d(ca-cas) = 5 (min) t d(e-casl) = 77.5 (max) row address column address e (oe) ras cas ma 0 Cma 9 a 16 /d 0 C a 23 /d 7 t aa ] = 35 (max) t d(ah-e) = 15 (min) t su(dl-e) 3 30 t w(el) = 135 (min) t w(rasl) = 120 (min) t w(casl) = 55 (min) t w(rash) = 60 (min) t d(r/w-e) = 20 (min) t d(e-casl) = 80C115 e ras cas ma 0 Cma 9 a 16 /d 0 C a 23 /d 7 ] : specifications of m5m417800cj-7 the others are specifications of m37721. address data ac32(t phl ) t wcs ] = 0 (min) t wch ] = 10 (min) t d(ra-ras) = 5 (min) t h(ras-ra) = 18 (min) ac32(t phl ) t h(cas-ca) = 60 (min) t d(ca-cas) = 10 (min) t dh ] = 15 (min) t h(e-dlq) = 18 (min) r/w w row address column address (unit : ns) fig. 16.1.23 timing chart for example of m5m417800cj (2m 5 8 bits) connection (external bus width = 8 bits)
application 7721 group users manual 16C28 16.1 memory connection (5) example of dram connection (external bus width = 8 bits) a fig. 16.1.24 example of m5m44400cj (1m 5 4 bits) connection (external bus width = 8 bits) 000000 16 000080 16 00047f 16 001fc0 16 001fff 16 f00000 16 ffffff 16 m5m44400cj-7 ma 0 ma 1 ma 2 ma 3 ma 4 ma 5 ma 6 ma 7 ma 8 ma 9 ras cas r/w e a 16 /d 0 a 17 /d 1 a 18 /d 2 a 19 /d 3 a 20 /d 4 a 21 /d 5 a 22 /d 6 a 23 /d 7 m37721 dq 1 dq 2 dq 3 dq 4 a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 a 9 ras cas w oe x in x out 25 mhz ac32 ma 0 ma 1 ma 2 ma 3 ma 4 ma 5 ma 6 ma 7 ma 8 ma 9 10 ras cas oe 4 w ras cas w e dq 1 dq 2 dq 3 dq 4 a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 a 9 byte m5m44400cj-7 ] sfr area internal ram area dram area (m5m44400cj 5 2) memory map circuit condition : dram area select bits (bits 3 to 0 at address 64 16 ) = 0001 2 ] : make sure that the propagation delay time is within 80 ns. sfr area not used not used
application 7721 group users manual 16C29 16.1 memory connection fig. 16.1.25 timing chart for example of m5m44400cj (1m 5 4 bits) connection (external bus width = 8 bits) e (oe) ras cas ma 0 Cma 9 a 16 /d 0 C a 23 /d 7 t w(el) = 135 (min) t w(rasl) = 120 (min) t w(casl) = 92.5 (min) t d(ras-cas) = 28 (min) t w(rash) = 60 (min) t d(e-rasl) = 30 (max) t d(ra-ras) = 5 (min) t d(e-ca) = 60 (max) input data address t oea ] = 20 (max) t rac ] = 70 (max) t clz ] = 5 (min) t cac ] = 20 (max) t pzx(e-dlz) = 20 (min) t d(ca-cas) = 5 (min) t d(e-casl) = 77.5 (max) row address column address t aa ] = 35 (max) t su(dl-e) 3 30 t oez ] = 0C20 t w(el) = 135 (min) t w(rasl) = 120 (min) t w(casl) = 55 (min) t w(rash) = 60 (min) t d(r/w-e) = 20 (min) t d(e-casl) = 80C115 ma 0 Cma 9 a 16 /d 0 C a 23 /d 7 ] : specifications of m5m44400cj-7 the others are specifications of m37721. address data ac32(t phl ) t wcs ] = 0 (min) t wch ] = 15 (min) t d(ra-ras) = 5 (min) t h(ras-ra) = 18 (min) ac32(t phl ) t h(cas-ca) = 60 (min) t d(ca-cas) = 10 (min) t dh ] = 15 (min) t h(e-dlq) = 18 (min) row address column address (unit : ns) e ras cas r/w w
application 7721 group users manual 16C30 16.1 memory connection (6) example of dram connection (external bus width = 16 bits) 000000 16 000080 16 00047f 16 001fc0 16 001fff 16 e00000 16 ffffff 16 dq 1 dq 2 dq 3 dq 4 dq 5 dq 6 dq 7 dq 8 dq 9 dq 10 dq 11 dq 12 dq 13 dq 14 dq 15 dq 16 m5m418160cj-7 ma 0 ma 1 ma 2 ma 3 ma 4 ma 5 ma 6 ma 7 ma 8 ma 9 ras a 16 /d 0 a 17 /d 1 a 18 /d 2 a 19 /d 3 a 20 /d 4 a 21 /d 5 a 22 /d 6 a 23 /d 7 a 8 /d 8 a 9 /d 9 a 10 /d 10 a 11 /d 11 a 12 /d 12 a 13 /d 13 a 14 /d 14 a 15 /d 15 a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 a 9 ras m37721 ac32 byte x in x out 25 mhz bhe ] 2 st0 st1 cas ble e r/w ac157 1a 1b 2a 2b select 1y 2y st lcas ucas oe w ] 1 sfr area internal ram area dram area (m5m418160cj) circuit condition : dram area select bits (bits 3 to 0 at address 64 16 ) = 0010 2 ] 1 : make sure that the propagation delay time is within 20 ns. ] 2 : make sure that the propagation delay time is within 7.5 ns. sfr area not used not used memory map fig. 16.1.26 example of m5m418160cj (1m 5 16 bits) connection (external bus width = 16 bits)
application 7721 group users manual 16C31 16.1 memory connection fig. 16.1.27 timing chart for example of m5m418160cj (1m 5 16 bits) connection (external bus width = 16 bits) t dh ] = 15 (min) + ac157(t phl ) t clz ] = 5 (min) + ac157 (t phl ) t w(el) = 135 (min) t w(rasl) = 120 (min) t w(casl) = 92.5 (min) t d(ras-cas) = 28 (min) t w(rash) = 60 (min) t d(e-rasl) = 30 (max) t d(ra-ras) = 5 (min) t d(e-ca) = 60 (max) input data address t oea ] = 20 (max) t rac ] = 70 (max) t su(dl/dh-e) 3 30 t oez ] = 0C15 t pzx(e-dlz/dhz) = 20 (min) t d(ca-cas) = 5 (min) t d(e-casl) = 77.5 (max) row address e (oe) ras cas ma 0 Cma 9 a 16 /d 0 Ca 23 /d 7, a 8 /d 8 Ca 15 /d 15 t aa ] = 35 (max) t w(el) = 135 (min) t w(rasl) = 120 (min) t w(casl) = 55 (min) t w(rash) = 60 (min) t d(r/w-e) = 20 (min) t d(e-casl) = 80C115 e ras cas row column address ma 0 Cma 9 address data ac32(t phl ) t wcs ] = 0 (min) t wch ] = 10 (min) t d(ra-ras) = 5 (min) t h(ras-ra) = 18 (min) ac32(t phl ) t h(cas-ca) = 60 (min) t d(ca-cas) = 10 (min) t h(e-dlq/dhq) = 18 (min) r/w w a 16 /d 0 Ca 23 /d 7, a 8 /d 8 Ca 15 /d 15 ble/bhe t d(ble/bhe-e) = 20 (min) ble/bhe t d(ble/bhe-e) = 20 (min) column address ] : specifications of m5m418160cj-7 the others are specifications of m37721. (unit : ns) t cac ] = 20 (max) + ac157 (t phl ) address
application 7721 group users manual 16C32 16.1 memory connection (7) example of dram connection (external bus width = 16 bits) 000000 16 000080 16 00047f 16 001fc0 16 001fff 16 f00000 16 ffffff 16 f7ffff 16 m5m44170cj-7 ma 0 ma 1 ma 2 ma 3 ma 4 ma 5 ma 6 ma 7 a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 a 9 ras cas oe m37721 x in x out 25 mhz ras cas e a 16 /d 0 a 17 /d 1 a 18 /d 2 a 19 /d 3 a 20 /d 4 a 21 /d 5 a 22 /d 6 a 23 /d 7 ale a 8 /d 8 a 9 /d 9 a 10 /d 10 a 11 /d 11 a 12 /d 12 a 13 /d 13 a 14 /d 14 a 15 /d 15 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 ] 2 ac573 le 8 ac32 wl wh q2 q1 byte dq 1 dq 2 dq 3 dq 4 dq 5 dq 6 dq 7 dq 8 dq 9 dq 10 dq 11 dq 12 dq 13 dq 14 dq 15 dq 16 lw uw ble bhe r/w ] 1 d0 d1 d2 d3 d4 d5 d6 d7 oe sfr area internal ram area dram area (m5m44170cj) sfr area not used not used memory map not used circuit condition : dram area select bits (bits 3 to 0 at address 64 16 ) = 0001 2 ] 1 : make sure that the propagation delay time is within 40 ns. ] 2 : make sure that the propagation delay time is within 15 ns. fig. 16.1.28 example of m5m44170cj (256k 5 16 bits) connection (external bus width = 16 bits)
application 7721 group users manual 16C33 16.1 memory connection fig. 16.1.29 timing chart for example of m5m44170cj (256k 5 16 bits) connection (external bus width = 16 bits) ble/bhe t asr = 0 (min) ac573 (m5m44170aj) a 8, a 9 e (oe) ras cas ma 0 Cma 7 a 16 /d 0 Ca 23 /d 7 , a 8 /d 8 Ca 15 /d 15 t w(el) = 135 (min) t w(rasl) = 120 (min) t w(casl) = 92.5 (min) t d(ras-cas) = 28 (min) t w(rash) = 60 (min) t d(e-rasl) = 30 (max) t d(ra-ras) = 5 (min) t d(e-ca) = 60 (max) input data address t oea ] = 20 (max) t rac ] = 70 (max) t clz ] = 5 (min) t cac ] = 20 (max) t pzx(e-dlz/dhz) = 20 (min) t d(ca-cas) = 5 (min) t d(e-casl) = 77.5 (max) row address column address t aa ] = 35 (max) t su(dl/dh-e) 3 30 t oez ] = 0C20 t d(ah-e) = 15 (min) t w(el) = 135 (min) t w(rasl) = 120 (min) t w(casl) = 55 (min) t w(rash) = 60 (min) t d(r/w-e) = 20 (min) t d(e-casl) = 80C115 ma 0 Cma 9 a 16 /d 0 Ca 23 /d 7 , a 8 /d 8 Ca 15 /d 15 ] : specification of m5m44170cj-7 the others are specifications of m37721. address data ac32(t phl ) 5 2 t wcs ] = 0 (min) t wch ] = 15 (min) t d(ra-ras) = 5 (min) t h(ras-ra) = 18 (min) ac32(t phl ) 5 2 t h(cas-ca) = 60 (min) t d(ca-cas) = 10 (min) t dh ] = 15 (min) t h(e-dlq/dhq) = 18 (min) row address column address e ras cas r/w wl/wh t d(ble/bheCe) = 20 (min) (unit : ns)
application 7721 group users manual 16C34 16.1 memory connection (8) example of dram connection (external bus width = 16 bits) a 000000 16 000080 16 00047f 16 001fc0 16 001fff 16 e00000 16 ffffff 16 ma 0 ma 1 ma 2 ma 3 ma 4 ma 5 ma 6 ma 7 ma 8 ma 9 ras cas e m37721 m5m417800cj-7 a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 a 9 a 10 ras cas oe w 10 ras cas oe 4 w a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 a 9 a 10 dq 1 dq 2 dq 3 dq 4 dq 5 dq 6 dq 7 dq 8 d 8 d 9 d 10 d 11 d 12 d 13 d 14 d 15 x in x out 25 mhz byte a 16 /d 0 a 17 /d 1 a 18 /d 2 a 19 /d 3 a 20 /d 4 a 21 /d 5 a 22 /d 6 a 23 /d 7 ale a 8 /d 8 a 9 /d 9 a 10 /d 10 a 11 /d 11 a 12 /d 12 a 13 /d 13 a 14 /d 14 a 15 /d 15 ] 2 d0 d1 d2 d3 d4 d5 d6 d7 ac573 le oe 8 q4 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 m5m417800cj-7 ac32 wl wh ] 1 r/w ble bhe dq 1 dq 2 dq 3 dq 4 dq 5 dq 6 dq 7 dq 8 sfr area internal ram area dram area (m5m417800cj 5 2) ] 1 : make sure that the propagation delay time is within 40 ns. ] 2 : make sure that the propagation delay time is within 15 ns. sfr area not used not used memory map circuit condition : dram area select bits (bits 3 to 0 at address 64 16 ) = 0010 2 fig. 16.1.30 example of m5m417800cj (2m 5 8 bits) connection (external bus width = 16 bits)
application 7721 group users manual 16C35 16.1 memory connection fig. 16.1.31 timing chart for example of m5m417800cj (2m 5 8 bits) connection (external bus width = 16 bits) w t asr = 0 (min) ac573 (m5m417800aj) a 10 e (oe) ras cas ma 0 Cma 9 a 16 /d 0 Ca 23 /d 7 , a 8 /d 8 Ca 15 /d 15 t w(el) = 135 (min) t w(rasl) = 120 (min) t w(casl) = 92.5 (min) t d(ras-cas) = 28 (min) t w(rash) = 60 (min) t d(e-rasl) = 30 (max) t d(ra-ras) = 5 (min) t d(e-ca) = 60 (max) input data address t oea ] = 20 (max) t rac ] = 70 (max) t clz ] = 5 (min) t cac ] = 20 (max) t pzx(e-dlz/dhz) = 20 (min) t d(ca-cas) = 5 (min) t d(e-casl) = 77.5 (max) row address column address t aa ] = 35 (max) t su(dl/dh-e) 3 30 t d(ah-e) = 15 (min) t oez ] = 0C15 t w(el) = 135 (min) t w(rasl) = 120 (min) t w(casl) = 55 (min) t w(rash) = 60 (min) t d(r/w-e) = 20 (min) t d(e-casl) = 80C115 ma 0 Cma 9 a 16 /d 0 Ca 23 /d 7 , a 8 /d 8 Ca 15 /d 15 ] : specifications of m5m417800cj-7 the others are specifications of m37721. address data ac32(t phl ) t wcs ] = 0 (min) t wch ] = 10 (min) t d(ra-ras) = 5 (min) t h(ras-ra) = 18 (min) ac32(t phl ) t h(cas-ca) = 60 (min) t d(ca-cas) = 10 (min) t dh ] = 15 (min) t h(e-dlq/dhq) = 18 (min) row address column address e ras cas r/w (unit : ns)
application 7721 group users manual 16C36 16.1 memory connection (9) example of dram connection (external bus width = 16 bits) ? 000000 16 000080 16 00047f 16 001fc0 16 001fff 16 e00000 16 ffffff 16 m5m44400cj-7 ma 0 ma 1 ma 2 ma 3 ma 4 ma 5 ma 6 ma 7 ma 8 ma 9 ras cas e r/w ble a 16 /d 0 a 17 /d 1 a 18 /d 2 a 19 /d 3 a 20 /d 4 a 21 /d 5 a 22 /d 6 a 23 /d 7 a 8 /d 8 a 9 /d 9 a 10 /d 10 a 11 /d 11 a 12 /d 12 a 13 /d 13 a 14 /d 14 a 15 /d 15 m37721 ac32 wl wh bhe x in x out 25 mhz byte a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 a 9 ras cas oe a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 a 9 ras cas oe a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 a 9 ras cas oe a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 a 9 ras cas oe w dq 1 dq 2 dq 3 dq 4 a 16 /d 0 a 17 /d 1 a 18 /d 2 a 19 /d 3 a 20 /d 4 a 21 /d 5 a 22 /d 6 a 23 /d 7 a 8 /d 8 a 9 /d 9 a 10 /d 10 a 11 /d 11 a 12 /d 12 a 13 /d 13 a 14 /d 14 a 15 /d 15 ] w dq 1 dq 2 dq 3 dq 4 w dq 1 dq 2 dq 3 dq 4 w dq 1 dq 2 dq 3 dq 4 sfr area internal ram area dram area (m5m4400cj 5 4) ] : make sure that the propagation delay time is within 40 ns. sfr area not used not used memory map circuit condition : dram area select bits (bits 3 to 0 at address 64 16 ) = 0010 2 fig. 16.1.32 example of m5m44400cj (1m 5 4 bits) connection (external bus width = 16 bits)
application 7721 group users manual 16C37 16.1 memory connection fig. 16.1.33 timing chart for example of m5m44400cj (1m 5 4 bits) connection (external bus width = 16 bits) e (oe) ras cas ma 0 Cma 9 a 16 /d 0 Ca 23 /d 7 , a 8 /d 8 Ca 15 /d 15 t w(el) = 135 (min) t w(rasl) = 120 (min) t w(casl) = 92.5 (min) t d(ras-cas) = 28 (min) t w(rash) = 60 (min) t d(e-rasl) = 30 (max) t d(ra-ras) = 5 (min) t d(e-ca) = 60 (max) input data address t oea ] = 20 (max) t rac ] = 70 (max) t clz ] = 5 (min) t cac ] = 20 (max) t pzx(e-dlz/dhz) = 20 (min) t d(ca-cas) = 5 (min) t d(e-casl) = 77.5 (max) row address column address t aa ] = 35 (max) t su(dl/dh-e) 3 30 t oez ] = 0C20 t w(el) = 135 (min) t w(rasl) = 120 (min) t w(casl) = 55 (min) t w(rash) = 60 (min) t d(r/w-e) = 20 (min) t d(e-casl) = 80C115 ma 0 Cma 9 a 16 /d 0 Ca 23 /d 7 , a 8 /d 8 Ca 15 /d 15 ] : specifications of m5m44400cj-7 the others are specifications of m37721. address data ac32(t phl ) 5 2 t wcs ] = 0 (min) t wch ] = 1 0 (min) t d(ra-ras) = 5 (min) t h(ras-ra) = 18 (min) ac32(t phl ) 5 2 t h(cas-ca) = 60 (min) t d(ca-cas) = 10 (min) t dh ] = 15 (min) t h(e-dlq/dhq) = 18 (min) row address column address e ras cas r/w wl/wh ble/bhe t d(ble/bheCe) = 20 (min) (unit : ns)
application 7721 group users manual 16C38 16.1 memory connection (10) example of dram connection (external bus width = 16 bits) ? ac157 000000 16 000080 16 00047f 16 001fc0 16 001fff 16 f00000 16 ffffff 16 f7ffff 16 m5m44260cj-7 ma 0 ma 1 ma 2 ma 3 ma 4 ma 5 ma 6 ma 7 ma 8 ras cas m37721 a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 ras ac32 1a 1y ] 2 2a 2b select 2y st lcas ucas oe w 1b ble bhe st0 st1 e r/w byte 25 mhz ] 1 sfr area internal ram area dram area (m5m44260cj) ] 1 : make sure that the propagation delay time is within 20 ns. ] 2 : make sure that the propagation delay time is within 7.5 ns. sfr area not used not used memory map circuit condition : dram area select bits (bits 3 to 0 at address 64 16 ) = ?001 2 not used a 16 /d 0 a 17 /d 1 a 18 /d 2 a 19 /d 3 a 20 /d 4 a 21 /d 5 a 22 /d 6 a 23 /d 7 a 8 /d 8 a 9 /d 9 a 10 /d 10 a 11 /d 11 a 12 /d 12 a 13 /d 13 a 14 /d 14 a 15 /d 15 dq 1 dq 2 dq 3 dq 4 dq 5 dq 6 dq 7 dq 8 dq 9 dq 10 dq 11 dq 12 dq 13 dq 14 dq 15 dq 16 x in x out fig. 16.1.34 example of m5m44260cj (256k 5 16 bits) connection (external bus width = 16 bits)
application 7721 group users manual 16C39 16.1 memory connection fig. 16.1.35 timing chart for example of m5m44260cj (256k 5 16 bits) connection (external bus width = 16 bits) t dh ] = 15 (min) + ac157(t phl ) t clz ] = 5 (min) + ac157 (t phl ) t w(el) = 135 (min) t w(rasl) = 120 (min) t w(casl) = 92.5 (min) t d(ras-cas) = 28 (min) t w(rash) = 60 (min) t d(e-rasl) = 30 (max) t d(ra-ras) = 5 (min) t d(e-ca) = 60 (max) input data address t oea ] = 20 (max) t rac ] = 70 (max) t su(dl/dh-e) 3 30 t oez ] = 0C20 t pzx(e-dlz/dhz) = 20 (min) t d(ca-cas) = 5 (min) t d(e-casl) = 77.5 (max) row address e (oe) ras ma 0 Cma 8 a 16 /d 0 Ca 23 /d 7, a 8 /d 8 Ca 15 /d 15 t aa ] = 35 (max) t w(el) = 135 (min) t w(rasl) = 120 (min) t w(casl) = 55 (min) t w(rash) = 60 (min) t d(r/w-e) = 20 (min) t d(e-casl) = 80C115 e ras cas row column address ma 0 Cma 8 address data ac32(t phl ) t wcs ] = 0 (min) t wch ] = 15 (min) t d(ra-ras) = 5 (min) t h(ras-ra) = 18 (min) ac32(t phl ) t h(cas-ca) = 60 (min) t d(ca-cas) = 10 (min) t h(e-dlq/dhq) = 18 (min) r/w w a 16 /d 0 Ca 23 /d 7, a 8 /d 8 Ca 15 /d 15 ble/bhe t d(ble/bhe-e) = 20 (min) ble/bhe t d(ble/bhe-e) = 20 (min) column address ] : specifications of m5m44260cj-7 the others are specification of m37721. (unit : ns) t cac ] = 20 (max) + ac157 (t phl ) cas address
application 7721 group users manual 16C40 16.1 memory connection 16.1.4 example of i/o expansion (1) example of port expansion circuit using m66010fp figure 16.1.36 shows an example of a port expansion circuit using the m66010fp. make sure that the frequency of serial i/o transfer clock must be 1.923 mhz or less. about serial i/o control in this expansion example is described below. in this example, 8-bit data transmission/reception is performed 3 times by using uart0, so that 24- bit port expansion is realized. setting of uart0 is described below: l clock synchronous serial i/o mode: transmission/reception enable state l internal clock is selected. transfer clock frequency is 1.66 mhz. l lsb first the control procedure is described below: output l level from port p4 5 . (expanded i/o ports of the m66010fp enter a floating state by this signal. ) output h level from port p4 5 . a output l level from port p4 4 . ? transmit/receive 24-bit data by using uart0. ? output h level from port p4 4 . figure 16.1.37 shows the serial transfer timing between the m37721 and the m66010fp.
application 7721 group users manual 16C41 16.1 memory connection d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 d16 d17 d18 d19 d20 d21 d22 d23 d24 m66010fp txd 0 rxd 0 clk 0 p4 4 p4 5 rts 0 a 0 Ca 7 a 8 /d 8 Ca 15 /d 15 a 16 /d 0 Ca 23 /d 7 ale e 1 r/w bhe ble m37721 di do clk cs s vcc gnd byte 25 mhz open x in x out expanded input ports circuit conditions: ?uart0 used in clock synchronous serial i/o mode ?internal clock selected ?frequency of transfer clock = f 2 2 (3 + 1) = 1.5625 mhz fig. 16.1.36 example of port expansion circuit using m66010fp
application 7721 group users manual 16C42 16.1 memory connection fig. 16.1.37 serial transfer timing between m37721 and m66010fp do1 do2 do3 do4 do5 do6 do7 do8 do20 do21 do22 do23 do24 di1 di2 di3 di4 di5 di6 di7 di8 di20 di21 di22 di23 di24 di1 di2 di24 s cs clk di do expanded i/o port do24 do2 do1 d1 d2 d24 p4 5 p4 4 clk 0 t x d 0 r x d 0 expanded i/o port expanded i/o port expanded i/o ports are released from floating state. data of expanded i/o ports is output to shift register 1. serial data is input to shift register 2. data of shift register 1 is output in serial. ] output structure of expanded i/o ports is n-channel open-drain output. : m37721s pin name the others are m66010fps pins names or operations. data of shift register 2 is output to expanded i/o ports. to
application 7721 group users manual 16C43 16.2 examples of using dma controller 16.2 examples of using dma controller 16.2.1 example of centronics interface configuration the following is an example of centronics interface configurated by using dma0, timers a2 and a3. (1) specifications ?octal latchs contents are transferred to the data buffer (ram) by using dma0. the trigger is the ____ stb signal. (refer to figure 16.2.1. ) ____ ?l level width of the ack signal is generated by using timer a2; one-shot pulse mode; the trigger _________ is the rising edge of the dmaack0 signal. (refer to figure 16.2.2. ) ____ ?timer a3 generates the time from when the ack signal rises until the busy signal falls; one-shot _________ pulse mode; the trigger is the rising edge of the dmaack0 signal. (refer to figure 16.2.2. ) ?p4 3 is used for busy signal generation. when outputting h level, the next transfer can wait. in that case, the contents of the preceding transfer are hold in the octal latch. ?when the data buffer is filled (in other words, dma transfer is completed), a dma interrupt occurs.
application 7721 group users manual 16C44 16.2 examples of using dma controller fig. 16.2.1 example of centronics interface configuration data bus dmareq0 ta3 out (one-shot output) ta3 in dmaack0 ta2 in p4 3 ta2 out (one-shot output) m37721 octal latch ac574 oc t q d s t data d-f/f cs rd stb busy ack x in x out 25 mhz dmaack0 ta2 out ta3 out ack busy t2 t3 t2 : timer a2? set time t3 : timer a3? set time ____ fig. 16.2.2 relationship between ack and busy
application 7721 group users manual 16C45 16.2 examples of using dma controller (2) initial setting example for relevant register b7 b0 port p4 register (address a 16 ) p4 3 output : h level 1 ta3 out output : h level (d-f/f initialized) b7 b0 1 b7 b0 p4 3 : output mode 1 b7 b0 b7 b0 dmareq0 pin : input mode 0 b7 b0 transfer source wait transfer destination wait single transfer mode 5 0 000000 5 : it may be 0 or 1. b7 b0 dma0 mode register l (address 1fcc 16 ) transfer unit : 8 bits 2-bus cycle transfer cycle-steal transfer mode transfer source address direction : fixed transfer destination address direction : forward 0 1 010001 ta2 in pin : input mode 1 00 port p5 register (address b 16 ) port p4 direction register (address c 16 ) port p5 direction register (address d 16 ) ta3 in pin : input mode ta3 out pin : output mode (dCf/f initialized) port p9 direction register (address 15 16 ) dma0 mode register h (address 1fcd 16 ) fig. 16.2.3 initial setting example for relevant register (1)
application 7721 group users manual 16C46 16.2 examples of using dma controller fig. 16.2.4 initial setting example for relevant register (2) period from falling edge of ack signal until falling edge of busy signal (t3 in figure 16.2.2) octal latchs address b23 b0 b16 b15 b8 b7 data buffers start address b23 b0 b16 b15 b8 b7 transfer counter register 0 (addresses 1fca 16 to 1fc8 16 ) data buffer size (unit : byte) b23 b0 b16 b15 b8 b7 b7 b0 timer a2 mode register (address 58 16 ) one-shot pulse mode trigger : rising edge of ta2 in pins input signal count source 11 0 01 1 b7 b0 11 0 01 1 ack signals l level time (t2 in figure 16.2.2) b15 b0 b8 b7 b15 b0 b8 b7 source address register 0 (addresses 1fc2 16 to 1fc0 16 ) destination address register 0 (addresses 1fc6 16 to 1fc4 16 ) timer a3 mode register (address 59 16 ) one-shot pulse mode trigger : rising edge of ta3 in pins input signal count source timer a2 register (addresses 4b 16 , 4a 16 ) timer a3 register (addresses 4d 16 , 4c 16 )
application 7721 group users manual 16C47 16.2 examples of using dma controller b7 b0 p4 3 output : l level 0 b7 b0 dma0 enabled 1 b7 b0 timer a2 count start timer a3 count start 1 1 b7 b0 dma0 request flag is set to ?. 0 b7 b0 dma0 control register (address 1fce 16 ) dma request source : external source (dmareq0) edge sense selected dmaack0 pin : valid 0 1 1000 b7 b0 dma0 interrupt control register (address 6c 16 ) interrupt priority level : any of ?01 2 ?to ?11 2 0 count start register (address 40 16 ) dmac control register l (address 68 16 ) dmac control register h (address 69 16 ) port p4 register (address a 16 ) fig. 16.2.5 initial setting example for relevant register (3)
application 7721 group users manual 16C48 16.2 examples of using dma controller 16.2.2 example of stepping motor control the following is an example where the slow-up or slow-down control for the stepping motor is performed by using dma1, dma2, and rtp0. (1) specifications ?dma1 transfers the stepping motors phase output data from the phase output data table to the rtp0 pulse output data register. (refer to figure 16.2.6 and table 16.2.1. ) ?dma2 transfers the step time for slow up or slow down from the timer a0 set value data table to the timer a0 register. (refer to figure 16.2.6. ) after slow up or slow down is completed, a dma2 interrupt occurs. ?phase output is performed by rtp0; pulse output mode 0 (refer to figures 16.2.6 and 16.2.7. ) ?after slow up or slow down is completed, the motor operates with the definite rate. m37721 rom rtp0 timer a0 stepping motor phase output data table dmac1 dmac2 bus aaaaaa aaaaaa m aaaaaa aaaaaa aaaaaa timer a0 set value data table motor driver fig. 16.2.6 example of stepping motor control
application 7721 group users manual 16C49 16.2 examples of using dma controller table 16.2.1 example of phase output data table 2-2 phase 0011 1001 1100 0110 0011 1001 1100 0110 1-2 phase 0011 0001 1001 1000 1100 0100 0110 0010 0 1 2 3 4 5 6 7 fig. 16.2.7 example of phase output 0 1234567 step phase 2-2 phase rtp0 3 rtp0 2 rtp0 1 rtp0 0 rtp0 3 rtp0 2 rtp0 1 rtp0 0 1-2 phase
application 7721 group users manual 16C50 16.2 examples of using dma controller (2) initial setting example for relevant register b7 b0 dma1 mode register l (address 1fdc 16 ) transfer unit : 8 bits 2-bus cycle transfer cycle-steal transfer mode transfer source address direction : at regular turning ; ?1 2 ?(forward) at reverse turning ; ?0 2 ?(backward) transfer destination address direction : fixed 0 1 00 01 b7 b0 dma1 mode register h (address 1fdd 16 ) transfer source wait no transfer destination wait repeat transfer mode 0 011000 source address register 1 (addresses 1fd2 16 to 1fd0 16 ) phase output data table? start address b23 b0 b16 b15 b8 b7 phase output data table? data number b23 b0 b16 b15 b8 b7 pulse output data register 0? address b23 b0 b16 b15 b8 b7 00 16 00 16 1a 16 b7 b0 dma1 control register (address 1fde 16 ) dma request source : timer a0 dmaack1 pin : invalid 1 1 0000 b7 b0 dma1 interrupt control register (address 6d 16 ) interrupt disabled 000 5 destination address register 1 (addresses 1fd6 16 to 1fd4 16 ) transfer counter register 1 (addresses 1fda 16 to 1fd8 16 ) 5 : it may be ??or ?.? fig. 16.2.8 initial setting example for relevant register (1)
application 7721 group users manual 16C51 16.2 examples of using dma controller b7 b0 dma2 mode register l (address 1fec 16 ) transfer unit : 16 bits 2-bus cycle transfer cycle-steal transfer mode transfer source address direction : at slow up; ?1 2 ?(forward) at slow down; ?0 2 ?(backward) transfer destination address direction : fixed 0 0 00 01 b7 b0 dma2 mode register h (address 1fed 16 ) transfer source wait no transfer destination wait single transfer mode 5 0 001000 source address register 2 (addresses 1fe2 16 to 1fe0 16 ) timer a0 set value data table? start address b23 b0 b16 b15 b8 b7 timer a0 register? address b23 b0 b16 b15 b8 b7 00 16 00 16 46 16 b23 b0 b16 b15 b8 b7 b7 b0 dma2 control register (address 1fee 16 ) dma request source : timer a0 dmaack2 pin : invalid 1 1 0000 b7 b0 dma2 interrupt control register (address 6e 16 ) interrupt priority level : any of ?01 2 ?to ?11 2 0 destination address register 2 (addresses 1fe6 16 to 1fe4 16 ) transfer counter register 2 (addresses 1fea 16 to 1fe8 16 ) data number of timer a0 set value data table 5 : it may be ??or ?. fig. 16.2.9 initial setting example for relevant register (2)
application 7721 group users manual 16C52 16.2 examples of using dma controller fig. 16.2.10 initial setting example for relevant register (3) dma1 request bit dma2 request bit b7 b0 port p6 register (address e 16 ) rtp0 0 /p6 0 ?tp0 3 /p6 3 initial output : h level 1111 b7 b0 1111 b7 b0 count source 000 00 b7 b0 rtp0 pulse mode 0 001 timer a0 register (addresses 47 16 , 46 16 ) first step time b15 b0 b8 b7 b7 b0 first phase output data b7 b0 timer a0 count start 1 dma1 enabled dma2 enabled b7 b0 1 1 b7 b0 0 0 are set to ?.? port p6 direction register (address 10 16 ) rtp0 0 /p6 0 ?tp0 3 /p6 3 pin : output mode pulse output data register 0 (address 1a 16 ) 5 timer a0 mode register (address 56 16 ) real-time output control register (address 62 16 ) count start register (address 40 16 ) dmac control register l (address 68 16 ) dmac control register h (address 69 16 ) 5 : it may be ??or ?.?
application 7721 group users manual 16C53 16.2 examples of using dma controller 16.2.3 example of dynamic lighting for led the following is an example of dynamic lighting for led by using dma3 and timer b0. (1) specifications ?the eight 7-segment leds are lighted up; port p6 outputs the segment data; port p7 outputs the digit data. (refer to figure 16.2.11. ) ?the display data and the segment data are transferred from the data buffer to the port p6 and p7 registers by dma3. ?digit switch interval is generated by timer b0. ?16 bytes of ram are used as the data buffer. 1-digit display data consists of 2 bytes; the digit data is placed in the high-order byte; the segment data is placed in the low-order byte. (refer to table 16.2.2. ) when the digit data and segment data are 0, the led is lighted up (on): when they are 1, the light goes out (off). assuming that the segment pattern is generated by another processing. m37721 led driver data buffer p6 7 p6 0 p7 7 p7 0 7-segment led 5 8 led driver data buffer digit data 00000001 00000010 00000100 00001000 00010000 00100000 01000000 10000000 segment pattern of the contents to be displayed in each digit segment pattern fig. 16.2.11 example of dynamic lighting for led table 16.2.2 data buffer notes 1: this applies in the following: ?when the digit data is 0, the light goes out. ?when the digit data is 1, the led is lighted up. 2: assuming that the segment pattern is generated by another processing.
application 7721 group users manual 16C54 16.2 examples of using dma controller b7 b0 5 0 011100 b23 b0 b16 b15 b8 b7 b23 b0 b16 b15 b8 b7 00 16 00 16 0e 16 b7 b0 0 0 0010 b7 b0 0 0 00 01 01 b7 b0 0 00 b23 b0 b16 b15 b8 b7 00 16 00 16 10 16 dma3 mode register l (address 1ffc 16 ) transfer unit : 16 bits 2-bus cycle transfer cycle-steal transfer mode transfer source address direction : forward transfer destination address direction : fixed dma3 mode register h (address 1ffd 16 ) no transfer source wait no transfer destination wait repeat transfer mode source address register 3 (addresses 1ff2 16 to 1ff0 16 ) data buffers start address port p6, p7 registers address destination address register 3 (addresses 1ff6 16 to 1ff4 16 ) transfer counter register 3 (addresses 1ffa 16 to 1ff8 16 ) data number (unit : byte) dma3 control register (address 1ffe 16 ) dma request source : timer b0 dmaack3 pin : invalid dma3 interrupt control register (address 6f 16 ) interrupt disabled 5 : it may be 0 or 1. fig. 16.2.12 initial setting example for relevant register (1)
application 7721 group users manual 16C55 16.2 examples of using dma controller b7 b0 dma3 enabled 1 b7 b0 1 b7 b0 dma3 request bit : ? 0 digit switch interval b15 b0 b8 b7 b7 b0 port p6 register (address e 16 ) output : l level (lights go out.) 0000 0000 b7 b0 0000 0000 b7 b0 output mode 1111 1111 b7 b0 1111 1111 b7 b0 timer mode count source 00 b7 b0 interrupt disabled 000 port p7 register (address f 16 ) output : l level (all digits off) port p6 direction register (address 10 16 ) port p7 direction register (address 11 16 ) output mode timer b0 register (addresses 51 16 , 50 16 ) 555 timer b0 mode register (address 5b 16 ) timer b0 interrupt control register (address 7a 16 ) count start register (address 40 16 ) timer b0 count started dmac control register l (address 68 16 ) dmac control register h (address 69 16 ) 5 : it may be ??or ?. fig. 16.2.13 initial setting example for relevant register (2)
application 7721 group users manual 16C56 16.3 comparison of sample program execution rate 16.3 comparison of sample program execution rate sample program execution rates are compared in this paragraph. the execution time ratio depends on the program or the usage conditions. 16.3.1 differences depending on data bus width and software wait internal areas are always accessed with data bus of which width is 16 bits and no software wait. in the external areas, the external data bus width and software wait are selectable. table 16.3.1 lists the sample program (refer to figure 16.3.1. ) execution time ratio depending on these selection and usable memory areas. table 16.3.1 sample program execution time ratio (external data bus width and software wait) sample program execution time ratio sample a 1.00 1.17 1.19 1.67 1.00 1.25 1.19 1.78 0.92 sample b 1.00 1.10 1.08 1.46 1.00 1.17 1.13 1.65 0.90 external data bus width (unit : bit) 16 8 16 8 memory area rom external internal ram internal external software wait none inserted none inserted none inserted none inserted calculated value ] calculated value ] : the value is calculated from the shortest execution cycle number of each instruction described in 7700 family software manual.
application 7721 group users manual 16C57 16.3 comparison of sample program execution rate sep m,x lda.b a,#0 sta a,dest+64 sta a,dest+65 sta a,dest+66 ldx.b #63 lda a,sour,x tay and.b a,#00000011b sta a,dest,x tya and.b a,#00001100b ora a,dest+1,x sta a,dest+1,x tya and.b a,#00110000b ora a,dest+2,x sta a,dest+2,x tya and.b a,#11000000b ora a,dest+3,x sta a,dest+3,x dex bpl italic italic: sep x clm .data 16 .index 8 ldy #69 ldx #69 asl sour,x sem .data 8 rol sour+2,x rol b clm .data 16 ror a dex dex dex bne loop1 sta a,dest,y sem .data 8 sta b,dest+2,y clm .data 16 dey dey dey bne loop0 loop0: loop1: sample a sample b ] sour, dest : work area (direct page area : access this area by using the following modes.) ?irect addressing mode ?irect indexed x addressing mode ?bsolute indexed y addressing mode fig. 16.3.1 sample program list
application 7721 group users manual 16C58 16.3 comparison of sample program execution rate 16.3.2 comparison between software wait (f(x in ) = 20 mhz) and software wait + ready (f(x in ) = 25 mhz) figure 16.3.3 shows the execution time ratio when sample programs in figure 16.3.1 are executed on the two conditions in table 16.3.2. figure 16.3.2 shows the memory assignment at execution rate comparison. the execution time ratio depends on the program or the usage conditions. table 16.3.2 comparison conditions fig. 16.3.2 memory assignment at execution rate comparison external sram sfr area condition ready valid area insert wait which is equivalent to 2 cycles of at access (software wait included) m37721 memory map internal sram program area external eprom area where software wait is valid specify either area as work area item processor mode f(x in ) external data bus width software wait ready program area work area condition microprocessor mode 25 mhz 16 bits inserted valid only for external eprom area external eprom internal or external sram condition microprocessor mode 20 mhz 16 bits inserted invalid external eprom internal or external sram
application 7721 group users manual 16C59 16.3 comparison of sample program execution rate figure 16.3.3 shows that there is almost no difference between conditions and about the execution time. the bus buffers become unnecessary when using the specified memory. (refer to table 16.1.6. ) considering this, the case where software wait is inserted with f(x in ) = 20 mhz (condition ) is superior in the cost performance. 1.10 1.00 0.90 0.80 0.70 0.60 0.50 0.40 0.30 0.20 0.10 0.00 work area = internal ram 1.00 1.04 1.00 1.01 1.10 1.00 0.90 0.80 0.70 0.60 0.50 0.40 0.30 0.20 0.10 0.00 sample b excution time ratio 1.00 1.05 1.00 1.03 : condition : condition work area = external ram work area = internal ram work area = external ram sample a excution time ratio fig. 16.3.3 execution time ratio
application 7721 group users manual 16C60 16.3 comparison of sample program execution rate memorandum
appendix appendix 1. memory assignment of 7721 group appendix 2. memory assignment in sfr area appendix 3. control registers appendix 4. package outline appendix 5. examples of handling unused pins appendix 6. machine instructions appendix 7. hexadecimal instruction code table appendix 8. countermeasure against noise appendix 9. 7721 group q & a appendix 10. differences between 7721 group and 7720 group appendix 11. electrical characteristics appendix 12. standard characteristics
appendix appendix 1. memory assignment of 7721 group 7721 group users manual 17C2 appendix 1. memory assignment of 7721 group microprocessor mode fig. 1 memory assignment (microprocessor mode) sfr area external area internal ram area (512 bytes) (note 2) external area (note 1) 000002 16 sfr area external area 000009 16 000000 16 000080 16 001fc0 16 00ffff 16 00047f 16 sfr area external area bank 1 16 bank ff 16 bank 0 16 010000 16 01ffff 16 ff0000 16 ffffff 16 m37721s2bfp 00007f 16 00027f 16 internal ram area (512 bytes) (512 bytes) 001fff 16 sfr area m37721s1bfp sfr area case of internal ram area select bit = ? case of internal ram area select bit = ? notes 1: interrupt vector table is assigned to addresses ffce 16 to ffff 16 . make sure to set a rom to this area. 2: for the m37721s1bfp, fix the internal ram area select bit to ?. (note 1) external area
appendix 7721 group users manual 17C3 appendix 2. memory assignment in sfr area appendix 2. memory assignment in sfr area ? 0 : 0 immediately after reset. 1 : 1 immediately after reset. ? : undefined immediately after reset. : always 0 at reading. 0 0 : always undefined at reading. : 0 immediately after reset. fix this bit to 0. 10 16 11 16 12 16 13 16 port p8 direction register 14 16 15 16 16 16 17 16 18 16 19 16 1a 16 1b 16 1c 16 1d 16 1e 16 1f 16 0 16 1 16 2 16 3 16 4 16 5 16 6 16 7 16 8 16 9 16 b 16 c 16 d 16 e 16 f 16 a 16 address port p4 register port p5 register port p4 direction register port p5 direction register port p6 register port p7 register port p6 direction register port p7 direction register port p8 register a-d control register a-d sweep pin select register register name access characteristics state immediately after reset rw rw rw rw rw rw rw rw rw rw ? 00 16 00 16 00 16 0 0 000 ? 11 b7 b0 b7 b0 : it is possible to read the bit state at reading. the written value becomes valid. : it is possible to read the bit state at reading. the written value becomes invalid. : the written value becomes valid. it is impossible to read the bit state. : nothing is assigned. it is impossible to read the bit state. the written value becomes invalid. rw ro wo rw ? ? ? ? ? ? ? ? ? ? ? ? ? 00 16 ? ? ? 0 ? ? ? ? ? ? ??? ? : always 1 at reading. 1 ? ? ? ? ? rw rw rw rw rw wo wo port p9 register port p9 direction register port p10 register port p10 direction register pulse output data register 0 pulse output data register 1 000 000 000 00 ? access characteristics state immediately after reset 00 16 00 16
appendix appendix 2. memory assignment in sfr area 7721 group users manual 17C4 0 : 0 immediately after reset. 1 : 1 immediately after reset. ? : undefined immediately after reset. : always 0 at reading. 0 0 : always undefined at reading. : 0 immediately after reset. fix this bit to 0. : it is possible to read the bit state at reading. the written value becomes valid. : it is possible to read the bit state at reading. the written value becomes invalid. : the written value becomes valid. it is impossible to read the bit state. : nothing is assigned. it is impossible to read the bit state. the written value becomes invalid. rw ro wo ? 0 : always 1 at reading. 1 access characteristics state immediately after a reset uart0 transmit/receive control register 0 uart0 transmit/receive mode register uart0 baud rate register uart0 transmit buffer register uart1 receive buffer register register name uart0 transmit/receive control register 1 uart0 receive buffer register uart1 transmit/receive mode register uart1 baud rate register uart1 transmit buffer register uart1 transmit/receive control register 0 uart1 transmit/receive control register 1 30 16 31 16 32 16 33 16 34 16 35 16 36 16 37 16 38 16 39 16 3a 16 3b 16 3c 16 3d 16 3e 16 28 16 29 16 2b 16 2c 16 2d 16 2e 16 2f 16 2a 16 20 16 21 16 22 16 23 16 24 16 25 16 26 16 27 16 3f 16 address access characteristics rw wo wo ro ro b7 b0 wo rw ro ro ro rw rw ro ro rw wo wo wo rw ro rw rw state immediately after reset 1 000 00 16 0 000 00 0 ? b7 b0 00 16 00000010 0000 0 0 0 1 000 0000 0 0 1 0 ? ? ? ? ? ? ? ? ? ? ? a-d register 5 a-d register 1 a-d register 3 a-d register 2 a-d register 4 a-d register 0 a-d register 6 a-d register 7 ro ro ro ro ro ro ro ro ro ro ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ??? ? ???
appendix 7721 group users manual 17C5 appendix 2. memory assignment in sfr area rw rw rw timer b2 register 40 16 41 16 42 16 43 16 44 16 45 16 46 16 47 16 48 16 49 16 50 16 51 16 52 16 53 16 54 16 55 16 56 16 57 16 58 16 59 16 5a 16 5b 16 5c 16 5d 16 5e 16 5f 16 4b 16 4c 16 4d 16 4e 16 4f 16 4a 16 address timer a2 register timer a3 register timer a4 register timer b0 register timer b1 register processor mode register 0 one-shot start register timer a0 register up-down register timer a1 register register name count start register timer a1 mode register timer a2 mode register timer a3 mode register timer b0 mode register timer b1 mode register timer b2 mode register access characteristics wo (note 1) (note 1) (note 1) (note 2) (note 2) (note 2) b7 b0 rw (note 2) rw rw rw rw rw rw wo state immediately after reset 00 16 00 16 00 16 ? 00 16 b7 b0 wo rw (note 1) (note 1) (note 1) rw timer a0 mode register timer a4 mode register (note 3) 0 00 0 0 0 0 0 0 0 0 0 0 00 0 00 0 0 0 0 0 0 0 0 rw rw ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? notes 1: the access characteristics at addresses 4a 16 to 4f 16 vary according to timer as operating mode. (refer to chapter 8. timer a. ) 2: the access characteristics at addresses 50 16 to 53 16 vary according to timer bs operating mode. (refer to chapter 9. timer b. ) 3: the access characteristics for bit 5 at addresses 5b 16 and 5c 16 vary according to timer bs operating mode. bit 5 at address 5d 16 is invalid. (refer to chapter 9. timer b. ) 4: bit 1 at address 5f 16 becomes 0 immediately after reset. for the m37721s1bfp, fix this bit to 0. rw (note 3) rw (note 3) 00 0 0 00 ? ? 0 0 0 00 0 ? ? ? processor mode register 1 rw rw rw rw rw rw rw 00 0 00 0 ? 0 0 00 0 00 0 0 0 1 ? (note 4) 0 : 0 immediately after reset. 1 : 1 immediately after reset. ? : undefined immediately after reset. : always 0 at reading. 0 0 : always undefined at reading. : 0 immediately after reset. fix this bit to 0. : it is possible to read the bit state at reading. the written value becomes valid. : it is possible to read the bit state at reading. the written value becomes invalid. : the written value becomes valid. it is impossible to read the bit state. : nothing is assigned. it is impossible to read the bit state. the written value becomes invalid. rw ro wo ? 0 : always 1 at reading. 1 access characteristics state immediately after reset
appendix appendix 2. memory assignment in sfr area 7721 group users manual 17C6 uart1 receive interrupt control register 60 16 61 16 62 16 63 16 64 16 65 16 66 16 67 16 68 16 69 16 70 16 71 16 72 16 73 16 74 16 75 16 76 16 77 16 78 16 79 16 7a 16 7b 16 7c 16 7d 16 7e 16 7f 16 6b 16 6c 16 6d 16 6e 16 6f 16 6a 16 address a-d conversion interrupt control register uart0 transmit interrupt control register uart1 transmit interrupt control register int 2 interrupt control register watchdog timer frequency select register register name watchdog timer register timer a0 interrupt control register timer a2 interrupt control register timer a3 interrupt control register timer a4 interrupt control register timer b1 interrupt control register timer b2 interrupt control register int 0 interrupt control register access characteristics rw b7 b0 rw state immediately after reset 0 ? (note 6) b7 b0 uart0 receive interrupt control register timer a1 interrupt control register timer b0 interrupt control register int 1 interrupt control register 0 0 00 0 by writing dummy data to address 60 16 , the value fff 16 is set to the watchdog timer. the dummy data is not retained anywhere. the value fff 16 is set to the watchdog timer. (refer to chapter 15. watchdog timer .) it is possible to read the bit state at reading. when writing 0 to this bit, this bit becomes 0. but when writing 1 to this bit, this bit does not change. rw notes 5: 6: 7: (note 5) ? ? ? rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 0 00 0 ? 0 00 0 ? 0 00 0 ? 0 00 0 ? 0 00 0 ? 0 00 0 ? 0 00 0 ? 0 00 0 ? 0 00 0 ? 0 00 0 ? 0 00 0 ? 0 00 0 0 00 0 0 00 0 0 0 0 0 0 0 ? ? ? ? ? ? ? ? ? 0 00 real-time output control register refresh timer dm ac control register l dm ac control register h dma0 interrupt control register dma1 interrupt control register dma2 interrupt control register dma3 interrupt control register rw 0 0 0 0 0 0 0 0 rw rw dram control register wo rw (note 7) rw wo rw rw rw rw 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ?? 0 0 00 0 ? ? 0 00 0 ? 0 00 0 ? 0 00 0 : 0 immediately after reset. 1 : 1 immediately after reset. ? : undefined immediately after reset. : always 0 at reading. 0 0 : always undefined at reading. : 0 immediately after reset. fix this bit to 0. : it is possible to read the bit state at reading. the written value becomes valid. : it is possible to read the bit state at reading. the written value becomes invalid. : the written value becomes valid. it is impossible to read the bit state. : nothing is assigned. it is impossible to read the bit state. the written value becomes invalid. rw ro wo ? 0 : always 1 at reading. 1 access characteristics state immediately after reset
appendix 7721 group users manual 17C7 appendix 2. memory assignment in sfr area 1fc0 16 1fc1 16 1fc2 16 1fc3 16 1fc4 16 1fc5 16 1fc6 16 1fc7 16 1fc8 16 1fc9 16 1fd0 16 1fd1 16 1fd2 16 1fd3 16 1fd4 16 1fd5 16 1fd6 16 1fd7 16 1fd8 16 1fd9 16 1fda 16 1fdb 16 1fdc 16 1fdd 16 1fde 16 1fdf 16 1fcb 16 1fcc 16 1fcd 16 1fce 16 1fcf 16 1fca 16 address register name source address register 0 access characteristics b7 b0 state immediately after reset b7 b0 rw 0 00 0 0 00 0 0 00 0 ? ? rw rw 0 0 00 0 0 00 0 ? 0 00 destination address register 0 transfer counter register 0 dma0 mode register l dma0 mode register h dma0 control register source address register 1 destination address register 1 transfer counter register 1 dma1 mode register l dma1 mode register h dma1 control register rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw ? ? ? ? ? ? ? ? ? ? 0 0 00 0 0 0 0 00 ?? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 00 0 0 00 0 0 0 ?? 0 : 0 immediately after reset. 1 : 1 immediately after reset. ? : undefined immediately after reset. : always 0 at reading. 0 0 : always undefined at reading. : 0 immediately after reset. fix this bit to 0. : it is possible to read the bit state at reading. the written value becomes valid. : it is possible to read the bit state at reading. the written value becomes invalid. : the written value becomes valid. it is impossible to read the bit state. : nothing is assigned. it is impossible to read the bit state. the written value becomes invalid. rw ro wo ? 0 : always 1 at reading. 1 access characteristics state immediately after reset
appendix appendix 2. memory assignment in sfr area 7721 group users manual 17C8 1fe0 16 1fe1 16 1fe2 16 1fe3 16 1fe4 16 1fe5 16 1fe6 16 1fe7 16 1fe8 16 1fe9 16 1ff0 16 1ff1 16 1ff2 16 1ff3 16 1ff4 16 1ff5 16 1ff6 16 1ff7 16 1ff8 16 1ff9 16 1ffa 16 1ffb 16 1ffc 16 1ffd 16 1ffe 16 1fff 16 1feb 16 1fec 16 1fed 16 1fee 16 1fef 16 1fea 16 address register name source address register 2 access characteristics b7 b0 state immediately after reset b7 b0 rw 0 00 0 0 00 0 0 00 0 ? ? rw rw 0 0 00 0 0 00 0 ? 0 00 destination address register 2 transfer counter register 2 dma2 mode register l dma2 mode register h dma2 control register source address register 3 destination address register 3 transfer counter register 3 dma3 mode register l dma3 mode register h dma3 control register rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw ? ? ? ? ? ? ? ? ? ? 0 0 00 0 0 0 0 00 ?? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 00 0 0 00 0 0 0 ?? 0 : 0 immediately after reset. 1 : 1 immediately after reset. ? : undefined immediately after reset. : always 0 at reading. 0 0 : always undefined at reading. : 0 immediately after reset. fix this bit to 0. : it is possible to read the bit state at reading. the written value becomes valid. : it is possible to read the bit state at reading. the written value becomes invalid. : the written value becomes valid. it is impossible to read the bit state. : nothing is assigned. it is impossible to read the bit state. the written value becomes invalid. rw ro wo ? 0 : always 1 at reading. 1 access characteristics state immediately after reset
appendix appendix 3. control registers 7721 group users manual 17C9 appendix 3. control registers the control registers allocated in the sfr area are shown on the following pages. below is the structure diagram for all registers. 0 1 0 xxx register (address xx 16 ) b1 b0 b2 b3 b4 b5 b6 b7 0 ] 1 ] 2 ] 3 2 3 ... select bit 0 : ... 1 : ... ... select bit 0 : ... 1 : ... the value is 0 at reading. 0 : ... 1 : ... fix this bit to 0. 4 7 to 5 nothing is assigned. 5 rw wo ro rw rw C 0 0 0 bit bit name this bit is invalid in ... mode. functions at reset rw ... flag undefined undefined ] 1 blank : set to 0 or 1 according to the usage. 0 : set to 0 at writing. 1 : set to 1 at writing. 5 : invalid depending on the mode or state. it may be 0 or 1. : nothing is assigned. ] 2 0 : 0 immediately after reset. 1 : 1 immediately after reset. undefined : undefined immediately after reset. ] 3 rw : it is possible to read the bit state at reading. the written value becomes valid. ro accordingly, the written value may be 0 or 1. wo : the written value becomes valid. it is impossible to read the bit state. the value is undefined at reading. however, when [0 is at reading] is indicated in the function or note column, the bit is always 0 at reading. (see ] 4 above.) : it is impossible to read the bit state. the value is undefined at reading. however, when [0 is at reading] is indicated in the function or note column, the bit is always 0 at reading. (see ] 4 above.) the written value becomes invalid. accordingly, the written value may be 0 or 1. ] 4 : it is possible to read the bit state at reading. the written value becomes invalid.
appendix appendix 3. control registers 7721 group users manual 17C10 port pi register bit bit name functions 0 1 2 3 4 5 6 7 port pi 0 ? pin port pi 2 ? pin port pi 3 ? pin port pi 4 ? pin port pi 6 ? pin data is input from or output to a pin by reading from or writing to the corresponding bit. port pi 5 ? pin port pi register (i = 4 to 10) (addresses a 16 , b 16 , e 16 , f 16 , 12 16 , 13 16 , 16 16 ) b1 b0 b2 b3 b4 b5 b6 b7 port pi 1 ? pin port pi 7 ? pin at reset rw undefined undefined undefined undefined undefined undefined undefined undefined 0 : ??level 1 : ??level rw rw rw rw rw rw rw rw note: for bits 0 to 2 of the port p4 register, nothing is assigned and these bits are fixed to ??at reading. port pi direction register bit bit name functions 0 1 2 3 4 5 6 7 port pi 0 direction bit port pi 2 direction bit port pi 3 direction bit port pi 4 direction bit port pi 6 direction bit 0 : input mode (the port functions as an input port) 1 : output mode (the port functions as an output port) port pi 5 direction bit port pi direction register (i = 4 to 10) (addresses c 16 , d 16 , 10 16 , 11 16 , 14 16 , 15 16 , 18 16 ) b1 b0 b2 b3 b4 b5 b6 b7 port pi 1 direction bit port pi 7 direction bit at reset rw 0 0 0 0 0 0 0 0 rw rw rw rw rw rw rw rw note: for bits 0 to 2 of the port p4 direction register, nothing is assigned and these bits are fixed to ??at reading.
appendix appendix 3. control registers 7721 group users manual 17C11 pulse output data register 0 bit bit name functions 0 1 2 3 7 to 4 rtp0 0 pulse output data bit pulse output data register 0 (address 1a 16 ) b1 b0 b2 b3 b4 b5 b6 b7 at reset rw undefined undefined undefined undefined undefined 0 : ??level output 1 : ??level output wo note: use the ldm or sta instruction for writing to this register rtp0 1 pulse output data bit wo wo wo rtp0 2 pulse output data bit (valid in pulse mode 0) rtp0 3 pulse output data bit (valid in pulse mode 0) nothing is assigned. pulse output data register 1 bit bit name functions 0, 1 2 3 nothing is assigned. pulse output data register 1 (address 1c 16 ) b1 b0 b2 b3 b4 b5 b6 b7 at reset rw undefined undefined undefined undefined undefined 0 : ??level output 1 : ??level output wo note: use the ldm or sta instruction for writing to this register. wo wo wo rtp0 3 pulse output data bit (valid in pulse mode 1) 4 rtp0 2 pulse output data bit (valid in pulse mode 1) rtp1 0 pulse output data bit 5 6 7 rtp1 1 pulse output data bit rtp1 2 pulse output data bit rtp1 3 pulse output data bit undefined undefined wo wo
appendix appendix 3. control registers 7721 group users manual 17C12 a-d control register b7 b6 b5 b4 b3 b2 b1 b0 a-d control register (address 1e 16 ) bit a-d conversion frequency ( ad ) select bit a-d conversion start bit trigger select bit 4 a-d operation mode select bit 2 1 0 bit name at reset 0 undefined rw functions 0 0 0 : an 0 selected 0 0 1 : an 1 selected 0 1 0 : an 2 selected 0 1 1 : an 3 selected 1 0 0 : an 4 selected 1 0 1 : an 5 selected 1 1 0 : an 6 selected 1 1 1 : an 7 selected (note 2) b2 b1 b0 0 : internal trigger 1 : external trigger 0 0 : one-shot mode 0 1 : repeat mode 1 0 : single sweep mode 1 1 : repeat sweep mode 0 : stop a-d conversion 1 : start a-d conversion b4 b3 notes 1: these bits are invalid in the single sweep and repeat sweep mode. (they may be either 0 or 1.) 2: when selecting an external trigger, the an 7 pin cannot be used as an analog input pin. 3: writing to each bit (except bit 6) of the a-d control register must be performed while the a-d converter halts. analog input select bits (valid in one-shot and repeat modes) (note 1) 3 7 6 5 undefined undefined rw rw rw rw rw rw rw rw 0 0 0 0 0 : f 2 divided by 4 1 : f 2 divided by 2 a-d sweep pin select register b7 b6 b5 b4 b3 b2 b1 b0 a-d sweep pin select register (address 1f 16 ) bit 1 0 bit name at reset 1 undefined rw functions notes 1: these bits are invalid in the one-shot and repeat modes. (they may be either 0 or 1.) 2: when selecting an external trigger, the an 7 pin cannot be used as an analog input pin. 3: writing to each bit of the a-d sweep pin select register must be performed while the a-d converter halts. 7 to 2 rw rw 0 0 : an 0 , an 1 (2 pins) 0 1 : an 0 to an 3 (4 pins) 1 0 : an 0 to an 5 (6 pins) 1 1 : an 0 to an 7 (8 pins) (note 2) a-d sweep pin select bits (valid in single sweep and repeat sweep modes) (note 1) b1 b0 nothing is assigned. C 1 a-d register i b7 b0 a-d register i (i = 0 to 7) (addresses 20 16 , 22 16 , 24 16 , 26 16 , 28 16 , 2a 16 , 2c 16 , 2e 16 ) bit 7 to 0 at reset undefined rw functions ro reads an a-d conversion result.
appendix appendix 3. control registers 7721 group users manual 17C13 uarti transmit/receive mode register uarti baud rate register b7 b6 b5 b4 b3 b2 b1 b0 bit 4 2 1 0 bit name at reset 0 rw functions b2 b1 b0 3 7 6 5 rw rw rw rw rw rw rw rw 0 0 0 0 serial i/o mode select bits 0 0 0 : serial i/o disabled (p8 functions as a programmable i/o port.) 0 0 1 : clock synchronous serial i/o mode 0 1 0 : do not select. 0 1 1 : do not select. 1 0 0 : uart mode (transfer data length = 7 bits) 1 0 1 : uart mode (transfer data length = 8 bits) 1 1 0 : uart mode (transfer data length = 9 bits) 1 1 1 : do not select. sleep select bit (valid in uart mode) ( note ) parity enable bit (valid in uart mode) ( note ) odd/even parity select bit (valid in uart mode when parity enable bit is 1) ( note ) stop bit length select bit (valid in uart mode) ( note ) internal/external clock select bit uart0 transmit/receive mode register (address 30 16 ) uart1 transmit/receive mode register (address 38 16 ) note: bits 4 to 6 are invalid in the clock synchronous serial i/o mode. (they may be either 0 or 1.) additionally, fix bit 7 to 0. 0 : odd parity 1 : even parity 0 : parity disabled 1 : parity enabled 0 : sleep mode terminated (invalid) 1 : sleep mode selected 0 : internal clock 1 : external clock 0 : one stop bit 1 : two stop bits 0 0 0 b7 b0 uart0 baud rate register (address 31 16 ) uart1 baud rate register (address 39 16 ) functions bit at reset rw 7 to 0 can be set to 00 16 to ff 16 . assuming that the set value = n, brgi divides the count source frequency by (n + 1). undefined wo note: writing to this register must be performed while the transmission/reception halts. use the ldm or sta instruction for writing to this register.
appendix appendix 3. control registers 7721 group users manual 17C14 uarti transmit buffer register uarti transmit/receive control register 0 b7 b0 bit 8 to 0 at reset undefined rw functions wo b7 b0 (b15) (b8) 15 to 9 C undefined uart0 transmit buffer register (addresses 33 16 , 32 16 ) uart1 transmit buffer register (addresses 3b 16 , 3a 16 ) nothing is assigned. transmit data is set. note: use the ldm or sta instruction for writing to this register. cts/rts select bit bit 1 brg count source select bits bit name at reset rw functions b7 b6 b5 b4 b3 b2 b1 b0 0 0 : f 2 0 1 : f 16 1 0 : f 64 1 1 : f 512 uart0 transmit/receive control register 0 (address 34 16 ) uart1 transmit/receive control register 0 (address 3c 16 ) b1 b0 0 : cts function selected 1 : rts function selected transmit register empty flag 0 : data present in transmit register (during transmission) 1 : no data present in transmit register (transmission completed) 1 0 0 0 0 2 rw rw ro 3 rw 7 to 4 nothing is assigned. undefined C
appendix appendix 3. control registers 7721 group users manual 17C15 uarti transmit/receive control register 1 bit bit name at reset 5 framing error flag (valid in uart mode) 0 0 : no framing error 1 : framing error detected rw functions b7 b6 b5 b4 b3 b2 b1 b0 uart0 transmit/receive control register 1 (address 35 16 ) uart1 transmit/receive control register 1 (address 3d 16 ) notes 1: bit 4 is cleared to 0 when the receive enable bit is cleared to 0 or when the serial i/o mode select bits (bits 2 to 0 at addresses 30 16 , 38 16 ) are cleared to 000 2 . bits 5 and 6 are cleared to 0 when one of the following is performed: ?clearing the receive enable bit to 0 ?reading the low-order byte of the uarti receive buffer register (addresses 36 16 , 3e 16 ) out ?clearing the serial i/o mode select bits (bits 2 to 0 at addresses 30 16 , 38 16 ) to 000 2 bit 7 is cleared to 0 when all of bits 4 to 6 become 0. 2: bits 5 to 7 are invalid in the clock synchronous serial i/o mode. 0 transmit enable bit 0 0 : transmission disabled 1 : transmission enabled 1 transmit buffer empty flag 1 0 : data present in transmit buffer register 1 : no data present in transmit buffer register 2 receive enable bit 0 0 : reception disabled 1 : reception enabled 3 receive complete flag 0 0 : no data present in receive buffer register 1 : data present in receive buffer register 4 overrun error flag 0 0 : no overrun error 1 : overrun error detected 6 parity error flag (valid in uart mode) 0 0 : no parity error 1 : parity error detected 7 error sum flag (valid in uart mode) 0 0 : no error 1 : error detected (notes 1, 2) (notes 1, 2) (notes 1, 2) (note 1) rw ro rw ro ro ro ro ro uarti receive buffer register b7 b0 bit 8 to 0 at reset undefined rw functions ro b7 b0 (b15) (b8) 15 to 9 C uart0 receive buffer register (addresses 37 16 , 36 16 ) uart1 receive buffer register (addresses 3f 16 , 3e 16 ) nothing is assigned. the value is 0 at reading. receive data is read out from here. 0
appendix appendix 3. control registers 7721 group users manual 17C16 count start register bit timer b2 count start bit timer b1 count start bit timer b0 count start bit timer a4 count start bit timer a3 count start bit timer a2 count start bit timer a1 count start bit timer a0 count start bit bit name at reset 0 0 0 0 0 0 0 0 rw functions b7 b6 b5 b4 b3 b2 b1 b0 count start register (address 40 16 ) 0 : stop counting 1 : start counting rw rw rw rw rw rw rw rw 0 1 2 3 4 5 6 7 one-shot start register bit 7 to 5 nothing is assigned. timer a4 one-shot start bit timer a3 one-shot start bit timer a2 one-shot start bit bit name at reset 0 0 undefined 0 0 0 rw functions b7 b6 b5 b4 b3 b2 b1 b0 one-shot start register (address 42 16 ) 1 : start outputting one-shot pulse (valid when internal trigger is selected.) the value is 0 at reading. 0 1 2 3 4 wo wo wo wo wo C 00 fix these bits to 0. the value is 0 at reading.
appendix appendix 3. control registers 7721 group users manual 17C17 up-down register bit bit name at reset 0 0 0 0 0 rw functions b7 b6 b5 b4 b3 b2 b1 b0 up-down register (address 44 16 ) 0 0 0 timer a4 up-down bit timer a3 up-down bit timer a2 up-down bit fix these bits to ?. timer a2 two-phase pulse signal processing select bit (note) timer a3 two-phase pulse signal processing select bit (note) timer a4 two-phase pulse signal processing select bit (note) 0 : countdown 1 : countup this function is valid when the contents of the up-down register is selected as the up- down switching factor. 0 : two-phase pulse signal processing function disabled 1 : two-phase pulse signal processing function enabled when not using the two-phase pulse signal processing function, set the bit to ?. the value is ??at reading. note: use the ldm or sta instruction for writing to bits 5 to 7. 0 1 2 3 4 5 6 7 rw rw rw rw rw wo wo wo 00
appendix appendix 3. control registers 7721 group users manual 17C18 timer ai register b7 b0 b7 b0 (b15) (b8) timer a0 register (addresses 47 16 , 46 16 ) timer a1 register (addresses 49 16 , 48 16 ) timer a2 register (addresses 4b 16 , 4a 16 ) timer a3 register (addresses 4d 16 , 4c 16 ) timer a4 register (addresses 4f 16 , 4e 16 ) functions bit at reset rw 15 to 0 these bits have different functions according to the operating mode. undefined rw (note 1) notes 1: the access characteristics for the timer a2 register, timer a3 register, and timer a4 register differ according to timer a? operating mode. 2: read from or write to this register in a unit of 16 bits. timer ai mode register bit 7 5 4 3 1 bit name at reset 0 0 0 0 0 0 0 0 rw functions b7 b6 b5 b4 b3 b2 b1 b0 timer ai mode register (i = 0 to 4) (addresses 56 16 to 5a 16 ) 0 0 : timer mode 0 1 : event counter mode 1 0 : one-shot pulse mode 1 1 : pulse width modulation (pwm) mode b1 b0 these bits have different functions according to the operating mode. operating mode select bits 6 2 0 rw rw rw rw rw rw rw rw
appendix appendix 3. control registers 7721 group users manual 17C19 timer mode b7 b0 b7 b0 (b15) (b8) timer a0 register (addresses 47 16 , 46 16 ) timer a1 register (addresses 49 16 , 48 16 ) timer a2 register (addresses 4b 16 , 4a 16 ) timer a3 register (addresses 4d 16 , 4c 16 ) timer a4 register (addresses 4f 16 , 4e 16 ) functions bit at reset rw 15 to 0 these bits can be set to 0000 16 to ffff 16 . assuming that the set value = n, the counter divides the count source frequency by (n + 1). when reading, the register indicates the counter value. undefined rw gate function select bits pulse output function select bit 1 operating mode select bits bit name functions b7 b6 b5 b4 b3 b2 b1 b0 timer aj mode register (j = 2 to 4) (addresses 58 16 to 5a 16 ) 0 0 : timer mode 0 : no pulse output (taj out pin functions as a programmable i/o port.) 1 : pulse output (taj out pin functions as a pulse output pin.) 0 0 : f 2 0 1 : f 16 1 0 : f 64 1 1 : f 512 b7 b6 count source select bits b1 b0 b4 b3 0 0 0 0 : no gate function 0 1 : (taj in pin functions as a prog- rammable i/o port.) 1 0 : counter counts only while taj in pins input signal is at l level. 1 1 : counter counts only while taj in pins input signal is at h level. bit 4 at reset rw 0 2 0 rw 0 rw 0 rw 3 0 rw 0 rw 5 0 rw 6 7 0 rw 0 rw 0 fix this bit to 0 in timer mode. bit 5 4 3 1 bit name at reset 0 0 0 0 0 0 rw functions b7 b6 b5 b4 b3 b2 b1 b0 timer a0 mode register (address 56 16 ) timer a1 mode register (address 57 16 ) fix these bits to 0. 2 0 rw rw rw rw rw rw note: read from or write to this register in a unit of 16 bits. 000000 0 0 : f 2 0 1 : f 16 1 0 : f 64 1 1 : f 512 b7 b6 count source select bits 6 7 0 rw 0 rw
appendix appendix 3. control registers 7721 group users manual 17C20 event counter mode b7 b6 b5 b4 b3 b2 b1 b0 001 bit up-down switching factor select bit count polarity select bit bit name these bits are invalid in event counter mode. fix this bit to ??in event counter mode. 7 functions 0 : counts at falling edge of external signal 1 : counts at rising edge of external signal 0 : contents of up-down register 1 : input signal to taj out pin at reset 0 0 0 0 0 rw pulse output function select bit operating mode select bits 1 0 : no pulse output (taj out pin functions as a programmable i/o port.) 1 : pulse output (taj out pin functions as a pulse output pin.) 0 1 : event counter mode b1 b0 0 0 0 55 0 2 rw rw 3 4 5 6 rw rw rw rw rw rw timer aj mode register (j = 2 to 4) (addresses 58 16 to 5a 16 ) b7 b0 b7 b0 (b15) (b8) timer a2 register (addresses 4b 16 , 4a 16 ) timer a3 register (addresses 4d 16 , 4c 16 ) timer a4 register (addresses 4f 16 , 4e 16 ) rw 15 to 0 bit functions at reset rw these bits can be set to ?000 16 ?to ?fff 16 . assuming that the set value = n, the counter divides the count source frequency by (n + 1) during countdown, or by (ffff 16 ?n + 1) during countup. when reading, the register indicates the counter value. undefined note: read from or write to this register in a unit of 16 bits.
appendix appendix 3. control registers 7721 group users manual 17C21 one-shot pulse mode b7 b0 b7 b0 (b15) (b8) timer a2 register (addresses 4b 16 , 4a 16 ) timer a3 register (addresses 4d 16 , 4c 16 ) timer a4 register (addresses 4f 16 , 4e 16 ) rw 15 to 0 these bits can be set to 0001 16 to ffff 16 . assuming that the set value = n, the h level width of the one-shot pulse output from the taj out pin is expressed as follows : undefined f i : frequency of count source (f 2 , f 16 , f 64 , or f 512 ) wo trigger select bits fix this bit to 1 in one-shot pulse mode. 1 bit name functions b7 b6 b5 b4 b3 b2 b1 b0 timer aj mode register (j = 2 to 4) (addresses 58 16 to 5a 16 ) 1 0 : one-shot pulse mode 7 0 0 : f 2 0 1 : f 16 1 0 : f 64 1 1 : f 512 b7 b6 count source select bits b1 b0 b4 b3 fix this bit to 0 in one-shot pulse mode. 10 1 0 0 : writing 1 to one-shot start register 0 1 : (taj in pin functions as a prog- rammable i/o port.) 1 0 : falling edge of taj in pins input signal 1 1 : rising edge of taj in pins input signal bit at reset 0 0 0 0 0 0 0 0 rw 0 4 0 2 3 5 6 rw rw rw rw rw rw rw rw operating mode select bits n f i . note: use the ldm or sta instruction for writing to this register. read from or write to this register in a unit of 16 bits. bit functions at reset
appendix appendix 3. control registers 7721 group users manual 17C22 pulse width modulation (pwm) mode b7 b0 b7 b0 timer a2 register (addresses 4b 16 , 4a 16 ) timer a3 register (addresses 4d 16 , 4c 16 ) timer a4 register (addresses 4f 16 , 4e 16 ) functions bit at reset rw 15 to 0 these bits can be set to 0000 16 to fffe 16 . assuming that the set value = n, the h level width of the pwm pulse output from the taj out pin is expressed as follows: (pwm pulse period = ) undefined (b15) (b8) wo n f i f i : frequency of count source (f 2 , f 16 , f 64 , or f 512 ) (b15) b7 b0 b7 b0 (b8) timer a2 register (addresses 4b 16 , 4a 16 ) timer a3 register (addresses 4d 16 , 4c 16 ) timer a4 register (addresses 4f 16 , 4e 16 ) functions bit at reset rw 7 to 0 15 to 8 undefined undefined these bits can be set to 00 16 to ff 16 . assuming that the set value = m, pwm pulses period output from the taj out pin is expressed as follows: (m + 1)(2 8 C 1) f i wo these bits can be set to 00 16 to fe 16 . assuming that the set value = n, the h level width of the pwm pulse output from the taj out pin is expressed as follows: n(m + 1) f i wo f i : frequency of count source (f 2 , f 16 , f 64 , or f 512 ) b7 b6 b5 b4 b3 b2 b1 b0 timer aj mode register (j = 2 to 4) (addresses 58 16 to 5a 16 ) 7 0 0 : f 2 0 1 : f 16 1 0 : f 64 1 1 : f 512 b7 b6 count source select bits 11 1 at reset 0 rw trigger select bits fix this bit to 1 in pwm mode. 1 operating mode select bits functions 1 1 : pwm mode b1 b0 b4 b3 16/8-bit pwm mode select bit 0 0 : writing 1 to count start register 0 1 : (taj in pin functions as a pro- grammable i/o port.) 1 0 : falling edge of taj in pins input signal 1 1 : rising edge of taj in pins input signal 0 : 16-bit pulse width modulator 1 : 8-bit pulse width modulator 4 0 2 3 5 6 0 0 0 0 0 0 0 rw rw rw rw rw rw rw rw note: use the ldm or sta instruction for writing to this register. read from or write to this register in a unit of 16 bits. note: use the ldm or sta instruction for writing to this register. read from or write to this register in a unit of 16 bits. n 16 C 1 f i bit bit name
appendix appendix 3. control registers 7721 group users manual 17C23 timer bi register b7 b0 b7 b0 (b15) (b8) timer b0 register (addresses 51 16 , 50 16 ) timer b1 register (addresses 53 16 , 52 16 ) timer b2 register (addresses 55 16 , 54 16 ) functions bit at reset rw 15 to 0 these bits have different functions according to the operating mode. undefined rw (note 1) notes 1: the access characteristics for the timer b0 register and timer b1 register differ according to timer bs operating mode. 2: read from or write to this register in a unit of 16 bits. timer bi mode register nothing is assigned. these bits have different functions according to the operating mode. 1 operating mode select bits bit name functions b7 b6 b5 b4 b3 b2 b1 b0 timer bi mode register (i = 0 to 2) (addresses 5b 16 to 5d 16 ) 0 0 : timer mode 0 1 : event counter mode 1 0 : pulse period/pulse width measurement mode 1 1 : do not select. b1 b0 bit 5 at reset rw 0 2 0 rw rw rw 6 7 note: bit 5 is invalid in the timer and event counter modes; its value is undefined at reading. 3 0 0 rw 0 C undefined 4 ro (note) undefined rw 0 rw 0 these bits have different functions according to the operating mode.
appendix appendix 3. control registers 7721 group users manual 17C24 timer mode b7 b6 b5 b4 b3 b2 b1 b0 00 bit this bit is invalid in timer mode; its value is undefined at reading. nothing is assigned. bit name count source select bits functions at reset rw these bits are invalid in timer mode. operating mode select bits 1 0 0 : timer mode b1 b0 0 5 5 0 2 rw rw 3 rw rw timer bi mode register (i = 0 to 2) (addresses 5b 16 to 5d 16 ) 5 0 0 0 undefined 4 undefined 5 6 7 0 0 : f 2 0 1 : f 16 1 0 : f 64 1 1 : f 512 b7 b6 rw 0 rw 0 b7 b0 b7 b0 (b15) (b8) timer b0 register (addresses 51 16 , 50 16 ) timer b1 register (addresses 53 16 , 52 16 ) timer b2 register (addresses 55 16 , 54 16 ) rw 15 to 0 bit functions at reset these bits can be set to ?000 16 ?to ?fff 16 . assuming that the set value = n, the counter divides the count source frequency by (n + 1). when reading, the register indicates the counter value. undefined rw ro note: read from or write to this register in a unit of 16 bits.
appendix appendix 3. control registers 7721 group users manual 17C25 event counter mode b7 b0 b7 b0 (b15) (b8) timer b0 register (addresses 51 16 , 50 16 ) timer b1 register (addresses 53 16 , 52 16 ) rw 15 to 0 bit functions at reset rw these bits can be set to ?000 16 ?to ?fff 16 . assuming that the set value = n, the counter divides the count source frequency by (n + 1). when reading, the register indicates the counter value. undefined note: read from or write to this register in a unit of 16 bits. 0 0 : count at falling edge of external signal 0 1 : count at rising edge of external signal 1 0 : counts at both falling and rising edges of external signal 1 1 : do not select. b7 b6 b5 b4 b3 b2 b1 b0 01 bit count polarity select bits bit name these bits are invalid in event counter mode. this bit is invalid in event counter mode; its value is undefined at reading. 7 functions at reset 0 0 0 rw operating mode select bits 1 0 1 : event counter mode b1 b0 0 0 0 55 0 2 rw rw 3 4 5 6 rw rw rw rw timer bj mode register (j = 0, 1) (addresses 5b 16 , 5c 16 ) b3 b2 nothing is assigned. 5 undefined undefined ro
appendix appendix 3. control registers 7721 group users manual 17C26 pulse period/pulse width measurement mode measurement mode select bits 1 operating mode select bits bit name functions b7 b6 b5 b4 b3 b2 b1 b0 timer bj mode register (j = 0, 1) (addresses 5b 16 , 5c 16 ) 1 0 : pulse period/pulse width measurement mode 7 0 0 : f 2 0 1 : f 16 1 0 : f 64 1 1 : f 512 b7 b6 count source select bits b1 b0 b3 b2 nothing is assigned. 0 1 0 0 : pulse period measurement (interval between falling edges of measurement pulse) 0 1 : pulse period measurement (interval between rising edges of measurement pulse) 1 0 : pulse width measurement (interval from a falling edge to a rising edge, and from a rising edge to a falling edge of measurement pulse) 1 1 : do not select. bit at reset undefined 0 rw 4 0 2 3 6 rw rw rw rw C rw rw b7 b0 b7 b0 (b15) (b8) timer b0 register (addresses 51 16 , 50 16 ) timer b1 register (addresses 53 16 , 52 16 ) rw 15 to 0 the measurement result of pulse period or pulse width is read out. undefined ro 5 0 0 0 timer bj overflow flag (note) 0 : no overflow 1 : overflowed undefined ro 0 0 note: the timer bj overflow flag is cleared to 0 at the next count timing of the count source when a value is written to the timer bj mode register with the count start bit = 1. note: read from this register in a unit of 16 bits. functions bit at reset
appendix appendix 3. control registers 7721 group users manual 17C27 processor mode register 0 bit bit name functions at reset rw 0 1 3 4 5 6 7 fix this bit to 0. software reset bit interrupt priority detection time select bits stack bank select bit 0 0 0 the microcomputer is reset by writing 1 to this bit. the value is 0 at reading. 0 0 : 7 cycles of 0 1 : 4 cycles of 1 0 : 2 cycles of 1 1 : do not select. 0 : bank 0 16 1 : bank ff 16 0 1 b5 b4 processor mode register 0 (address 5e 16 ) b1 b0 b2 b3 b4 b5 b6 b7 0 rw C wo 0 rw 0 rw fix this bit to 0. rw rw 0 nothing is assigned. the value is 1 at reading. 2 0 wait bit rw 0 : software wait is inserted when accessing external area. 1 : no software wait is inserted when accessing external area. processor mode register 1 b7 b6 b5 b4 b3 b2 b1 b0 processor mode register 1 (address 5f 16 ) bit 7 to 2 1 0 bit name at reset rw functions notes 1: for the m37721s1bfp, fix bit 1 to 0. 2: for the m37721s2bfp, set bit 1 before setting the stack pointer. nothing is assigned. C undefined internal ram area select bit (notes 1, 2) 0 : 512 bytes (addresses 80 16 to 27f 16 ) 1 : 1024 bytes (addresses 80 16 to 47f 16 ) nothing is assigned. rw 0 C undefined
appendix appendix 3. control registers 7721 group users manual 17C28 watchdog timer register b7 b0 watchdog timer register (address 60 16 ) bit initializes watchdog timer. when dummy data is written to this register, watchdog timer? value is initialized to ?ff 16 .?(dummy data: 00 16 to ff 16 ) at reset undefined rw functions 7 to 0 watchdog timer frequency select register 0 : f 512 1 : f 32 at reset undefined 0 rw functions b7 b6 b5 b4 b3 b2 b1 b0 watchdog timer frequency select register (address 61 16 ) bit nothing is assigned. watchdog timer frequency select bit bit name 0 7 to 1 rw
appendix appendix 3. control registers 7721 group users manual 17C29 real-time output control register b7 b6 b5 b4 b3 b2 b1 b0 bit nothing is assigned. the value is ??at reading. bit name functions at reset rw pulse output mode select bit waveform output select bits 1 see the following table. 0 0 2 rw rw 7 to 3 rw real-time output control register (address 62 16 ) 0 0 undefined 0 : pulse mode 0 1 : pulse mode 1 note: when using the p6 0 ?6 7 pins as the pulse output pins for real-time output, set the corresponding bits of the port p6 direction register (address 10 16 ) to ?. b1 b0 when pulse mode 0 is selected 00 p6 7 /rtp1 3 p6 6 /rtp1 2 p6 5 /rtp1 1 p6 4 /rtp1 0 p6 3 /rtp0 3 p6 2 /rtp0 2 p6 1 /rtp0 1 p6 0 /rtp0 0 port 01 p6 7 /rtp1 3 p6 6 /rtp1 2 p6 5 /rtp1 1 p6 4 /rtp1 0 p6 3 /rtp0 3 p6 2 /rtp0 2 p6 1 /rtp0 1 p6 0 /rtp0 0 port port rtp 10 p6 7 /rtp1 3 p6 6 /rtp1 2 p6 5 /rtp1 1 p6 4 /rtp1 0 p6 3 /rtp0 3 p6 2 /rtp0 2 p6 1 /rtp0 1 p6 0 /rtp0 0 rtp 11 p6 7 /rtp1 3 p6 6 /rtp1 2 p6 5 /rtp1 1 p6 4 /rtp1 0 p6 3 /rtp0 3 p6 2 /rtp0 2 p6 1 /rtp0 1 p6 0 /rtp0 0 port rtp rtp p6 7 /rtp1 3 p6 6 /rtp1 2 p6 5 /rtp1 1 p6 4 /rtp1 0 p6 3 /rtp0 3 p6 2 /rtp0 2 p6 1 /rtp0 1 p6 0 /rtp0 0 port port when pulse mode 1 is selected p6 7 /rtp1 3 p6 6 /rtp1 2 p6 5 /rtp1 1 p6 4 /rtp1 0 p6 3 /rtp0 3 p6 2 /rtp0 2 p6 1 /rtp0 1 p6 0 /rtp0 0 port rtp p6 7 /rtp1 3 p6 6 /rtp1 2 p6 5 /rtp1 1 p6 4 /rtp1 0 p6 3 /rtp0 3 p6 2 /rtp0 2 p6 1 /rtp0 1 p6 0 /rtp0 0 port rtp p6 7 /rtp1 3 p6 6 /rtp1 2 p6 5 /rtp1 1 p6 4 /rtp1 0 p6 3 /rtp0 3 p6 2 /rtp0 2 p6 1 /rtp0 1 p6 0 /rtp0 0 rtp rtp port : this functions as a programmable i/o port. rtp : this functions as a pulse output pin.
appendix appendix 3. control registers 7721 group users manual 17C30 dram control register 0 0 0 0 : no dram area 0 0 0 1 : f00000 16 ?fffff 16 (1 mbyte) 0 0 1 0 : e00000 16 ?fffff 16 (2 mbytes) 0 0 1 1 : d00000 16 ?fffff 16 (3 mbytes) 0 1 0 0 : c00000 16 ?fffff 16 (4 mbytes) 0 1 0 1 : b00000 16 ?fffff 16 (5 mbytes) 0 1 1 0 : a00000 16 ?fffff 16 (6 mbytes) 0 1 1 1 : 900000 16 ?fffff 16 (7 mbytes) 1 0 0 0 : 800000 16 ?fffff 16 (8 mbytes) 1 0 0 1 : 700000 16 ?fffff 16 (9 mbytes) 1 0 1 0 : 600000 16 ?fffff 16 (10 mbytes) 1 0 1 1 : 500000 16 ?fffff 16 (11 mbytes) 1 1 0 0 : 400000 16 ?fffff 16 (12 mbytes) 1 1 0 1 : 300000 16 ?fffff 16 (13 mbytes) 1 1 1 0 : 200000 16 ?fffff 16 (14 mbytes) 1 1 1 1 : 100000 16 ?fffff 16 (15 mbytes) bit bit name functions at reset rw 0 1 3 6 to 4 7 dram area select bits dram validity bit (note) 0 0 0 : invalid (p10 4 ?10 7 pins function as programmable input ports. a 0 a 7 pins function as address output pins. refresh timer stops counting.) 1 : valid (p10 4 ?10 7 pins function as cas, ras, ma 8 , and ma 9 . a 0 ? 7 function as ma 0 ?a 7 . refresh timer starts counting.) 0 dram control register (address 64 16 ) b1 b0 b2 b3 b4 b5 b6 b7 rw 0 rw nothing is assigned. the value is ??at reading. 2 0 rw b3 b2 b1 b0 rw 0 rw note: set the refresh timer (address 66 16 ) before setting this bit to ?. refresh timer b7 b0 refresh timer (address 66 16 ) functions bit at reset rw 7 to 0 these bits can be set to ?1 16 ?to ?f 16 . assuming that the set value = n, this register divides f 16 by (n + 1). undefined wo note: use the ldm or sta instruction for writing to this register. do not set this register to ?0 16 .
appendix appendix 3. control registers 7721 group users manual 17C31 dmac control register l 0 : fixed 1 : rotating bit bit name functions at reset rw 0 1 priority select bit undefined 0 0 : no request 1 : requested (note 1) 0 dmac control register l (address 68 16 ) b1 b0 b2 b3 b4 b5 b6 b7 rw rw 3, 2 0 rw 0 rw tc pin validity bit 0 : invalid (p10 3 pin functions as a programmable i/o port (cmos).) 1 : valid (p10 3 pin functions as tc pin (n- channel open-drain).) nothing is assigned. 4 5 6 7 dma0 request bit dma1 request bit dma2 request bit dma3 request bit 0rw 0 rw notes 1. the state of bits 4 to 7 are not changed when writing ??to these bits. 2. ?hen writing to this register while any of dmai enable bits (bits 4 to 7 at address 69 16 ) is ?,?set m flag to ??and use the ldm or sta instruction. when dmai request bit (bits 4 to 7 at address 68 16 ) must not be changed, set dmai request bit to ?. ?hen writing to this register while all of dmai enable bits (bits 4 to 7 at address 69 16 ) are ?,?m flag may be ??or ?.?use the ldm or sta instruction for writing to this register. when dmai request bit (bits 4 to 7 at address 68 16 ) must not be changed, set dmai request bit to ?. dmac control register h 1 : dma request (valid when software dma source is selected.) the value is ??at reading. bit bit name functions at reset rw 0 1 software dma0 request bit 0 0 : disabled 1 : enabled 0 dmac control register h (address 69 16 ) b1 b0 b2 b3 b4 b5 b6 b7 wo rw 0wo 0 rw 4 5 6 7 dma0 enable bit 0rw 0 rw 0 0 wo wo software dma1 request bit software dma2 request bit software dma3 request bit 2 3 dma0 enable bit dma1 enable bit dma2 enable bit dma3 enable bit note: when any of bits 4 to 7 is set to ?,?use the clb or seb instruction for writing to this register.
appendix appendix 3. control registers 7721 group users manual 17C32 interrupt control register b7 b6 b5 b4 b3 b2 b1 b0 dma0 to dma3, a-d conversion, uart0 and 1 transmit, uart0 and 1 receive, timers a0 to a4, timers b0 to b2 interrupt control registers (addresses 6c 16 to 7c 16 ) bit 7 to 4 interrupt request bit 2 1 0 bit name at reset 0 rw functions 0 0 0 : level 0 (interrupt disabled) 0 0 1 : level 1 0 1 0 : level 2 0 1 1 : level 3 1 0 0 : level 4 1 0 1 : level 5 1 1 0 : level 6 1 1 1 : level 7 b2 b1 b0 0 : no interrupt requested 1 : interrupt requested interrupt priority level select bits 3 rw rw rw rw undefined 0 0 0 nothing is assigned. note: the interrupt request bits of int 0 to int 2 interrupts are invalid when the level sense is selected. 0 : interrupt request bit is set to ?? at ??level when level sense is selected; this bit is set to ??at falling edge when edge sense is selected. 1 : interrupt request bit is set to ?? at ??level when level sense is selected; this bit is set to ??at rising edge when edge sense is selected. 0 0 0 : level 0 (interrupt disabled) 0 0 1 : level 1 0 1 0 : level 2 0 1 1 : level 3 1 0 0 : level 4 1 0 1 : level 5 1 1 0 : level 6 1 1 1 : level 7 b7 b6 b5 b4 b3 b2 b1 b0 int 0 to int 2 interrupt control registers (addresses 7d 16 to 7f 16 ) bit 4 interrupt request bit (note) 2 1 0 bit name at reset 0 rw functions b2 b1 b0 0 : no interrupt requested 1 : interrupt requested interrupt priority level select bits 3 rw rw rw rw rw 0 0 0 0 polarity select bit 0 : edge sense 1 : level sense 7, 6 5 rw 0 undefined level sense/edge sense select bit nothing is assigned.
appendix appendix 3. control registers 7721 group users manual 17C33 source address register i b7 b0 b15 b8 source address register 0 (addresses 1fc2 16 to 1fc0 16 ) source address register 1 (addresses 1fd2 16 to 1fd0 16 ) source address register 2 (addresses 1fe2 16 to 1fe0 16 ) source address register 3 (addresses 1ff2 16 to 1ff0 16 ) functions bit at reset rw 23 to 0 these bits have different functions according to the operating mode. undefined rw note: when writing to this register, write to all 24 bits. b23 b16 destination address register i b7 b0 b15 b8 destination address register 0 (addresses 1fc6 16 to 1fc4 16 ) destination address register 1 (addresses 1fd6 16 to 1fd4 16 ) destination address register 2 (addresses 1fe6 16 to 1fe4 16 ) destination address register 3 (addresses 1ff6 16 to 1ff4 16 ) functions bit at reset rw 23 to 0 these bits have different functions according to the operating mode. undefined rw note: when writing to this register, write to all 24 bits. b23 b16 transfer counter register i b7 b0 b15 b8 transfer counter register 0 (addresses 1fca 16 to 1fc8 16 ) transfer counter register 1 (addresses 1fda 16 to 1fd8 16 ) transfer counter register 2 (addresses 1fea 16 to 1fe8 16 ) transfer counter register 3 (addresses 1ffa 16 to 1ff8 16 ) functions bit at reset rw 23 to 0 these bits have different functions according to the operating mode. undefined rw note: when writing to this register, write to all 24 bits. do not write ?00000 16 ?to this register. b23 b16
appendix appendix 3. control registers 7721 group users manual 17C34 single transfer mode b7 b0 b15 b8 source address register 0 (addresses 1fc2 16 to 1fc0 16 ) source address register 1 (addresses 1fd2 16 to 1fd0 16 ) source address register 2 (addresses 1fe2 16 to 1fe0 16 ) source address register 3 (addresses 1ff2 16 to 1ff0 16 ) functions bit at reset rw 23 to 0 [write] set the transfer start address of the source. these bits can be set to ?00000 16 ?to ?fffff 16 . [read] the read value indicates the source address of data which is next transferred. undefined rw note: when writing to this register, write to all 24 bits. b23 b16 b7 b0 b15 b8 destination address register 0 (addresses 1fc6 16 to 1fc4 16 ) destination address register 1 (addresses 1fd6 16 to 1fd4 16 ) destination address register 2 (addresses 1fe6 16 to 1fe4 16 ) destination address register 3 (addresses 1ff6 16 to 1ff4 16 ) functions bit at reset rw 23 to 0 [write] set the transfer start address of the destination. these bits can be set to ?00000 16 ?to ?fffff 16 . [read] the read value indicates the destination address of data which is next transferred. undefined rw note: when writing to this register, write to all 24 bits. b23 b16 b7 b0 b15 b8 transfer counter register 0 (addresses 1fca 16 to 1fc8 16 ) transfer counter register 1 (addresses 1fda 16 to 1fd8 16 ) transfer counter register 2 (addresses 1fea 16 to 1fe8 16 ) transfer counter register 3 (addresses 1ffa 16 to 1ff8 16 ) functions bit at reset rw 23 to 0 [write] set the byte number of the transfer data. these bits can be set to ?00001 16 ?to ?fffff 16 . [read] the read value indicates remaining byte number of the transfer data. undefined rw note: when writing to this register, write to all 24 bits. do not set this register to ?00000 16 . b23 b16
appendix appendix 3. control registers 7721 group users manual 17C35 repeat transfer mode b7 b0 b15 b8 source address register 0 (addresses 1fc2 16 to 1fc0 16 ) source address register 1 (addresses 1fd2 16 to 1fd0 16 ) source address register 2 (addresses 1fe2 16 to 1fe0 16 ) source address register 3 (addresses 1ff2 16 to 1ff0 16 ) functions bit at reset rw 23 to 0 [write] set the transfer start address of the source. these bits can be set to ?00000 16 ?to ?fffff 16 . [read] the read value indicates the source address of data which is next transferred. undefined rw note: when writing to this register, write to all 24 bits. b23 b16 b7 b0 b15 b8 destination address register 0 (addresses 1fc6 16 to 1fc4 16 ) destination address register 1 (addresses 1fd6 16 to 1fd4 16 ) destination address register 2 (addresses 1fe6 16 to 1fe4 16 ) destination address register 3 (addresses 1ff6 16 to 1ff4 16 ) functions bit at reset rw 23 to 0 [write] set the transfer start address of the destination. these bits can be set to ?00000 16 ?to ?fffff 16 . [read] the read value indicates the destination address of data which is next transferred. undefined rw note: when writing to this register, write to all 24 bits. b23 b16 b7 b0 b15 b8 transfer counter register 0 (addresses 1fca 16 to 1fc8 16 ) transfer counter register 1 (addresses 1fda 16 to 1fd8 16 ) transfer counter register 2 (addresses 1fea 16 to 1fe8 16 ) transfer counter register 3 (addresses 1ffa 16 to 1ff8 16 ) functions bit at reset rw 23 to 0 [write] set the byte number of the transfer data. these bits can be set to ?00001 16 ?to ?fffff 16 . [read] the read value indicates the remaining byte number of the block which is being transferred. undefined rw note: when writing to this register, write to all 24 bits. do not write ?00000 16 ?to this register. b23 b16
appendix appendix 3. control registers 7721 group users manual 17C36 array chain transfer mode b7 b0 b15 b8 source address register 0 (addresses 1fc2 16 to 1fc0 16 ) source address register 1 (addresses 1fd2 16 to 1fd0 16 ) source address register 2 (addresses 1fe2 16 to 1fe0 16 ) source address register 3 (addresses 1ff2 16 to 1ff0 16 ) functions bit at reset rw 23 to 0 [write] set the start address of transfer parameter memory. these bits can be set to ?00000 16 ?to ?fffff 16 . [read] ?fter a value is written to this register and until transfer starts, the read value indicates the written value (the start address of the transfer parameter memory). ?fter tranfer starts, the read value indicates the source address of data which is next transferred. undefined rw note: when writing to this register, write to all 24 bits. b23 b16 b7 b0 b15 b8 destination address register 0 (addresses 1fc6 16 to 1fc4 16 ) destination address register 1 (addresses 1fd6 16 to 1fd4 16 ) destination address register 2 (addresses 1fe6 16 to 1fe4 16 ) destination address register 3 (addresses 1ff6 16 to 1ff4 16 ) functions bit at reset rw 23 to 0 need not to set. [read] after transfer starts, the read value indicates the destination address of data which is next transferred. undefined rw b23 b16 b7 b0 b15 b8 transfer counter register 0 (addresses 1fca 16 to 1fc8 16 ) transfer counter register 1 (addresses 1fda 16 to 1fd8 16 ) transfer counter register 2 (addresses 1fea 16 to 1fe8 16 ) transfer counter register 3 (addresses 1ffa 16 to 1ff8 16 ) functions bit at reset rw 23 to 0 [write] set the number of transfer blocks. these bits can be set to ?00001 16 ?to ?fffff 16 . [read] ?fter a value is written to this register and until transfer starts, the read value indicates the written value (the transfer block number) . ?fter transfer starts, the read value indicates the remaining byte number of the block which is being transferred. undefined rw note: when writing to this register, write to all 24 bits. do not write ?00000 16 ?to this register. b23 b16
appendix appendix 3. control registers 7721 group users manual 17C37 link array chain transfer mode b7 b0 b15 b8 source address register 0 (addresses 1fc2 16 to 1fc0 16 ) source address register 1 (addresses 1fd2 16 to 1fd0 16 ) source address register 2 (addresses 1fe2 16 to 1fe0 16 ) source address register 3 (addresses 1ff2 16 to 1ff0 16 ) functions bit at reset rw 23 to 0 [write] set the start address of transfer parameter memory of block which is first transferred. these bits can be set to 000000 16 to ffffff 16 . [read] ?after a value is written to this register and until transfer starts, the read value indicates the written value (the start address of the transfer parameter memory of block which is first transferred). ?after transfer starts, the read value indicates the source address of data which is next transferred. undefined rw note: when writing to this register, write to all 24 bits. b23 b16 b7 b0 b15 b8 destination address register 0 (addresses 1fc6 16 to 1fc4 16 ) destination address register 1 (addresses 1fd6 16 to 1fd4 16 ) destination address register 2 (addresses 1fe6 16 to 1fe4 16 ) destination address register 3 (addresses 1ff6 16 to 1ff4 16 ) functions bit at reset rw 23 to 0 need not to set. [read] after transfer starts, the read value indicates the destination address of data which is next transferred. undefined rw b23 b16 b7 b0 b15 b8 transfer counter register 0 (addresses 1fca 16 to 1fc8 16 ) transfer counter register 1 (addresses 1fda 16 to 1fd8 16 ) transfer counter register 2 (addresses 1fea 16 to 1fe8 16 ) transfer counter register 3 (addresses 1ffa 16 to 1ff8 16 ) functions bit at reset rw 23 to 0 [write] set the dummy data. these bits can be set to 000001 16 to ffffff 16 . [read] ?after a value is written to this register and until transfer starts, the read value indicates the written value (dummy data). ?after transfer starts, the read value indicates the remaining byte number of the block which is being transferred. undefined rw note: when writing to this register, write to all 24 bits. do not write 000000 16 to this register. b23 b16
appendix appendix 3. control registers 7721 group users manual 17C38 dmai mode register l bit bit name at reset 5 0 rw functions b7 b6 b5 b4 b3 b2 b1 b0 dma0 mode register l (address 1fcc 16 ) dma1 mode register l (address 1fdc 16 ) dma2 mode register l (address 1fec 16 ) dma3 mode register l (address 1ffc 16 ) note: when the external data bus has a width of 8 bits and 1-bus cycle transfer is selected, set bit 0 to ?. 0 0 0 : 16 bits 1 : 8 bits 1 0 : 2-bus cycle transfer 1 : 1-bus cycle transfer 2 0 0 : burst transfer mode 1 : cycle-steal transfer mode 3 0 4 0 0 0 : fixed 0 1 : forward 1 0 : backward 1 1 : do not select. 6 0 7 rw rw 0 number-of-unit-transfer-bits select bit (note) transfer method select bit transfer mode select bit fix this bit to ?. transfer source address direction select bits transfer destination address direction select bits 0 0 : fixed 0 1 : forward 1 0 : backward 1 1 : do not select. b5b4 b7b6 rw rw rw rw 0 0 rw rw dmai mode register h bit bit name at reset 5 0 rw functions b7 b6 b5 b4 b3 b2 b1 b0 dma0 mode register h (address 1fcd 16 ) dma1 mode register h (address 1fdd 16 ) dma2 mode register h (address 1fed 16 ) dma3 mode register h (address 1ffd 16 ) notes 1: set bit 0 to ??in 2-bus cycle transfer. 2: bits 4 and 5 are valid to the external and internal areas. however, dram area is always handled with ?ait?regardless of the contents of these bits. the wait bit (bit 2 at address 5e 16 ) is invalid in dma transfer. 0 0 0 : from memory to i/o 1 : from i/o to memory 1 refer to fig.13.2.7. 2 0 3 0 4 0 6 0 7 rw rw 0 transfer direction select bit (used in 1-bus cycle transfer) (note 1) i/o connection select bit (valid in 1-bus cycle transfer) fix these bits to ?. transfer source wait bit (note 2) continuous transfer mode select bits 0 0 : single transfer 0 1 : repeat transfer 1 0 : array chain transfer 1 1 : link array chain transfer b7b6 rw rw rw rw 0 0 rw rw 0 transfer destination wait bit (note 2) 0 : wait 1 : no wait
appendix appendix 3. control registers 7721 group users manual 17C39 dmai control register bit bit name at reset 5 0 rw functions b7 b6 b5 b4 b3 b2 b1 b0 dma0 control register (address 1fce 16 ) dma1 control register (address 1fde 16 ) dma2 control register (address 1fee 16 ) dma3 control register (address 1ffe 16 ) note: when a certain source other than an external source is selected by bits 0 to 3 or when the cycle-steal transfer mode is selected, set bit 4 to 0. level sense can be selected only when both of the external source and the burst transfer mode are selected. 0 0 0 0 0 0 : do not select. 0 0 0 1 : external source (dmareqi) 0 0 1 0 : software dma source 0 0 1 1 : timer a0 0 1 0 0 : timer a1 0 1 0 1 : timer a2 0 1 1 0 : timer a3 0 1 1 1 : timer a4 1 0 0 0 : timer b0 1 0 0 1 : timer b1 1 0 1 0 : timer b2 1 0 1 1 : uart0 receive 1 1 0 0 : uart0 transmit 1 1 0 1 : uart1 receive 1 1 1 0 : uart1 transmit 1 1 1 1 : a-d conversion 1 2 0 3 0 4 0 0 7, 6 rw rw dma request source select bits (note) edge sense/level sense select bit (used when external source and burst transfer mode are selected) (note) dmaacki validity bit 0 : invalid (the pin functions as a programmable i/o port.) 1 : valid (the pin functions as dmaacki.) rw rw rw rw undefined C 0 : edge sense (falling edge) 1 : level sense (l level) nothing is assigned. b3b2b1b0
appendix appendix 4. package outline 7721 group users manual 17C40 appendix 4. package outline
appendix 7721 group users manual 17C41 appendix 5. examples of handling unused pins appendix 5. examples of handling unused pins examples of handling unused pins are described below. these descriptions are just examples. the user shall modify them according to the actual application and test them. table 1 examples of handling unused pins handling example connect these pins to the vcc or vss pin via resistors after these pins are set to the input mode, or leave these pins open after they are set to the output mode (notes 1, 2) . leave this pin open. leave this pin open. connect these pins to the vcc pin via resistors (these pins are pulled high.) (note 2) connect this pin to the vcc pin or vss pin. connect this pin to the vcc pin. connect these pins to the vss pin. pins p4 3 to p4 7 , p5 to p10 ____ ____ ble, bhe, ale, f 1 , st0, st1 x out (note 3) _____ ____ hold, rdy cnvss avcc avss, v ref p4 3 Cp4 7 , p5Cp10 m37721 v ss hold rdy av cc cnv ss av ss v ref v cc left open l when setting ports to input mode l when setting ports to output mode st0 st1 ble bhe ale 1 x out left open ] p4 3 Cp4 7 , p5Cp10 m37721 v ss hold rdy av cc cnv ss av ss v ref v cc left open st0 st1 ble bhe ale 1 x out left open ] left open ] cnvss pin can be connected to vcc pin. notes 1: when leaving these pins open after they are set to the output mode, note the following: these pins function as input ports from reset until they are switched to the output mode by software. therefore, voltage levels of these pins are undefined and the power source current may increase while these pins function as input ports. accordingly, set these ports to the output mode immediately after reset. software reliability can be enhanced when the contents of the above ports direction registers are set periodically. this is because these contents may be changed by noise, a program runaway which occurs to noise, etc. 2: for unused pins, use the shortest possible wiring (within 20 mm from the microcomputers pins). 3: this applies when a clock externally generated is input to the x in pin. fig. 2 examples of handling unused pins
appendix appendix 6. machine instructions 7721 group users manual 17C42 a cc ,c ? a cc +m+c a cc ? a cc m symbol functions details adds the carry, the accumulator and the memory contents.the result is entered into the accumulator. when the d flag is 0, binary additions is done, and when the d flag is 1, decimal addition is done. obtains the logical product of the contents of the accumu- lator and the contents of the memory . the result is en- tered into the accumulator. shifts the accumulator or the memory contents one bit to the left. 0 is entered into bit 0 of the accumulator or the memory. the contents of bit 15 ( bit 7 when the m flag is 1) of the accumulator or memory before shift is entered into the c flag. tests the specified bit of the memory. branches when all the contents of the specified bit is 0. tests the specified bit of the memory. branches when all the contents of the specified bit is 1. branches when the contents of the c flag is 0. branches when the contents of the c flag is 1. branches when the contents of the z flag is 1. branches when the contents of the n flag is 1. branches when the contents of the z flag is 0. branches when the contents of the n flag is 0. jumps to the address indicated by the program counter plus the offset value. executes software interruption. branches when the contents of the v flag is 0. branches when the contents of the v flag is 1. makes the contents of the specified bit in the memory 0. makes the contents of the c flag 0. makes the contents of the i flag 0. specifies the bit position in the processor status register by the bit pattern of the second byte in the instruction, and sets 0 in that bit. makes the contents of the v flag 0. compares the contents of the accumulator with the con- tents of the memory. mb=0? mb=1? c=0? c=1? z=1? n=1? z=0? n=0? pc ? pcoffset pg ? pg+1 ( when carry occurs ) pg ? pgC1 ( when borrow occurs ) pc ? pc+2 m(s) ? pg s ? sC1 m(s) ? pc h s ? sC1 m(s) ? pc l s ? sC1 m(s) ? ps h s ? sC1 m(s) ? ps l s ? sC1 i ? 1 pc l ? ad l pc h ? ad h pg ? 00 16 v=0? v=1? c ? 0 mb ? 0 makes the contents of the m flag 0. i ? 0 m ? 0 psb ? 0 v ? 0 a cc Cm imp imm a dir dir,b dir,x dir,y (dir) (dir,x) (dir),y op n n op addressing modes and (notes 1,2) adc (notes 1,2) asl (note 1) bbc (notes 3,5) bbs (notes 3,5) bcc (note 3) bcs (note 3) beq (note 3) bmi (note 3) bne (note 3) bpl (note 3) bra (note 4) brk bvc (note 3) bvs (note 3) clb (note 5) clc cli clm clv cmp (notes 1,2) clp n n op n 58 d8 1 1 1 21 29 c2 222 61 72 71 2 3 42 75 3 42 72 3 42 61 3 42 71 10 3 2 35 32 2 21 31 82 43 3 42 32 3 42 21 3 4 1 2 72 16 72 3 4 2 4 d5 42 31 10 3 c1 d1 42 d1 8 10 2 3 42 c1 2 2 3 2 3 6 2 3 7 5 7 2 5 7 5 8 6 8 6 8 6 m=0 c ? b 15 b 0 ? 0 m=1 c ? b 7 b 0 ? 0 # op n# op n# op n# 69 2 65 2 4 42 69 43 42 65 6 75 72 # op op n# op # op #n# # 8 9 22 25 472 42 29 3 42 25 6 42 35 93 0a 2 06 42 0a 00 15 2 14 8 18 2 2 2 2 b8 c9 42 c9 42 c5 4 c5 42 d5 42 d2 d2 7 93 2 appendix 6. machine instructions
appendix 6. machine instructions appendix 7721 group users manual 17C43 processor status register addressing modes l(dir) l(dir),y abl,x (abs) stk rel sr (sr),y blk abs,b abs,x abs,y dir,b,r abs,b,r ( abs,x ) 30 op op op n n n n n n n n abs ipl n v m c 2 85 64 diz n op op op n n n op op n op 67 42 67 10 2 3 42 77 3 4 42 7d 6 8 3 4 42 79 8 3 4 6 8 4 5 42 7f 7 9 4 5 op 63 5 7 2 3 73 10 3 42 23 5 7 2 3 33 42 33 8 10 2 3 10 2 37 12 3 42 37 0e 3 663 2f 64 3f 74 42 3d 8 3 4 42 39 84 42 2f 5 8 42 3f 95 1e 83 ??nv? x ?? ?zc ? z ? ? ? ? ? n ? ??n?? ?? ?zc 5 3c 8 4 7 90 42 24 74 2c 85 b0 f0 30 4 4 4 2 2 2 2 4 d0 10 42 82 4 4 2 3 50 42 2 4 ic 94 ???????? ? ? ? ? ? ? ? ? ? ? ? ? ???? ???? ? ? ? ? ? ? ? ? ?? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?? ?? ????? ???? ????? ?? ?? ????? ? ? ? ? ? ? ? ? ? ? ? ??? ? ?????? 0 ? ? ? ? ? ? ? ? ? ? ???? ???0?? ? ? c ? ? z ? ? ? ? ? ? ? ? ? 0 ? ? ? 0 ? ? ? ? ? ? ? ? ? ? ? c3 52 8 d3 2 42 d3 3 10 3 7 42 c3 c7 10 2 d7 11 2 cd 3 dd 63 42 c7 3 13 34 d9 63 84 84 cf 64 df 74 85 95 42 df op # op ## # op op # op #n# # # op ## op # n#n# op # 1 7 ## l(abs) abl # nn 77 11 2 6d 4 7d 6 79 6f 7f 2 8 42 73 42 63 42 6f 42 6d 13 36 12 27 11 2 2d 3 3d 39 23 42 27 13 3 42 2d 4 64 7 34 80 ? 70 12 42 d7 42 cd 4 6 42 dd 42 d9 42 cf 9 10 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?? ? ? ? ? ? ? ? ? specified flag be- comes 0. n
appendix appendix 6. machine instructions 7721 group users manual 17C44 symbol functions details imp imm dir dir,b dir,x dir,y (dir) (dir,x) (dir),y n op op op n nn op n op addressing modes compares the contents of the index register x with the contents of the memory. compares the contents of the index register y with the contents of the memory. decrements the contents of the accumlator or memory by 1. decrements the contents of the index register x by 1. decrements the contents of the index register y by 1. the numeral that places the contents of accumlator b to the higher order and the contents of accumulator a to the lower order is divided by the contents of the memory. the quotient is entered into accumula- tor a and the remainder into accumulator b. logical exclusive sum is obtained of the contents of the accumulator and the contents of the memory. the result is placed into the accumulator. increments the contents of the accumulator or memory by 1. increments the contents of the index register x by 1. increments the contents of the index register y by 1. places a new address into the program counter and jumps to that new address. xCm yCm a cc ? a cc C1 or m ? mC1 x ? xC1 y ? yC1 a(quotient) ? b,a/m b(remainder) a cc ? a cc m a cc ? a cc +1 or m ? m+1 x ? x+1 y ? y+1 abs pc l ? ad l pc h ? ad h abl pc l ? ad l pc h ? ad h pg ? ad g (abs) pc l ? (ad h , ad l ) pc h ? (ad h ,ad l +1) l(abs) pc l ? (ad h , ad l ) pc h ? (ad h , ad l +1) pg ? (ad h , ad l +2) (abs, x) pc l ? (ad h , ad l +x) pc h ? (ad h , ad l +x +1) abs m(s) ? pc h s ? sC1 m(s) ? pc l s ? sC1 pc l ? ad l pc h ? ad h abl m(s) ? pg s ? sC1 m(s) ? pc h s ? sC1 m(s) ? pc l s ? sC1 pc l ? ad l pc h ? ad h pg ? ad g (abs, x) m(s) ? pc h s ? sC1 m(s) ? pc l s ? sC1 pc l ? (ad h , ad l +x) pc h ? (ad h , ad l +x +1) cpx (note 2) cpy (note 2) dec (note 1) dex dey div (notes 2,10) eor (notes 1,2) inc (note 1) inx jmp iny jsr saves the contents of the program counter (also the con- tents of the program bank register for abl) into the stack, and jumps to the new address. n op nn op op n op op n e0 2 e4 42 c4 4 2 1a 21 42 c6 72 d6 21 2 89 29 89 25 29 3 89 35 30 3 89 32 31 3 89 21 32 3 89 31 33 3 49 2 45 42 55 52 62 72 51 82 42 49 42 45 63 42 55 73 42 52 83 42 41 93 10 3 3a 21 42 3a 42 e6 77 e8 c8 21 2 ### # ### ### a 2 c0 2 2 2 7 42 1a 88 ca 1 3 27 41 52 42 51 f6 43 2 1 2 2
appendix 6. machine instructions appendix 7721 group users manual 17C45 1 processor status register addressing modes l(dir),y abl abl,x (abs) l(abs) stk rel (sr),y blk abs,y dir,b,r abs,b,r ( abs,x ) 30 op # op op op n n n n op n n n abs op ipl n v m c 2 85 64 10 9 diz n nn op op n op n op n op op n n op 3 op ??n? ? x ?? ?z 4 op 47 42 47 35 10 12 3 2 3 89 37 57 42 57 3 36 11 13 2 3 4 42 4d ee 20 83 31 89 2f 31 5 89 3f 32 5 89 3d 31 4 5d 63 42 5d 84 fe 3 8 59 42 59 6 84 3 42 4f 85 4f 64 42 5f 5f 95 74 5c 44 22 84 dc 33 86 7c 3 3 fc 8 89 23 30 3 89 33 73 43 42 43 52 42 53 53 10 3 33 8 3 2 ??n?? ???zc ? ?? n? ? ?z ?? ? z ? ? ? ? n ? ? ?? ? ? n? ? ??z? ? vc z ? ? ? ? ? ?n ? ?? n? ? ?z ?? ? ?? n? ? ?z ?? ?? ??? ?????? ?????????? ??n? ?? ?? ? ?? ? ???? ? nz z l(dir) abs,b abs,x ### # op ## n# # ## n op op ##n# sr #### 7 ? ? ? c ? ? ? ? ? ? ? cc ec 43 ce 73 de 89 27 89 2d 29 89 39 4 3 4 4d 64 3 7 3 2 4c 3 6 4 6c
appendix appendix 6. machine instructions 7721 group users manual 17C46 symbol functions details imp imm a dir dir,b dir,x dir,y (dir) (dir,x) (dir),y # n op n op n op n op addressing modes a cc ? m m ? imm dt ? imm x ? m y ? m m=0 0 ? b 15 b 0 ? c m=1 0 ? b 7 b 0 ? c enters the contents of the memory into the accummulator. enters the immediate vaiue into the memory. enters the immediate value into the data bank regiater. enters the contents of the memory into index register x. enters the contents of the memory into index register y. shifts the contents of the accumulator or the contents of the memory one bit to the right. the bit 0 of the accumu- lator or the memory is entered into the c flag. 0 is en- tered into bit 15 (bit 7 when the m flag is 1.) b, a ? a ] m mn+i ? mm+i mnCi ? mmCi pc ? pc+1 a cc ? a cc vm m(s) ? imm 2 s ? sC1 m(s) ? imm 1 s ? sC1 m(s) ? m((dpr)+imm +1) s ? sC1 m(s) ? m((dpr)+imm) s ? sC1 ear ? pc+imm 2 ,imm 1 m(s) ? ear h s ? sC1 m(s) ? ear l s ? sC1 m=0 m(s) ? a h s ? sC1 m(s) ? a l s ? sC1 m=1 m(s) ? a l s ? sC1 m=0 m(s) ? b h s ? sC1 m(s) ? b l s ? sC1 m=1 m(s) ? b l s ? sC1 transmits the data block. the transmission is done from the lower order address of the block. advances the program counter, but pertorms nothing else. logical sum per bit of the contents of the accumulator and the contents of the memory is obtained. the result is en- tered into the accumulator. the 3rd and the 2nd bytes of the instruction are saved into the stack, in this order. specifies 2 sequential bytes in the direct page in the 2nd byte of the instruction, and saves the contents into the stack. regards the 2nd and 3rd bytes of the instruction as 16-bit numerals, adds them to the program counter, and saves the result into the stack. saves the contents of accumulator a into the stack. saves the contents of accumuator b into the stack. lda (notes 1,2) ldm (note 5) ldt ldx (note 2) ldy (note 2) lsr (note 1) mpy (notes 2,11) mvn (note 8) mvp (note 9) nop ora (notes 1,2) pea pei per pha phb n op nn op op op n n op op n 252 b2 62 2 43 74 53 a6 42 2 2 a4 42 5 2 21 46 72 56 72 89 09 16 3 89 05 89 15 19 3 89 12 20 333 21 09 22 05 42 05 4 6 2 3 52 3 7 42 15 12 6 8 2 3 01 42 01 7 9 2 3 11 42 11 10 3 3 463 3 7 42 b2 3 8933 10 2 42 09 multiplies the contents of accumulator a and the contents of the memory. the higher order of the result of operation are entered into accumulator b, and the lower order into accumulator a. transmits the data block. transmission is done form the higher order address of the data block. ### ###### a9 22 42 a9 89 c2 53 64 42 a5 a5 4 b5 42 b5 a1 42 a1 72 b1 42 b1 8 b6 5 b4 a0 a2 2 2 2 4a 42 4a 2 4 89 11 22 89 01 21 18 3 ea 43 15 42 12 8
appendix 6. machine instructions appendix 7721 group users manual 17C47 1 processor status register addressing modes abl abl,x (abs) stk (sr),y abs,x abs,y abs,b,r ( abs,x ) 30 op n op n n n n n abs ipl n v m c 2 87 5 64 10 9 diz n n op n op n op n op op ?n? x ?? op op n op op op op op n op op op n op a7 2 b7 11 2 ad 43 3 b9 63 af 64 bf 7 n a3 52 b3 42 a7 3 13 3 42 ad 42 bd 4 42 b9 84 42 af 85 42 bf 9 4 5 42 a3 73 42 b3 10 3 9c 54 4 43 be 63 ac 43 3 4e 73 3 89 07 24 33 89 0d 44 89 19 20 4 89 0f 20 5 89 03 19 3 07 10 2 17 11 2 0d 43 89 1f 21 5 1d 63 19 63 0f 64 1f 74 03 52 13 82 42 07 12 3 42 17 13 3 42 0d 64 42 1d 84 42 19 84 42 0f 85 42 1f 95 42 03 73 42 13 10 3 f4 53 d4 62 62 53 48 41 42 48 62 54 73 i + 5 7 2 3 9 + i 5 7 2 ????z ???? ?????? ?? ? ? ?? ?? ? ? ? ? ? n n? ?? ? ? ? ??z? ? z ? ? ? ? ? ? ? ? ? 0 n ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? z z ? c 0 ? ? ? ? ? ? ? ? ? z ? ? ? ? ? ? ? ?? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? n ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?? ? ? ### ## # ###n# ### #### ? ? ? ? ? ? ? ? ? ? ? ? blk sr dir,b,r 44 rel l(abs) abs,b l(dir),y l(dir) # 10 12 n 42 b7 4 6 bd n 6 8 6 9e bc 5e ae 89 17 25 18 89 1d 20 3 2 8 89 13 22 6 8
appendix 6. machine instructions appendix 7721 group users manual 17C48 symbol functions details imp imm a dir dir,b dir,x dir,y (dir) (dir,x) (dir),y op n op n n n n nnn n addressing modes phd m(s) ? dpr h s ? sC1 m(s) ? dpr l s ? sC1 saves the contents of the direct page register into the stack. m(s) ? pg s ? sC1 m(s) ? ps h s ? sC1 m(s) ? ps l s ? sC1 m(s) ? dt s ? sC1 x=0 m(s) ? x h s ? sC1 m(s) ? x l s ? sC1 x=1 m(s) ? x l s ? sC1 x=0 m(s) ? y h s ? sC1 m(s) ? y l s ? sC1 x=1 m(s) ? y l s ? sC1 m=0 s ? s+1 a l ? m(s) s ? s+1 a h ? m(s) m=1 s ? s+1 a l ? m(s) m=0 s ? s+1 b l ? m(s) s ? s+1 b h ? m(s) m=1 s ? s+1 b l ? m(s) s ? s+1 dpr l ? m(s) s ? s+1 dpr h ? m(s) s ? s+1 ps l ? m(s) s ? s+1 ps h ? m(s) s ? s+1 dt ? m(s) x=0 s ? s+1 x l ? m(s) s ? s+1 x h ? m(s) x=1 s ? s+1 x l ? m(s) phg php pht phx phy saves the contents of the program bank register into the stack. saves the contents of the program status register into the stack. saves the contents of the data bank register into the stack. saves the contents of the index register x into the stack. saves the contents of the index register y into the stack. pla restores the contents of the stack on the accumulator a. restores the contents of the stack on the accumulator b. restores the contents of the stack on the direct page reg- ister. restores the contents of the stack on the processor status register. restores the contents of the stack on the data bank reg- ister. restores the contents of the stack on the index register x. plb pld plp plt plx op op op op op op op # # # # # # # # # # op n
appendix 6. machine instructions appendix 7721 group users manual 17C49 processor status register addressing modes l(dir) l(dir),y abl abl,x (abs) l(abs) stk sr (sr),y blk abs,b abs,x abs,y dir,b,r abs,b,r ( abs,x ) 10 98 76 5 2 30 op n op op op op op op op n op n op op op op op n n n n op n n op op n n n n op n n n n n abs 41 31 4 08 1 8b 3 1 41 5a 41 68 51 42 72 2b 1 1 6 28 ab 61 fa 51 68 ipl n v m x d i c z ? ? ? ? ? ? ? ? n ?? ? ? ? z? ? ? ? n ?? ? ? ? z? ? ? ? n ?? ? ? ? z? ? ? ? n ?? ? ? ? z? 5 value saved in stack. ? ? ? ? ?? 0b da 41 ? ? ? ? ?? ? ? ? ?? ? ? ? ? ?? ? ? ? ?? ? ? ? ? ?? ? ? ? ?? ? ? ? ? ?? ? ? ? ?? ? ? ? ? ?? ? ? ? ?? ? ? ? ? ?? ? ? ? ?? 4b #### ## # ########### rel
appendix 6. machine instructions appendix 7721 group users manual 17C50 3 symbol functions details imp imm a dir dir,b dir,x dir,y (dir) (dir,x) (dir),y op n op op n op n n op op n op nn op op n op addressing modes ply x=0 s ? s+1 y l ? m(s) s ? s+1 y h ? m(s) x=1 s ? s+1 y l ? m(s) restores the contents of the stack on the index register y. m(s) ? a, b, x saves the registers among accumulator, index register, direct page register, data bank register, program bank register, or processor status register, specified by the bit pattern of the second byte of the instruction into the stack. restores the contents of the stack to the registers among accumulator, index register, direct page register, data bank register, or processor status register, specified by the bit pattern of the second byte of the instruction. m=0 n bit rotate left ? b 15 b 0 ? m=1 n bit rotate left ? b 7 b 0 ? a, b, x ? m(s) psh (note 6) pul (note 7) rla (note 13) rotates the contents of the accumulator a, n bits to the left. m=0 ? b 15 b 0 ? c ? m=1 ? b 7 b 0 ? c ? rol (note 1) links the accumulator or the memory to c flag, and rotates result to the left by 1 bit. m=0 ? c ? b 15 b 0 ? m=1 ? c ? b 7 b 0 ? ror (note 1) links the accumulator or the memory to c flag, and rotates result to the right by 1 bit. s ? s+1 ps l ? m(s) s ? s+1 ps h ? m(s) s ? s+1 pc l ? m(s) s ? s+1 pc h ? m(s) s ? s+1 pg ? m(s) s ? s+1 pc l ? m(s) s ? s+1 pc h ? m(s) s ? s+1 pg ? m(s) s ? s+1 pc l ? m(s) s ? s+1 pc h ? m(s) a cc , c ? a cc CmCc rti rtl rts sbc (notes 1,2) returns from the interruption routine. returns from the subroutine. the contents of the program bank register are also restored. returns from the subroutine. the contents of the program bank register are not restored. subtracts the contents of the memory and the borrow from the contents of the accumulator. 81 6b 60 51 40 11 1 6a 21 66 72 42 4 2 6a 72 1 2 26 72 36 7 2 2a 42 42 89 63 49 2 2 e5 4 2 f5 5 26 f2 2 e1 7 2 f1 2 3 42 9 f1 e1 42 83 f2 42 73 f5 42 63 e5 4 e9 3 2a 76 + i e9 42 8 10 42 # ##n# ###### n
appendix 6. machine instructions appendix 7721 group users manual 17C51 processor status register addressing modes l(dir) l(dir),y abl abl,x (abs) l(abs) stk rel sr (sr),y blk abs,b abs,x abs,y dir,b,r abs,b,r ( abs,x ) 10 98 76 5 2 30 op n op op op op op op op op op op op op op n n n n op n op op n n n op n n n n n abs 1 ipl v m x d i c z 7a 41 ? ? ? n ?? ? ? ? z? ? ? ? ? ?? ? ? ? ?? n if restored the contents of ps, it becomes its value. and the other cases are no change. ? ? ? n ?? ? ? ? z ? ? ? n v? ? ? ? z c ? ? ? ? ?? ? ? ? ?? value saved in stack. ? ? ? n ?? ? ? ? z c ? ? ? ? ?? ? ? ? ?? 5 eb 12 2 2 14 fb 3i 1 +4i 2 3e 83 6e 3 8 7e 2e 73 73 52 e3 ed e7 f7 2 f7 11 2 10 ed 43 4 42 12 3 42 6 42 13 3 f9 ef ff 84 42 8 42 485 42 9 fd 63 f9 63 ef 6 ff 74 82 f3 42 73 42 10 3 e3 f3 ? ? ? ? ?? ? ? ? ?? # ## # n# # n n# # # # n # # # # # # # # e7 42 fd 4 5 c + 2i 1 +i 2 +
appendix appendix 6. machine instructions 7721 group users manual 17C52 symbol functions details imp imm a dir dir,b dir,x dir,y (dir) (dir,x) (dir),y op n op op n op n n op op n op nn op op op addressing modes makes the contents of the specified bit in the memory 1. makes the contents of the i flag 1. makes the contents of the m flag 1. set the specified bit of the processor status register's lower byte (ps l ) to 1. stores the contents of the accumulator into the memory. stops the oscillation of the oscillator. stores the contents of the index register x into the memory. stores the contents of the index register y into the memory. transmits the contents of the accumulator a to the direct page register. transmits the contents of the accumulator a to the stack pointer. transmits the contents of the accumulator a to the index register x. transmits the contents of the accumulator a to the index register y. transmits the contents of the accumulator b to the direct page register. transmits the contents of the accumulator b to the stack pointer. transmits the contents of the accumulator b to the index register x. transmits the contents of the accumulator b to the index register y. transmits the contents of the direct page register to the accumulator a. transmits the contents of the direct page register to the accumulator b. makes the contents of the c flag 1. seb (note 5) mb ? 1 sec sei sem sep sta (note 1) stp stx sty tad tas c ? 1 i ? 1 m ? 1 psb ? 1 m ? a cc m ? x m ? y dpr ? a s ? a x ? a y ? a dpr ? b s ? b tax tay tbd tbs tdb x ? b tbx tby tda y ? b a ? dpr b ? dpr 42 2 2 04 83 38 21 78 21 2 f8 1 2 3 db 31 2 4 85 42 6 85 3 3 9 42 3 9 42 7 42 2 5 95 72 81 72 91 72 91 3 81 92 95 2 4 86 2 4 84 52 96 94 2 5 5b 21 1b 21 aa 21 a8 21 4 42 2 5b 42 42 1b 42 aa 42 4 a8 7b 21 42 4 7b transmits the contents of the stack pointer to the accumulator a. transmits the contents of the stack pointer to the accu- mulator b. a ? s b ? s tsa tsb 3b 21 42 42 transmits the contents of the stack pointer to the index register x. transmits the contents of the index register x to the ac- cumulator a. x ? s a ? x tsx txa transmits the contents of the index register x to the ac- cumulator b. transmits the contents of the index register x to the stack pointer. b ? x s ? x txb txs transmits the contents of the index register x to the index register y. y ? x txy transmits the contents of the index register y to the ac- cumulator a. a ? y tya tyb b ? y transmits the contents of the index register y to the index register x. stops the internal clock. exchanges the contents of the accumulator a and the con- tents of the accumulator b. tyx wit xab x ? y a b ? ? ba 21 21 42 2 4 8a 9a 21 9b 21 98 21 42 42 98 transmits the contents of the index register y to the ac- cumulator b. bb 21 cb 31 2 6 89 28 8a 3b e2 92 9 3 42 ###n# ### n# # # n
appendix 6. machine instructions appendix 7721 group users manual 17C53 addressing modes l(dir) l(dir),y abl abl,x (abs) l(abs) stk sr (sr),y blk abs,b abs,x abs,y dir,b,r abs,b,r ( abs,x ) 10 98 76 5 2 30 op n op op op op op op op n op n op op op op op n n n n op n n op op n n n n op n n n n abs ipl v m x d i c z 41 n 4 0c 9 97 3 533 544 7 3 42 4 74 74 75 85 9 97 9f 3 5 3 5 processor status register 22 6 3 83 3 2 8 ? ? ? ? ?? ? ? ? ? ? ? ? ? ?? ? ? 1 ?? ? ? ? ? ?1 ? ? ? ?? ? ? ? ? ?? ? ? ? ?? ? ? ? ? ?? ? ? ? ?? specified flag becomes 1. ? ? ? ? ?? ? ? ? ?? ? ? ? ? ?? ? ? ? ?? ? ? ? ? ?? ? ? ? ?? ? ? ? ? ?? ? ? ? ?? ? ? ? ? ?? ? ? ? ?? ? ? ? ? ?? ? ? ? ?? ? ? ? n ?? ? ? ? z? ? ? ? n ?? ? ? ? z ? ? ? ? ? ?? ? ? ? ?? ? ? ? ? ?? ? ? ? ?? ? ? ? n ?? ? ? ? z ? ? ? ? n ?? ? ? ? z ? ? ? ? n ?? ? ? ? z ? ? ? ? n ?? ? ? ? z ? ? ? ? n ?? ? ? ? z? ? ? ? n ?? ? ? ? z ? ? ? ? n ?? ? ? ? z ? ? ? ? ? n ?? ? ? ? z ? ? ? n ?? ? ? ? z ? ? ? ? ? ?? ? ? ? ? ? ? ? n ?? ? ? ? z ? ? ? ? n ?? ? ? ? z ? ? ? ? n ?? ? ? ? z ? ? ? ? n ?? ? ? ? z? ? ? ? n ?? ? ? ? z 12 11 13 42 9d 42 99 5 9d 99 8f 9f 5 7 2 3 93 42 83 42 10 ? ? ? ? ? ? ?? ? ? ? ?? ##n#### # # ## # rel ##### # # 1 93 42 42 8f 8d 42 8d 8c 8e 10 87 42 87
appendix appendix 6. machine instructions 7721 group users manual 17C54 the number of cycles shown in the table is described in the case of the fastest mode for each instruction. the number of cycles shown in the table is calculated for dpr l =0. the number of cycles in the addressing mode concerning the dpr when dpr l 0 must be incremented by 1. the number of cycles shown in the table differs according to the bytes fetched into the instruction queue buffer, or according to whether the memory read/write address is odd or even. it also differs when the external region memory is accessed by byte=h. notes 1. the operation code at the upper row is used for accumulator a, and the operation at the lower row is used for accumulator b. 2. when setting flag m=0 to handle the data as 16-bit data in the immediate addressing mode, the number of bytes increments by 1. 3. the number of cycles increments by 2 when branching. 4. the operation code on the upper row is used for branching in the range of C128 to +127, and the operation code on the lower row is used for branching in the range of C32768 to +32767. 5. when handling 16-bit data with flag m=0, the byte in the table is incremented by 1. 6. the number of cycles corresponding to the register to be pushed are added. the number of cycles when no pushing is done is 12. i 1 indicates the number of registers among a, b, x, y, dpr, and ps to be saved, while i 2 indicates the number of registers among dt and pg to be saved. 7. the number of cycles corresponding to the register to be pulled are added. the number of cycles when no pulling is done is 14. i 1 indicates the number of registers among a, b, x, y, dt, and ps to be restored, while i 2 =1 when dpr is to be restored. 8. the number of cycles is the case when the number of bytes to be transferred is even. when the number of bytes to be transferred is odd, the number is calculated as; 7 + (i/2) 5 7 + 4 note that, (i/2) shows the integer part when i is divided by 2. 9. the number of cycles is the case when the number of bytes to be transferred is even. when the number of bytes to be transferred is odd, the number is calculated as; 9 + (i/2) 5 7 + 5 note that, (i/2) shows the integer part when i is divided by 2. 10. the number of cycles is the case in the 16-bit 8-bit operation. the number of cycles is incremented by 16 for 32-bit 16- bit operation. 11. the number of cycles is the case in the 8-bit 5 8-bit operation. the number of cycles is incremented by 8 for 16-bit 5 16- bit operation. 12. when setting flag x=0 to handle the data as 16-bit data in the immediate addressing mode, the number of bytes increments by 1. 13. when flag m is 0, the byte in the table is incremented by 1. b 3 a 3 x 3 y 3 dpr 4 dt 3 ps 3 a 2 b 2 x 2 y 2 dpr 2 dt 1 pg 1 ps 2 type of register number of cycles type of register number of cycles
appendix appendix 6. machine instructions 7721 group users manual 17C55 symbols in machine instructions table description symbol description symbol imp imm a dir dir, b dir, x dir, y (dir) (dir,x) (dir), y l (dir) l (dir),y abs abs, b abs, x abs, y abl abl, x (abs) l (abs) (abs, x) stk rel dir, b, rel abs, b, rel sr (sr), y blk c z i d x m v n ipl implied addressing mode immediate addressing mode accumulator addressing mode direct addressing mode direct bit addressing mode direct indexed x addressing mode direct indexed y addressing mode direct indirect addressing mode direct indexed x indirect addressing mode direct indirect indexed y addressing mode direct indirect long addressing mode direct indirect long indexed y addressing mode absolute addressing mode absolute bit addressing mode absolute indexed x addressing mode absolute indexed y addressing mode absolute long addressing mode absolute long indexed x addressing mode absolute indirect addressing mode absolute indirect long addressing mode absolute indexed x indirect addressing mode stack addressing mode relative addressing mode direct bit relative addressing mode absolute bit relative addressing mode stack pointer relative addressing mode stack pointer relative indirect indexed y addressing mode block transfer addressing mode carry flag zero flag interrupt disable flag decimal operation mode flag index register length selection flag data length selection flag overflow flag negative flag processor interrupt priority level addition subtraction multiplication division logical and logical or C ? a cc a cch a ccl a a h a l b b h b l x x h x l y y h y l s pc pc h pc l pg dt dpr dpr h dpr l ps ps h ps l ps b m(s) mb ad g ad h ad l op n # i i 1 , i 2 exclusive or negation movement to the arrow direction accumulator accumulators upper 8 bits accumulators lower 8 bits accumulator a accumulator as upper 8 bits accumulator as lower 8 bits accumulator b accumulator bs upper 8 bits accumulator bs lower 8 bits index register x index register xs upper 8 bits index register xs lower 8 bits index register y index register ys upper 8 bits index register ys lower 8 bits stack pointer program counter program counters upper 8 bits program counters lower 8 bits program bank register data bank register direct page register direct page registers upper 8 bits direct page registers lower 8 bits processor status register processor status registers upper 8 bits processor status registers lower 8 bits processor status registers b-th bit contents of memory at address indicated by stack pointer b-th memory location value of 24-bit addresss upper 8-bit (a 23 Ca 16 ) value of 24-bit addresss middle 8-bit (a 15 Ca 8 ) value of 24-bit addresss lower 8-bit (a 7 Ca 0 ) operation code number of cycle number of byte number of transfer byte or rotation number of registers pushed or pulled + C ] /
appendix appendix 7. hexadecimal instruction code table 7721 group users manual 17C56 appendix 7. hexadecimal instruction code table instruction code table-1 d 3 d 0 d 7 d 4 hexadecimal notation 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1101 1100 1110 1111 0 1 2 3 4 5 6 7 8 9 a b c d e f 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0123456789 bcdef brk bpl bmi rti bvc rts bvs bcc bcs bne beq jsr abs bra rel ldy imm cpx imm cpy imm ora a,(dir,x) ora a,(dir),y and a,(dir,x) eor a,(dir,x) eor a,(dir),y adc a,(dir,x) adc a,(dir),y sta a,(dir,x) lda a,(dir,x) and a,(dir),y sta a,(dir),y lda a,(dir),y cmp a,(dir),y cmp a,(dir,x) sbc a,(dir,x) sbc a,(dir),y ora a,(dir) jsr abl and a,(dir) note 1 eor a,(dir) per adc a,(dir) sta a,(dir) lda a,(dir) cmp a,(dir) sbc a,(dir) bra rel ldx imm clp imm sep imm ora a,sr a ora a,dir seb dir,b asl dir ora a,l(dir) ora a,imm ora a,abs php phd asl a seb abs,b asl abs ora a,(sr),y ora a,l(dir),y clb dir,b ora a,dir,x asl dir,x clc tas ora a,abs,y dec a clb abs,b ora a,abs,x asl abs,x and a,sr bbs dir,b,r and a,dir rol dir and a,l(dir) plp pld and a,imm rol a bbs abs,b,r and a,abs rol abs and a,(sr),y bbc dir,b,r and a,dir,x rol dir,x and a,l(dir),y sec and a,abs,y inc a tsa bbc abs,b,r and a,abs,x rol abs,x eor a,sr mvp eor eor eor eor a,dir lsr dir a,l(dir) pha a,imm lsr a phg jmp abs a,abs lsr abs eor a,(sr),y a,(sr),y a,(sr),y a,(sr),y a,(sr),y a,(sr),y mvn eor eor eor eor lsr lsr cli tad phy jmp a,dir,x a,dir,x a,dir,x a,dir,x a,dir,x a,dir,x dir,x dir,x dir,y dir,y dir,x dir,x a,l(dir),y a,l(dir),y a,l(dir),y a,l(dir),y a,l(dir),y a,l(dir),y a,abs,y a,abs,y a,abs,y a,abs,y a,abs,y a,abs,y abl (abs) abs abs abs abs a,abs,x a,abs,x a,abs,x a,abs,x a,abs,x a,abs,x abs,x abs,x abs,x abs,y abs,x abs,x adc adc adc adc adc ror ror ror jmp rtl pla ldm a,sr a,sr a,sr a,sr a,sr dir dir dir dir dir a,dir a,dir a,dir a,dir a,dir dir dir dir dir dir a,l(dir) a,l(dir) a,l(dir) a,l(dir) a,l(dir) a,imm a,imm a,imm a,imm a a,abs abs a,abs abs a,abs abs a,abs abs a,abs abs adc adc adc adc adc jmp ror ror ldm dir,x dir,x dir,x sei tda ply (abs,x) sta sty sta sta sta stx sty stx dey txa pht note 2 sta sta sta sta sta sty stx txs txy tya ldm ldm lda lda ldy lda lda lda ldx ldx ldy plt tax tay lda lda ldy lda ldx lda tyx tsx clv abs,x lda ldx ldy cmp cmp cmp cmp cmp cpy dec cpy dec cmp dec iny dex wit cmp cmp cmp dec clm cmp phx stp jmp l(abs) pei sbc sbc sbc sbc sbc ora a,abl ora a,abl,x and a,abl and a,abl,x eor a,abl eor a,abl,x a,abl,x a,abl,x a,abl,x a,abl,x a,abl,x adc a,abl a,abl a,abl a,abl a,abl adc sta sta lda lda cmp cmp sbc sbc sbc sbc cpx cpx inc inc inx inc sbc pea sbc sbc inc sem plx nop psh pul jsr abs (abs,x) notes 1: 42 16 specifies the contents of the instruction code table-2. about the second word? codes, refer to the instruction code table-2. 2: 89 16 specifies the contents of the instruction code table-3. about the second word? codes, refer to the instruction code table-2.
appendix appendix 7. hexadecimal instruction code table 7721 group users manual 17C57 instruction code table-2 (the first words code of each instruction is 42 16 ) d 3 d 0 d 7 d 4 hexadecimal notation 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1101 1100 1110 1111 0 1 2 3 4 5 6 7 8 9 a b c d e f 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0123456789 bcdef ora b,(dir,x) ora b,(dir),y and b,(dir,x) eor b,(dir,x) eor b,(dir),y adc b,(dir,x) adc b,(dir),y sta b,(dir,x) lda b,(dir,x) and b,(dir),y sta b,(dir),y lda b,(dir),y cmp b,(dir),y cmp b,(dir,x) sbc b,(dir,x) sbc b,(dir),y ora b,(dir) and b,(dir) eor b,(dir) adc b,(dir) sta b,(dir) lda b,(dir) cmp b,(dir) sbc b,(dir) ora b,sr a ora b,dir ora b,l(dir) ora b,imm ora b,abs asl b ora b,(sr),y ora b,l(dir),y ora b,dir,x tbs ora b,abs,y dec b ora b,abs,x and b,sr and b,dir and b,l(dir) and b,imm rol b and b,abs and b,(sr),y and b,dir,x and b,l(dir),y and b,abs,y inc b tsb and b,abs,x eor b,sr eor eor eor eor b,dir b,l(dir) phb b,imm lsr b b,abs eor b,(sr),y b,(sr),y b,(sr),y b,(sr),y b,(sr),y b,(sr),y eor eor eor eor tbd b,dir,x b,dir,x b,dir,x b,dir,x b,dir,x b,dir,x b,l(dir),y b,l(dir),y b,l(dir),y b,l(dir),y b,l(dir),y b,l(dir),y b,abs,y b,abs,y b,abs,y b,abs,y b,abs,y b,abs,y b,abs,x b,abs,x b,abs,x b,abs,x b,abs,x b,abs,x adc adc adc adc adc ror plb b,sr b,sr b,sr b,sr b,sr b,dir b,dir b,dir b,dir b,dir b,l(dir) b,l(dir) b,l(dir) b,l(dir) b,l(dir) b,imm b,imm b,imm b,imm b b,abs b,abs b,abs b,abs b,abs adc adc adc adc adc tdb sta sta sta sta txb sta sta sta sta sta tyb lda lda lda lda lda tbx tby lda lda lda lda lda cmp cmp cmp cmp cmp cmp cmp cmp cmp cmp sbc sbc sbc sbc sbc ora b,abl ora b,abl,x and b,abl and b,abl,x eor b,abl eor b,abl,x b,abl,x b,abl,x b,abl,x b,abl,x b,abl,x adc b,abl b,abl b,abl b,abl b,abl adc sta sta lda lda cmp cmp sbc sbc sbc sbc sbc sbc sbc
appendix appendix 7. hexadecimal instruction code table 7721 group users manual 17C58 instruction code table-3 (the first words code of each instruction is 89 16 ) d 3 d 0 d 7 d 4 hexadecimal notation 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1101 1100 1110 1111 0 1 2 3 4 5 6 7 8 9 a b c d e f 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0123456789 bcdef mpy (dir,x) mpy (dir),y div (dir,x) div (dir),y mpy (dir) div (dir) mpy sr a mpy dir mpy l(dir) mpy imm mpy abs mpy (sr),y mpy l(dir),y mpy dir,x mpy abs,y mpy abs,x div sr div dir div l(dir) div imm div abs div (sr),y div dir,x div l(dir),y div abs,y div abs,x rla imm imm ldt mpy abl mpy abl,x div abl div abl,x xab
7721 group users manual 17C59 appendix appendix 8. countermeasure against noise appendix 8. countermeasure against noise general countermeasure examples against noise are described below. although the effect of these countermeasure depends on each system, refer to the following when an noise-related problem occurs. 1. short wiring length the wiring on a printed circuit board may function as an antenna which feeds noise into the microcomputer. the shorter the total wiring length (by mm unit), the less possibility of noise insertion into the microcomputer. (1) ______ wiring for reset pin ______ make the length of wiring connected to the reset pin as short as possible. ______ in particular, connect a capacitor between the reset pin and the vss pin with the shortest possible wiring (within 20 mm). reason: ______ if noise is input to the reset pin, the microcomputer restarts operation before the internal state of the microcomputer is completely initialized. this may cause a program runaway. noise x in x out vss x in x out vss m37721 m37721 n o t a c c e p t a b l e a c c e p t a b l e fig. 4 wiring for clock input/output pins reset circuit vss reset vss m37721 a c c e p t a b l e reset reset circuit noise vss vss m37721 n o t a c c e p t a b l e ______ fig. 3 wiring for reset pin (2) wiring for clock input/output pins l make the length of wiring connected to the clock input/output pins as short as possible. l make the length of wiring between the grounding lead of the capacitor, which is connected to the oscillator, and the vss pin of the microcomputer, as short as possible (within 20 mm). l separate the vss pattern for oscillation from all other vss patterns. (refer to figure 11. ) reason: the microcomputers operation synchronizes with a clock generated by the oscillation circuit. if noise enters clock i/o pins, clock waveforms may be deformed. this may cause a malfunction or a program runaway. also, if the noise causes a potential difference between the vss level of the microcomputer and the vss level of an oscillator, the correct clock will not be input in the microcomputer.
7721 group users manual 17C60 appendix appendix 8. countermeasure against noise (3) wiring for cnvss pin connect cnvss pin to the vss pin with the shortest possible wiring. reason: the processor mode of the microcomputer is influenced by a potential at the cnvss pin when the cnvss pin and the vcc or vss pin are connected. if the noise causes a potential difference between the cnvss pin and the vss or vcc pin, the processor mode may become unstable. this may cause a microcomputer malfunction or a program runaway. noise cnvss vss m37721 cnvss vss m37721 a c c e p t a b l e n o t a c c e p t a b l e when connecti ng th e c nvss and vcc pins, connect them in the shortest possible distance, also. fig. 5 wiring for cnvss pin 2. connection of bypass capacitor between vss and vcc lines connect an approximate 0.1 f bypass capacitor as follows: l connect a bypass capacitor between the vss and vcc pins, at equal lengths. l the wiring connecting the bypass capacitor between the vss and vcc pins should be as short as possible. l use thicker wiring for the vss and vcc lines than that for the other signal lines. fig. 6 bypass capacitor between vss and vcc lines bypass capacitor vcc vss m37721 wiring pattern wiring pattern
7721 group users manual 17C61 appendix appendix 8. countermeasure against noise 3. wiring for analog input pins, analog power source pins, etc. (1) processing for analog input pins l connect a resistor to the analog signal line, which is connected to an analog input pin, in series. additionally, connect the resistor to the microcomputer as close as possible. l connect a capacitor between the analog input pin and the avss pin, as close to the avss pin as possible. reason: a signal which is input to the analog input pin is usually an output signal from a sensor. the sensor, which detects changes in status, is installed far from the microcomputers printed circuit board. therefore, this long wiring between them becomes an antenna which picks up noise and feeds it into the microcomputers analog input pin. if a capacitor between an analog input pin and the avss pin is grounded far away from the avss pin, noise on the gnd line may enter the microcomputer through the capacitor. fig. 7 countermeasure example against noise for analog input pin using thermistor an i avss thermistor noise m3772 1 ri ci reference values ri : approximate 100 w to 1000 w ci : approximate 100 pf to 1000 pf notes 1 : design an external circuit for the ani pin so that charge/discharge is available within 1 cycle of ad . 2 : this resistor and thermistor are used to divide resistance. (note 2) a c c e p t a b l e a c c e p t a b l e n o t a c c e p t a b l e
7721 group users manual 17C62 appendix appendix 8. countermeasure against noise (2) processing for analog power source pins, etc. l use independent power sources for the vcc, avcc and v ref pins. l insert capacitors between the avcc and avss pins, and between the v ref and avss pins. reasons: prevents the a-d converter from noise on the vcc line. fig. 8 processing for analog power source pins, etc. avcc avss m3772 1 reference values c1 0.47 f c2 0.47 f note : connect capacitors using the thickest, shortest wiring possible. v ref an i c1 c2 (sensor, etc.)
7721 group users manual 17C63 appendix appendix 8. countermeasure against noise 4. oscillator protection the oscillator, which generates the basic clock for the microcomputer operations, must be protected from the affect of other signals. (1) distance oscillator from signal lines with large current flows install the microcomputer, especially the oscillator, as far as possible from signal lines which handle currents larger than the microcomputer current value tolerance. reason: the microcomputer is used in systems which contain signal lines for controlling motors, leds, thermal heads, etc. noise occurs due to mutual inductance when a large current flows through the signal lines. (2) distance oscillator from signal lines with frequent potential level changes l install an oscillator and its wiring pattern away from signal lines where potential levels change frequently. l do not cross these signal lines over the clock-related or noise-sensitive signal lines. reason: signal lines with frequently changing potential levels may affect other signal lines at a rising or falling edge. in particular, if the lines cross over a clock-related signal line, clock waveforms may be deformed, which causes a microcomputer malfunction or a program runaway. x in x out vss m m37721 mutual inductance large current x in x out vss ] do not cross. m377 1 ] i/o pin for signal with frequently changing potential levels fig. 10 wiring for signal lines where potential levels frequently change (3) oscillator protection using vss pattern print a vss pattern on the bottom (soldering side) of a double-sided printed circuit board, under the oscillator mount position. connect the vss pattern to the vss pin of the microcomputer with the shortest possible wiring, separating it from other vss patterns. x in x out vss an example of vss pattern on the underside of an oscillator. mounted pattern example of oscillator unit. separate vss lines for oscillation and supply. m37721 fig. 11 vss pattern underneath mounted oscillator fig. 9 wiring for signal lines where large current flows 2
7721 group users manual 17C64 appendix appendix 8. countermeasure against noise 5. setup for i/o ports setup i/o ports by hardware and software as follows: l connect a resistor of 100 w or more to an i/o port in series. l read the data of an input port several times to confirm that input levels are equal. l since the output data may reverse because of noise, rewrite data to the output ports pi register periodically. l rewrite data to port pi direction registers periodically. 6. reinforcement of the power source line l for the vss and vcc lines, use thicker wiring than that of other signal lines. l when using a multilayer printed circuit board, the vss and vcc patterns must each be one of the middle layers. l the following is necessary for double-sided printed circuit boards: ?on one side, the microcomputer is installed at the center, and the vss line is looped or meshed around it. the vacant area is filled with the vss line. ?on the opposite side, the vcc line is wired the same as the vss line. ?the power source lines of external devices which are connected by bus to the microcomputer must be connected to the microcomputer's power source lines with the shortest possible wiring. reasons: with external devices connected to the microcomputer, the levels of many of the signal lines (total external address buses: 24 bits) may change simultaneously, causing noise on the power source line. noise direction register port latch data bus port fig. 12 setup for i/o ports
appendix 7721 group users manual 17C65 appendix 9. 7721 group q & a appendix 9. 7721 group q & a information which may be helpful in fully utilizing the 7721 group is provided in q & a format. in q & a, as a rule, one question and its answer are summarized within one page. the upper box on each page is a question, and a box below the question is its answer. (if a question or an answer extends to two or more pages, there is a page number at the lower right corner.) at the upper right corner of each page, the main function related to the contents of description in that page is listed.
appendix appendix 9. 7721 group q & a 7721 group users manual 17C66 sfr q is there any sfr to which a certain instruction cannot be used for writing ? (1) use the ldm or sta instruction to write to the registers or the bits listed below. do not use read-modify-write instructions (i.e., clb, seb, asl, asr, dec, inc, lsr, rol, and ror ). pulse output data register 0, 1 (addresses 1a 16 , 1c 16 ) uart0, 1 baud rate register (addresses 31 16, 39 16 ) uart0, 1 transmit buffer register (addresses 33 16 , 32 16 , 3b 16 , 3a 16 ) timer a2Ca4 two-phase pulse signal processing select bit (bits 5C7 at address 44 16 ) timer a2Ca4 register (addresses 4a 16 C4f 16 ; one-shot pulse mode or pulse width modulation mode) refresh timer (address 66 16 ) (2) use the seb or clb instruction to write to the following register. dmac control register h (address 69 16 ; when any of bits 4 to 7 = 1) a
appendix 7721 group users manual 17C67 appendix 9. 7721 group q & a reset, stp instruction, wit instruction q is it possible to distinguish power-on reset from hardware reset for terminating the stop or wait mode ? a the contents of the internal ram is undefined after power-on reset. on the other hand, the contents of the internal ram are retained when performing hardware reset in the stop or wait mode with vcc 3 2 v. accordingly, write a certain data to the internal ram before executing stp or wit instruction, and judge by checking the contents of the internal ram after hardware reset.
appendix appendix 9. 7721 group q & a 7721 group users manual 17C68 interrupt q if an interrupt request (b) occurs while executing an interrupt routine (a), is it true that the main routine is not executed at all from when the execution of the interrupt routine (a) is completed until the execution of the intack sequence for the next interrupt (b) starts? (2) if the next interrupt request (b) occurs immediately after sampling pulse is generated, the microcomputer executes one instruction of the main routine before executing the intack sequence for (b). it is because that the interrupt request is sampled by the next sampling pulse . sampling for interrupt requests is performed by sampling pulses generated synchronously with the cpus op-code fetch cycles. (1) if the next interrupt request (b) occurs before sampling pulse for the rti instruction is gener- ated, the microcomputer executes the intack sequence for (b) without executing the main rou- tine (not even one instruction). it is because that sampling is completed while executing the rti instruction. a conditions: l i is cleared to 0 by executing the rti instruction. l iinterrupt priority level of interrupt (b) is higher than ipl of main routine. l interrupt priority detection time is 2 cycles of f. interrupt routine (a) main routine intack sequence for interrupt (b) sequence of execution rti instruction ? intack sequence for interrupt (b) interrupt request (b) interrupt routine (a) sampling pulse rti instruction main routine interrupt request (b) sampling pulse intack sequence for interrupt (b) one instruction executed interrupt routine (a) rti instruction
appendix 7721 group users manual 17C69 appendix 9. 7721 group q & a interrupt suppose that there is a routine which should not accept one certain interrupt request. (the other interrupt request are acceptable). although when the interrupt priority level select bits for the above interrupt are set to 000 2 , in other words, when this interrupt is set to be disabled, this interrupt request is actually accepted immediately after change of the priority level. why did this occur and what should i do about it? as for the change of the interrupt priority level, when the following are met, the microcomputer may pretend to accept an interrupt request immediately after this interrupt is set to be disabled: ?the next instruction (in the above example, it is the lda instruction) is already stored into a instruc- tion queue buffer for the biu. ?conditions for accepting the instruction which should not be accepted are satisfied immediately before the next instruction in the instruction queue buffer is executed. when writing to a memory or an i/o, the cpu passes the address and data to the biu. then, the cpu executes the next instruction in the instruction queue buffer while the biu is writing data into the actual address. detection of interrupt priority level is performed at the beginning of each instruc- tion. in the above case, the cpu executes the next instruction before the biu completes the change of the interrupt priority level. therefore, when the interrupt priority level is detected synchronously with the execution of the next instruction, the interrupt priority level before the change is detected and its interrupt request is accepted. q a (1/2) interrupt request is accepted in this interval : ldm #00h, xxxic ; writes 000 2 to interrupt priority level select bits. ; clears interrupt request bit to 0. lda a,data ; instruction at the beginning of the routine which should not accept one certain interrupt request. :; previous instruction executed (instruction prefetched) cpu operation biu operation interrupt priority detection time sequence of execution interrupt priority level select bits set change of interrupt priority levels completed interrupt request accepted interrupt request generated ldm instruction executed lda instruction executed
appendix appendix 9. 7721 group q & a 7721 group users manual 17C70 interrupt (2/2) a to prevent this problem, after change of the interrupt priority level is completed, use software to execute the routine that should not accept a certain interrupt request. the following shows a sample program. [ sample program ] after an instruction which writes 000 2 to the interrupt priority level select bits, fill the instruction queue buffer with the nop instruction to make the next instruction not to be executed before the writing is completed. : ldm #00h, xxxic ; sets the interrupt priority level select bits to 000 2 . nop ; nop ; nop ; lda a,data ; instruction at the beginning of the routine that should not accept a certain : interrupt request
appendix 7721 group users manual 17C71 appendix 9. 7721 group q & a interrupt q (1) in both the edge sense and level sense, external interrupt requests occur when the input ____ signal to the int i pin changes its level. this is independent of clock f 1 . in the edge sense, the interrupt request bit is set to 1 at this time. (2) there are two methods: one uses external interrupts level sense, and the other uses the timers event counter mode. method using external interrupts level sense as for hardware, input a logical sum of multiple interrupt signals (e.g., a, b, and c) to the ____ int i pin, and input each signal to each corresponding port. ___ as for software, check the ports input levels in the int i interrupt routine in order to detect which signal (a, b, or c) was input. a (1) ____ which timing of clock f 1 is the external interrupts (input signals to the int i pin) detected? (2) ____ how can four or more external interrupt input pins (int i ) be used? method using timers event counter mode as for hardware, input interrupt signals to the tai in pins or tbi in pins. as for software, set the timers operating mode to the event counter mode. then, set a value 0000 16 into the timer register and select the valid edge. the timers interrupt request occurs when an interrupt signal (selected valid edge) is input. a m37721 port port port int i b c
appendix appendix 9. 7721 group q & a 7721 group users manual 17C72 what are there the stack bank select bit (bit 7 at address 5e 16 ) for? q stack, dram a it is supposed that dram is used as the stack area. when connecting dram, the stack pointer addressing mode or stack operation instruction etc. can be used. it is because all of 64 kbytes can be used as the stack area when bank ff 16 which is assigned to dram is set as the stack area. (the internal ram also functions as the temporary area or the register file which is accessed frequently because the internal ram can be accessed with no wait. accordingly, it is expected that the capacity will lack to be used as the stack area. as for the m37721, dram area can be set as the stack area because cheap dram can be connected.) use bank 0 which is assigned to the internal ram area as the stack area when dram is not connected or the internal ram is sufficient to be used as the stack area.
appendix 7721 group users manual 17C73 appendix 9. 7721 group q & a are there methods to refresh dram in the wait mode? q dram, wit instruction
appendix appendix 9. 7721 group q & a 7721 group users manual 17C74 a in the wait mode, dram refresh function does not operate, but the watchdog timer, timer a, and timer b operate. accordingly, dram can be refreshed by using these timers and ports. (1) method using watchdog timer return from the wait mode by the watchdog timer interrupt. control ports p10 4 , p10 5 by ____ ____ software and perform the cas-before-ras- refresh. example 1: a case in 1024 refresh cycles, every 16.4 ms, f(x in ) = 16 mhz, watchdog timer count source = f 32 ?dram refresh is performed 256 times. this refresh is performed by every watchdog timer interrupt. (see flow chart .) interval of watchdog timer interrupt f(x in ) 25 mhz 16 mhz f 32 selected 2.621 ms 4.096 ms f 512 selected 41.943 ms 65.536 ms (1/2) dram validity bit (bit 7 at address 64 16 ) bits 4, 5 of port p10 register (address 16 16 ) ? 1 wit instruction wait mode completed ? n y wait mode dramc stopped watchdog timer count source: f 32 selected ports p10 4 , p10 5 : h level output note: by using 1 bit of ram, judge whether this interrupt is for return from the wait mode or for refresh. 256 times ? n y rti return to main routine ? 1 bits 4, 5 of port p10 direction register (address 18 16 ) ? 1 ? 0 watchdog timer frequency select bit (bit 0 at address 61 16 ) main routine flow chart watchdog timer interrupt routine ? 0 bit 4 of port p10 register (address 16 16 ) ? 0 bit 5 of port p10 register (address 16 16 ) ? 1 bit 4 of port p10 register (address 16 16 ) ? 1 bit 5 of port p10 register (address 16 16 ) port p10 5 (ras) h level output port p10 4 (cas): h level output port p10 5 (ras): l level output port p10 4 (cas): l level output port p10 5 (ras): h level output
appendix 7721 group users manual 17C75 appendix 9. 7721 group q & a dram, wit instruction a (2) method using timer a or timer b return from the wait mode by a timer a ( or timer b) interrupt every definite time. control ____ ____ ports p10 4 , p10 5 by software and perform the cas-before-ras-refresh. example 2: a case in 512 refresh cycles, every 64 ms, f(x in ) = 25 mhz, timer a0 used ?dram refresh is performed 512 times by timer a0 interrupts. this interrupt occurs every 64 ms. (see flow chart .) (2/2) n y n y flow chart main routine ? 1 bits 4, 5 of port p10 direction register (address 18 16 ) ? 1 bits 4, 5 of port p10 register (address 16 16 ) dram validity bit (bit 7 at address 64 16 ) ? 0 timer a0 mode register (address 56 16 ) ? 11000000 2 timer a0 register (addresses 47 16 , 46 16 ) ? 3124 timer a0 interrupt control register (address 75 16 ) ? xxxx0001 2 timer a0 count start bit (bit 0 at address 40 16 ) ? 1 interrupt enable flag i ? 0 wit instruction wait mode completed ? wait mode timer a0 interrupt routine ? 0 bit 4 of port p10 register (address 16 16 ) ? 0 bit 5 of port p10 register (address 16 16 ) ? 1 bit 4 of port p10 register (address 16 16 ) ? 1 bit 5 of port p10 register (address 16 16 ) 512 times ? rti return to main routine port p10 5 (ras): h level output port p10 4 (cas): h level output port p10 5 (ras): l level output port p10 4 (cas): l level output ports p10 4 , p10 5 : h level output dramc stopped f 512 counted timer value set: one cycle = 64 ms interrupt priority level set: level 1 or more (interrupt enabled) timer a0 count started interrupt enabled note: by using 1 bit of ram, judge whether this interrupt is for return from the wait mode or for refresh.
appendix appendix 9. 7721 group q & a 7721 group users manual 17C76 dram how is the program execution time affected when using dram ? q a (1/2) rate occupied by dram refresh cycle during program execution time rate occupied by dram refresh cycle f(x in ) = 25 mhz 2.6 % 0.3 % f(x in ) = 16 mhz 4.2 % 0.5 % refresh interval 15.625 s (case of 512 refresh cycles, every 8 ms) 125 s (case of 512 refresh cycles, every 64 ms) when the m37721 uses dram, the execution time is affected as follows: ?cpu stops and dram refresh cycle is inserted. ?1-bus cycle becomes 3 f when accessing dram. (1) refresh method of the m37721s dramc is the dispersion refresh and 5 cycles of f are necessary for one refresh. the rate occupied by the dram refresh cycle during the program execution time is described below. (2) the comparison results of two sample programs execution times are listed below; one is for the case where sram is used and the other is for the case where dram is used. use conditions : execution program sample program b (see (2/2)) f(x in ) 16 mhz external data bus width 16 bits refresh interval 13 s memory used as work area sram sram dram (bank ff 16 ) dram (bank ff 16 ) software wait valid area nothing rom and ram nothing rom speed comparison 1.00 1.47 1.15 1.53 execution time 3.4 ms 5.0 ms 3.9 ms 5.2 ms
appendix 7721 group users manual 17C77 appendix 9. 7721 group q & a dram a (2/2) l sample program b sep x clm .data 16 .index 8 ldy #69 loop0: ldx #69 loop1: asl sour, x sem .data 8 rol sour+2, x rol b clm .data 16 ror a dex dex dex bne loop1 sta a, dest, y sem .data 8 sta b, dest+2, y clm .data 16 dey dey dey bne loop0 ] sour, dest : work areas
appendix appendix 9. 7721 group q & a 7721 group users manual 17C78 watchdog timer when detecting the software runaway by the watchdog timer, if the same value as the contents of the reset vector address is set to the watchdog timer interrupt vector address, not performing software reset, how does it result in? when branching to the reset branch address within the watchdog timer interrupt routine, how does it result in? a the cpu registers and the sfr are not initialized in the above-mentioned way. accordingly, the user must initialize all of them by software. note that the processor interrupt priority level (ipl) retains 7 of the watchdog timer interrupt priority level and is not initialized. consequently, all interrupt requests cannot be accepted. when rewriting the ipl by software, save once the 16-bit immediate value to the stack area and then restore that 16-bit immediate value to all bits of the processor status register (ps). when a software runaway occurs, we recommend to use software reset in order to initialize the microcomputer. q
appendix 7721 group users manual 17C79 appendix 10. differences between 7721 group and 7720 group appendix 10. differences between 7721 group and 7720 group table 2 differences between m37721s2bfp and m37720s1afp m37720s1afp 512 bytes 16 mhz (maximum) 250 ns 4 bits 5 2 channels undefined exists ( ldm , sta instructions cannot be used.) one of the following: ?when setting the receive enable bit to 0 ?when setting the serial i/o mode select bits to 000 2 ?when reading the receive buffer register when all of the following are satisfied: ?receive enable bit = 1 ?reception is stopped. 8 mbytes/sec real-time output m37721s2bfp 1024 bytes (note) 25 mhz (maximum) 160 ns 4 bits 5 2 channels, or 6 bits 5 1channel and 2 bits 5 1channe l retains the value before using real-time output nothing ( ldm , sta instructions can be used.) one of the following: ?when setting the receive enable bit to 0 ?when setting the serial i/o mode select bits to 000 2 when all of the following are satisfied: ?receive enable bit = 1 ?reception is stopped. ?dummy data is present in the transmit buffer register 12.5 mbytes/sec item internal ram size external clock input frequency instruction execution time (minimum) bit configuration of realCtime output channel port latch state after using real-time output limitation for instruction used when writing to interrupt control register timing when overrun error flag becomes 0 ____ conditions for outputting l of rts signal in clock synchronous serial i/o mode dma shortest transfer rate (at 1-bus cycle transfer) serial i/o note: 512 bytes can be selected by software. for the m37721s1bfp, its internal ram size is 512 bytes.
7721 group users manual 17C80 appendix appendix 11. electrical characteristics appendix 11. electrical characteristics the electrical characteristics of the m37721s2bfp are described below. for the latest data, inquire of addresses described last ( + contact addresses for further information) . absolute maximum ratings conditions ta = 25 c ratings C0.3 to 7 C0.3 to 7 C0.3 to 12 C0.3 to v cc +0.3 C0.3 to v cc +0.3 300 C20 to 85 C40 to 150 unit v v v v v mw c c ______ reset , cnv ss , byte a 8 /d 8 Ca 15 /d 15 , a 16 /d 0 Ca 23 /d 7 , p4 3 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 , p8 0 Cp8 7 , p9 0 Cp9 7 , ____ _____ p10 0 Cp10 7 , rdy, hold, x in , v ref a 0 /ma 0 Ca 7 /ma 7 , a 8 /d 8 Ca 15 /d 15 , a 16 /d 0 Ca 23 /d 7 , p4 3 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 , p8 0 Cp8 7 , p9 0 Cp9 7 , p10 0 Cp10 7 , ________ __ f 1 , reset out , x out , e, st0, ____ ____ __ st1, ale, ble, bhe, r/w parameter power source voltage analog power source voltage input voltage input voltage output voltage power dissipation operating temperature storage temperature symbol v cc av cc v i v i v o p d t opr t stg
7721 group users manual 17C81 appendix 11. electrical characteristics appendix recommended operating conditions (v cc = 5 v 10 %, ta = C20 to 85 c, unless otherwise noted) v v v v v v v v ma ma ma ma mhz vcc avcc vss avss v ih v ih v il v il i oh (peak) i oh (avg) i ol (peak) i ol (avg) f(x in ) unit limits parameter symbol min. max. typ. 5.5 vcc vcc 0.2 vcc 0.16 vcc C10 C5 10 5 25 5.0 vcc 0 0 4.5 0.8 vcc 0.5 vcc 0 0 power source voltage analog power source voltage power source voltage analog power source voltage high-level input voltage high-level input voltage low-level input voltage low-level input voltage high-level peak output current high-level average output current low-level peak output current low-level average output current external clock input frequency p4 3 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 , ____ p8 0 Cp8 7 , p9 0 Cp9 7 , p10 0 Cp10 7 , rdy, _____ ______ hold, byte, cnvss, reset, x in , v ref a 8 /d 8 Ca 15 /d 15 , a 16 /d 0 Ca 23 /d 7 p4 3 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 , ____ p8 0 Cp8 7 , p9 0 Cp9 7 , p10 0 Cp10 7 , rdy, _____ ______ hold, byte, cnvss, reset, x in , v ref a 8 /d 8 Ca 15 /d 15 , a 16 /d 0 Ca 23 /d 7 a 0 /ma 0 Ca 7 /ma 7 , a 8 /d 8 Ca 15 /d 15 , a 16 /d 0 Ca 23 /d 7 , p4 3 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 , p8 0 Cp8 7 , ________ p9 0 Cp9 7 , p10 0 Cp10 7 , f 1 , reset out , ____ ____ __ st0, st1, ale, ble, bhe, r/w a 0 /ma 0 Ca 7 /ma 7 , a 8 /d 8 Ca 15 /d 15 , a 16 /d 0 Ca 23 /d 7 , p4 3 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 , p8 0 Cp8 7 , _________ p9 0 Cp9 7 , p10 0 Cp10 7 , f 1 , reset out , ____ ____ __ st0, st1, ale, ble, bhe, r/w a 0 /ma 0 Ca 7 /ma 7 , a 8 /d 8 Ca 15 /d 15 , a 16 /d 0 Ca 23 /d 7 , p4 3 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 , p8 0 Cp8 7 , _________ p9 0 Cp9 7 , p10 0 Cp10 7 , f 1 , reset out , ____ ____ __ st0, st1, ale, ble, bhe, r/w a 0 /ma 0 Ca 7 /ma 7 , a 8 /d 8 Ca 15 /d 15 , a 16 /d 0 Ca 23 /d 7 , p4 3 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 , p8 0 Cp8 7 , _________ p9 0 Cp9 7 , p10 0 Cp10 7 , f 1 , reset out , ____ ____ __ st0, st1, ale, ble, bhe, r/w notes 1: average output current is the average value of a 100 ms interval. ____ 2: the sum of i ol(peak) for p8, p9, a 0 /ma 0 Ca 7 /ma 7 , a 8 /d 8 Ca 15 /d 15 , a 16 /d 0 Ca 23 /d 7 , st0, st1, ale, ble, ____ __ bhe, and r/w must be 80 ma or less; the sum of i oh(peak) for p8, p9, a 0 /ma 0 Ca 7 /ma 7 , a 8 /d 8 C ____ ____ __ a 15 /d 15 , a 16 /d 0 Ca 23 /d 7 , st0, st1, ale, ble, bhe, and r/w must be 80 ma or less; the sum of i ol(peak) for p4, p5, p6, p7, p10, and f 1 must be 80 ma or less; the sum of i oh(peak) for p4, p5, p6, p7, p10, and f 1 must be 80 ma or less.
7721 group users manual 17C82 appendix appendix 11. electrical characteristics high-level output voltage high-level output voltage high-level output voltage high-level output voltage low-level output voltage low-level output voltage low-level output voltage low-level output voltage hysteresis hysteresis hysteresis high-level input current low-level input current ram hold voltage power source current electrical characteristics (v cc = 5 v, v ss = 0 v, ta = C20 to 85 c, f(x in ) = 25 mhz, unless otherwise noted) symbol parameter test conditions unit 2 0.45 1.9 0.43 1.6 0.4 1 0.5 0.3 5 C5 54 1 20 limits min. typ. 27 max. v oh v oh v oh v oh v ol v ol v ol v ol v t+ Cv tC v t+ Cv tC v t+ Cv tC i ih i il v ram icc a 0 /ma 0 Ca 7 /ma 7 , a 8 /d 8 Ca 15 /d 15 , a 16 /d 0 Ca 23 /d 7 , p4 3 C p4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 , _________ p8 0 Cp8 7 , p9 0 Cp9 7 , p10 0 Cp10 7 , f 1 , reset out , st0, ____ ____ __ st1, ale, ble, bhe, r/w a 0 /ma 0 Ca 7 /ma 7 , a 8 /d 8 Ca 15 /d 15 , a 16 /d 0 Ca 23 /d 7 , ma 8 , ____ ____ ____ ____ __ ma 9 , ras, cas, f 1 , st0, st1, ble, bhe, r/w ale __ e a 0 /ma 0 Ca 7 /ma 7 , a 8 /d 8 Ca 15 /d 15 , a 16 /d 0 Ca 23 /d 7 , p4 3 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 , p8 0 Cp8 7 , p9 0 Cp9 7 , p10 0 Cp10 7 , f 1 , ________ ____ ____ __ reset out , st0, st1, ale, ble, bhe, r/w a 0 /ma 0 Ca 7 /ma 7 , a 8 /d 8 Ca 15 /d 15 , ____ ____ a 16 /d 0 Ca 23 /d 7 , ma 8 , ma 9 , ras, cas, f 1 , st0, st1, ____ ____ __ ble, bhe, r/w ale __ e _____ ____ ____ ____ hold, rdy, ta2 in Cta4 in , tb0 in , tb1 in , int 0 Cint 2 , _____ ____ ____ ad trg , cts 0 , cts 1 , clk 0 , clk 1 , ________ ________ ___ dmareq0Cdmareq3, tc ______ reset x in a 8 /d 8 Ca 15 /d 15 , a 16 /d 0 Ca 23 /d 7 , p4 3 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 , p8 0 Cp8 7 , ____ _____ p9 0 Cp9 7 , p10 0 Cp10 7 , rdy, hold, byte, cnvss, ______ x in , reset a 8 /d 8 Ca 15 /d 15 , a 16 /d 0 Ca 23 /d 7 , p4 3 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 , p8 0 Cp8 7 , p9 0 Cp9 7 , p10 0 Cp10 7 , ____ _____ ______ rdy, hold, byte, cnvss, x in , reset i oh = C10 ma i oh = C400 m a i oh = C10 ma i oh = C400 m a i oh = C10 ma i oh = C400 m a i ol = 10 ma i ol = 2 ma i ol = 10 ma i ol = 2 ma i ol = 10 ma i ol = 2 ma v i = 5 v v i = 0 v when clock is stopped. f(x in ) = 25 mhz (square waveform) ta = 25 c (when clock is stopped) ta = 85 c (when clock is stopped) 3 4.7 3.1 4.8 3.4 4.8 0.4 0.2 0.1 2 v v v v v v v v v v v m a m a v ma m a m a a-d converter characteristics (v cc = 5 v, v ss = 0 v, ta = C20 to 85 c, f(x in ) = 25 mhz, unless otherwise noted) unit test conditions v ref = v cc v ref = v cc v ref = v cc bits lsb k w s v v symbol r ladder t conv v ref v ia parameter resolution absolute accuracy ladder resistance conversion time reference voltage analog input voltage min. 2 9.12 2 0 max. 8 3 10 v cc v ref typ. limits
7721 group users manual 17C83 appendix 11. electrical characteristics appendix internal peripheral devices timing requirements (v cc = 5 v 10 %, v ss = 0 v, ta = C20 to 85 c, f(x in ) = 25 mhz, unless otherwise noted) note: the limits depend on f(x in ). table 3 lists calculation formulas for the limits. limits t c(ta) t w(tah) t w(tal) taj in input cycle time taj in input high-level pulse width taj in input low-level pulse width max. parameter timer a input (count input in event counter mode) timer a input (gating input in timer mode) t c(ta) t w(tah) t w(tal) taj in input cycle time taj in input high-level pulse width taj in input low-level pulse width symbol parameter (note) (note) (note) symbol min. 80 40 40 unit limits min. 320 160 160 max. unit timer a input (external trigger input in one-shot pulse mode) t c(ta) t w(tah) t w(tal) taj in input cycle time taj in input high-level pulse width taj in input low-level pulse width symbol parameter (note) limits min. 160 80 80 max. unit ns ns ns t w(tah) t w(tal) taj in input high-level pulse width taj in input low-level pulse width symbol parameter limits min. 80 80 max. unit timer a input (external trigger input in pulse width modulation mode) ns ns ns ns ns ns ns ns timer a input (up-down input in event counter mode) t c(up) t w(uph) t w(upl) t su(up-t in ) t h(t in -up) taj out input cycle time taj out input high-level pulse width taj out input low-level pulse width taj out input setup time taj out input hold time symbol parameter limits min. 2000 1000 1000 400 400 max. unit ns ns ns ns ns timer a input (two-phase pulse input in event counter mode) t c(ta) t su(taj in Ctaj out ) t su(taj out Ctaj in ) taj in input cycle time taj in input setup time taj out input setup time symbol parameter limits min. 800 200 200 max. unit ns ns ns
7721 group users manual 17C84 appendix appendix 11. electrical characteristics taj in input t c(ta) t w(tah) t w(tal) taj out input (up-down input) t c(up) t w(uph) t w(upl) t h(t in -up) t su(up-t in ) t su(taj in -taj out ) t su(taj out -taj in ) t su(taj in -taj out ) t su(taj out -taj in ) ?p-down input and count input in event counter mode t c(ta) internal peripheral devices ?ount input in event counter mode ?ating input in timer mode ?xternal trigger input in one-shot pulse mode ?xternal trigger input in pulse width modulation mode taj out input (up-down input) taj in input (when counted at falling edge) taj in input (when counted at rising edge) ?wo-phase pulse input in event counter mode taj in input taj out input test conditions ?cc = 5 v 10 % ?nput timing voltage : v il = 1.0 v, v ih = 4.0 v
7721 group users manual 17C85 appendix 11. electrical characteristics appendix limits t c(tb) t w(tbh) t w(tbl) t c(tb) t w(tbh) t w(tbl) tbj in input cycle time (one edge count) tbj in input high-level pulse width (one edge count) tbj in input low-level pulse width (one edge count) tbj in input cycle time (both edges count) tbj in input high-level pulse width (both edges count) tbj in input low-level pulse width (both edges count) max. parameter timer b input (count input in event counter mode) symbol min. 80 40 40 160 80 80 unit ns ns ns ns ns ns timer b input (pulse period measurement mode) t c(tb) t w(tbh) t w(tbl) tbj in input cycle time tbj in input high-level pulse width tbj in input low-level pulse width symbol parameter (note) (note) (note) limits min. 320 160 160 max. unit ns ns ns t c(tb) t w(tbh) t w(tbl) tbj in input cycle time tbj in input high-level pulse width tbj in input low-level pulse width symbol parameter (note) (note) (note) limits min. 320 160 160 max. unit ns ns ns timer b input (pulse width measurement mode) a-d trigger input t c(ad) t w(adl) ad trg input cycle time (trigger enabled minimum) ad trg input low-level pulse width symbol parameter limits min. 1000 125 max. unit ns ns serial i/o t c(ck) t w(ckh) t w(ckl) t d(cCq) t h(cCq) t su(dCc) t h(cCd) clki input cycle time clki input high-level pulse width clki input low-level pulse width txdi output delay time txdi hold time rxdi input setup time rxdi input hold time symbol parameter limits min. 200 100 100 0 20 90 max. unit ns ns ns ns ns ns ns 80 ____ external interrupt inti input t w(inh) t w(inl) ____ inti input high-level pulse width ____ inti input low-level pulse width symbol parameter limits min. 250 250 max. unit ns ns
7721 group users manual 17C86 appendix appendix 11. electrical characteristics tbj in input t c(tb) t w(tbh) t w(tbl) t c(ad) t w(adl) ad trg input t w(inl) t w(inh) int i input t c(ck) t w(ckh) t w(ckl) t h(c-q) t su(d-c) clk i input txd i output rxd i input t d(c-q) t h(c-d) internal peripheral devices test conditions ?cc = 5 v 10 % ?nput timing voltage : v il = 1.0 v, v ih = 4.0 v ?utput timing voltage : v ol = 0.8 v, v oh = 2.0 v
7721 group users manual 17C87 appendix 11. electrical characteristics appendix ready and hold timing requirements (vcc = 5 v 10 %, vss = 0 v, ta = C20 to 85 c, f(x in ) = 25 mhz, unless otherwise noted) switching characteristics (vcc = 5 v 10 %, vss = 0 v, ta = C20 to 85 c, f(x in ) = 25 mhz, unless otherwise noted) limits unit st0, st1 output delay time min. max. 40 ns note: figure 13 shows the test circuit. t d( f 1 Csti) ns ns ns ns unit parameter ____ rdy input setup time _____ hold input setup time ____ rdy input hold time _____ hold input hold time symbol t su(rdyC f 1 ) t su(holdC f 1 ) t h( f 1 Crdy) t h( f 1 Chold) min. 55 55 0 0 limits max. symbol parameter
7721 group users manual 17C88 appendix appendix 11. electrical characteristics 1 with no wait 1 with wait rdy input e output e output rdy input t su(rdy- 1 ) t h( 1 -rdy) t su(rdy- 1 ) t h( 1 -rdy) ?ready function test conditions ?vcc = 5 v 10 % ?input timing voltage : v il = 1.0 v, v ih = 4.0 v ?output timing voltage : v ol = 0.8 v, v oh = 2.0 v 1 hold input sti output t h( 1 -hold) t d( 1 -sti) t su(hold- 1 ) t d( 1 -sti) ?hold function test conditions ?vcc = 5 v 10 % ?input timing voltage : v il = 1.0 v, v ih = 4.0 v ?output timing voltage : v ol = 0.8 v, v oh = 2.0 v
7721 group user?s manual 17e89 appendix 11. electrical characteristics appendix microprocessor mode : with no wait note: the limits depend on f(x in ). table 4 lists calculation formulas for the limits. limits t c t w(h) t w(l) t r t f t su(pidCe) t h(eCpid) external clock input cycle time external clock input high-level pulse width external clock input low-level pulse width external clock input rising time external clock input falling time port pi input setup time (i = 4C10) port pi input hold time (i = 4C10) max. parameter timing requirements (v cc = 5 v 10 %, v ss = 0 v, ta = C20 to 85 c, f(x in ) = 25 mhz, unless otherwise noted) symbol min. 40 15 15 60 0 unit ns ns ns ns ns ns ns 8 8 limits t d(e-piq) t d(alCe) t d(eCdhq) t pxz(eCdhz) t d(amCe) t d(amCale) t d(eCdlq) t pxz(eCdlz) t d(ahCe) t d(ahCale) t d(aleCe) t w(ale) t d(bheCe) t d(bleCe) t d(r/wCe) t d(eC f 1 ) t h(eeal) t h(aleeam) t h(eedhq) t pzx(eedhz) t h(eeam) t h(aleeah) t h(eedlq) t pzx(eedlz) t h(eebhe) t h(eeble) t h(eer/w) t w(el) t su(aedl) t su(aleedl) t su(aedh) t su(aleedh) port pi data output delay time (i = 4e10) address low-order output delay time data high-order output delay time (byte = l) data high-order floating start delay time (byte = l) address middle-order output delay time address middle-order output delay time data low-order output delay time data low-order floating start delay time address high-order output delay time address high-order output delay time ale output delay time ale pulse width ____ bhe output delay time ____ ble output delay time __ r/w output delay time f 1 output delay time address low-order hold time address middle-order hold time (byte = l) data high-order hold time (byte = l) data high-order floating release delay time (byte = l) address middle-order hold time (byte = h) address high-order hold time data low-order hold time data low-order floating release delay time ____ bhe hold time ____ ble hold time __ r/w hold time e pulse width data low-order setup time after address stabilization data low-order setup time after rising of ale data high-order setup time after address stabilization data high-order setup time after rising of ale max. parameter switching characteristics (v cc = 5 v 10 %, v ss = 0 v, ta = C20 to 85 c, f(x in ) = 25 mhz, unless otherwise noted) symbol min. 15 15 5 15 5 4 22 20 20 20 0 18 9 18 20 18 9 18 20 18 18 18 55 unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 80 35 0 35 0 18 50 55 50 55 note: figure 13 shows the test circuit. (note) (note) (note) (note) (note) (note) (note) (note) (note) (note) (note) (note) (note) (note) (note) (note) (note) (note) (note) (note) (note) (note) (note)
7721 group users manual 17C90 appendix appendix 11. electrical characteristics microprocessor mode : with no wait f(x in ) 1 address output a 0 Ca 7 port pi output (i = 4C10) e address/data output a 16 /d 0 Ca 23 /d 7 ale output r/w output t d(am-e) t d(am-e) t w(l) t w(h) t r t f t c t w(el) t d(e- 1 ) t d(e- 1 ) t d(al-e) t d(e-dhq) address address t d(e-dlq) t d(ah-e) data address address t h(ale-am) t d(am-ale) t h(ale-ah) t d(ah-ale) t d(bhe-e) t d(ale-e) t w(ale) t d(ble-e) t d(r/w-e) t h(e-bhe) t h(e-r/w) t d(e-piq) t h(e-al) t h(e-am) t h(e-dhq) t h(e-dlq) t h(e-ble) data address output a 8 Ca 15 (byte = h) address/data output a 8 /d 8 Ca 15 /d 15 (byte = l) data input d 0 Cd 15 (byte = l) data input d 0 Cd 7 bhe output ble output test conditions (port pi) ?vcc = 5 v 10 % ?input timing voltage : v il = 1.0 v, v ih = 4.0 v ?output timing voltage : v ol = 0.8 v, v oh = 2.0 v test conditions (except port pi) ?vcc = 5 v 10 % ?output timing voltage : v ol = 0.8 v, v oh = 2.0 v ?data input : v il = 0.8 v, v ih = 2.5 v
7721 group users manual 17C91 appendix 11. electrical characteristics appendix t d(am-ale) t d(am-e) t d(am-e) t w(l) t w(h) t r t f t c t w(el) t d(e- 1 ) t d(e- 1 ) t d(al-e) t pxz(e-dhz) address address address address t h(ale-am) t d(bhe-e) t d(ale-e) t w(ale) t d(e-piq) t h(e-al) t h(e-am) t pzx(e-dhz) t pzx(e-dlz) t h(e-ble) t d(ble-e) t d(r/w-e) t su(pid-e) t h(e-r/w) data data t h(e-dh) t su(dh-e) t su(a-dh) t su(ale- dh) t pxz(e-dlz) t d(ah-ale) t h(ale-ah) t h(e-dl) t su(dl-e) t su(a-dl) t su(ale-dl) t h(e-bhe) t d(ah-e) microprocessor mode : with no wait f(x in ) 1 address output a 0 Ca 7 port pi input (i = 4C10) e address/data output a 16 /d 0 Ca 23 /d 7 ale output r/w output address output a 8 Ca 15 (byte = h) address/data output a 8 /d 8 Ca 15 /d 15 (byte = l) data input d 8 Cd 15 (byte = l) data input d 0 Cd 7 bhe output ble output test conditions (port pi) ?vcc = 5 v 10 % ?input timing voltage : v il = 1.0 v, v ih = 4.0 v ?output timing voltage : v ol = 0.8 v, v oh = 2.0 v test conditions (except port pi) ?vcc = 5 v 10 % ?output timing voltage : v ol = 0.8 v, v oh = 2.0 v ?data input : v il = 0.8 v, v ih = 2.5 v
7721 group users manual 17C92 appendix appendix 11. electrical characteristics microprocessor mode : with wait note: the limits depend on f(x in ). table 4 lists calculation formulas for the limits. limits t c t w(h) t w(l) t r t f t su(pidCe) t h(eCpid) external clock input cycle time external clock input high-level pulse width external clock input low-level pulse width external clock input rising time external clock input falling time port pi input setup time (i = 4C10) port pi input hold time (i = 4C10) max. parameter timing requirements (v cc = 5 v 10 %, v ss = 0 v, ta = C20 to 85 c, f(x in ) = 25 mhz, unless otherwise noted) symbol min. 40 15 15 60 0 unit ns ns ns ns ns ns ns 8 8 limits max. parameter switching characteristics (v cc = 5 v 10 %, v ss = 0 v, ta = C20 to 85 c, f(x in ) = 25 mhz, unless otherwise noted) symbol min. 15 15 5 15 5 4 22 20 20 20 0 18 9 18 20 18 9 18 20 18 18 18 135 unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 80 35 0 35 0 18 130 135 130 135 note: figure 13 shows the test circuit. (note) (note) (note) (note) (note) (note) (note) (note) (note) (note) (note) (note) (note) (note) (note) (note) (note) (note) (note) (note) (note) (note) (note) t d(e-piq) t d(alCe) t d(eCdhq) t pxz(eCdhz) t d(amCe) t d(amCale) t d(eCdlq) t pxz(eCdlz) t d(ahCe) t d(ahCale) t d(aleCe) t w(ale) t d(bheCe) t d(bleCe) t d(r/wCe) t d(eC f 1 ) t h(eCal) t h(aleCam) t h(eCdhq) t pzx(eCdhz) t h(eCam) t h(aleCah) t h(eCdlq) t pzx(eCdlz) t h(eCbhe) t h(eCble) t h(eCr/w) t w(el) t su(aCdl) t su(aleCdl) t su(aCdh) t su(aleCdh) port pi data output delay time address low-order output delay time data high-order output delay time (byte = l) data high-order floating start delay time (byte = l) address middle-order output delay time address middle-order output delay time data low-order output delay time data low-order floating start delay time address high-order output delay time address high-order output delay time ale output delay time ale pulse width ____ bhe output delay time ____ ble output delay time __ r/w output delay time f 1 output delay time address low-order hold time address middle-order hold time (byte = l) data high-order hold time (byte = l) data high-order floating release delay time (byte = l) address middle-order hold time (byte = h) address high-order hold time data low-order hold time data low-order floating release delay time ____ bhe hold time ____ ble hold time __ r/w hold time __ e pulse width data low-order setup time after address stabilization data low-order setup time after rising of ale data high-order setup time after address stabilization data high-order setup time after rising of ale
7721 group users manual 17C93 appendix 11. electrical characteristics appendix t d(am-e) t d(am-e) t w(l) t w(h) t r t f t c t w(el) t d(e- 1 ) t d(e- 1 ) t d(al-e) t d(e-dhq) address t d(e-dlq) t d(ah-e) address t h(ale-am) t d(am-ale) t h(ale-ah) t d(ah-ale) t h(e-bhe) t d(bhe-e) t d(ale-e) t w(ale) t h(e-r/w) t d(e-piq) t h(e-al) t h(e-am) t h(e-dhq) t h(e-dlq) t h(e-ble) t d(ble-e) t d(r/w-e) data microprocessor mode : with wait f(x in ) 1 address output a 0 Ca 7 port pi output (i = 4C10) e address/data output a 16 /d 0 Ca 23 /d 7 ale output r/w output address output a 8 Ca 15 (byte = h) address/data output a 8 /d 8 Ca 15 /d 15 (byte = l) data input d 0 Cd 15 (byte = l) data input d 0 Cd 7 bhe output ble output test conditions (port pi) ?vcc = 5 v 10 % ?input timing voltage : v il = 1.0 v, v ih = 4.0 v ?output timing voltage : v ol = 0.8 v, v oh = 2.0 v test conditions (except port pi) ?vcc = 5 v 10 % ?output timing voltage : v ol = 0.8 v, v oh = 2.0 v ?data input : v il = 0.8 v, v ih = 2.5 v address address data
7721 group users manual 17C94 appendix appendix 11. electrical characteristics t su(ale-dh) t d(am-ale) t d(am-e) t d(am-e) t w(l) t w(h) t r t f t c t w(el) t d(e- 1 ) t d(e- 1 ) t d(al-e) t pxz(e-dhz) address address address t h(ale-am) t d(bhe-e) t d(ale-e) t w(ale) t d(e-piq) t h(e-al) t h(e-am) t pzx(e-dhz) t pzx(e-dlz) t h(e-ble) t d(ble-e) t d(r/w-e) t su(pid-e) t h(e-r/w) data data t h(e-dh) t su(dh-e) t su(a-dh) t pxz(e-dlz) t d(ah-ale) t h(ale-ah) t h(e-dl) t su(dl-e) t su(a-dl) t su(ale-dl) t h(e-bhe) t d(ah-e) microprocessor mode : with wait f(x in ) 1 address output a 0 Ca 7 port pi input (i = 4C10) e address/data output a 16 /d 0 Ca 23 /d 7 ale output r/w output address output a 8 Ca 15 (byte = h) address/data output a 8 /d 8 Ca 15 /d 15 (byte = l) data input d 8 Cd 15 (byte = l) data input d 0 Cd 7 bhe output ble output test conditions (port pi) ?vcc = 5 v 10 % ?input timing voltage : v il = 1.0 v, v ih = 4.0 v ?output timing voltage : v ol = 0.8 v, v oh = 2.0 v test conditions (except port pi) ?vcc = 5 v 10 % ?output timing voltage : v ol = 0.8 v, v oh = 2.0 v ?data input : v il = 0.8 v, v ih = 2.5 v address
7721 group user?s manual 17e95 appendix 11. electrical characteristics appendix dram control switching characteristics (v cc = 5 v 10 %, v ss = 0 v, ta = C20 to 85 c, f(x in ) = 25 mhz, unless otherwise noted) note: the limits depend on f(x in ). table 5 lists calculation formulas for the limits. limits t w(rasl) t w(casl) t w(rash) t d(rasCcas) t d(raCras) t h(rasCra) t d(caCcas) t h(casCca) t d(r/wCras) t h(casCr/w) t d(eCca) t d(eCrasl) t d(eCcasl) t d(eCrash) t d(eCcash) ____ ras lowClevel pulse width ____ cas lowClevel pulse width ____ cas highClevel pulse width ____ ____ rasCcas delay time ____ row address delay time before ras ____ row address hold time after ras ____ column address delay time before cas ____ column address hold time after cas __ ____ r/w delay time before ras __ ____ r/w hold time after cas __ column address delay time after es low level ____ __ ras delay time after es low level ____ __ cas delay time after es low level ____ __ ras delay time after es high level ____ __ cas delay time after es high level max. parameter read symbol unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns note: figure 13 shows the test circuit. limits t w(rasl) t w(casl) t w(rash) t d(rasCcas) t d(raCras) t h(rasCra) t d(caCcas) t h(casCca) t d(r/wCras) t h(casCr/w) t d(eCrasl) t d(eCcasl) t d(eCrash) t d(eCcash) ____ ras lowClevel pulse width ____ cas lowClevel pulse width ____ cas highClevel pulse width ____ ____ rasCcas delay time ____ row address delay time before ras ____ row address hold time after ras ____ column address delay time before cas ____ column address hold time afrer cas __ ____ r/w delay time before ras __ ____ r/w hold time after cas ____ __ ras delay time after es low level ____ __ cas delay time after es low level ____ __ ras delay time after es high level ____ __ cas delay time after es high level max. parameter write symbol min. 120 55 60 60 5 18 10 60 18 18 80 0 0 unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns (note) (note) (note) (note) (note) (note) (note) (note) (note) (note) (note) (note) (note) (note) (note) (note) (note) (note) (note) (note) (note) (note) 30 115 20 20 note: figure 13 shows the test circuit. limits t w(rasl) t w(casl) t d(casCras) t h(rasCcas) ____ ras lowClevel pulse width ____ cas lowClevel pulse width ____ ___ casCras delay time ____ ____ cas hold time after ras max. parameter refresh state symbol min. 120 55 17.5 17.5 unit ns ns ns ns (note) (note) (note) (note) note: figure 13 shows the test circuit. 65 30 77.5 20 20 min. 120 92.5 60 28 5 18 5 100 18 18 0 0
7721 group users manual 17C96 appendix appendix 11. electrical characteristics r/w output t w(rash) row address t d(ras-cas) t d(ra-ras) t d(r/w-ras) t w(rasl) t d(e-rash) t h(cas-r/w) t d(e-cash) t w(casl) t h(cas-ca) t d(e-ca) t d(ca-cas) t h(ras-ra) t d(e-rasl) t d(e-casl) ma 0 Cma 9 output at read t w(rash) column address row address t d(ras-cas) t d(ra-ras) t d(r/w-ras) t w(rasl) t d(e-rash) t h(cas-r/w) t d(e-cash) t w(casl) t h(cas-ca) t d(ca-cas) t h(ras-ra) t d(e-rasl) t d(e-casl) t w(rasl) t d(cas-ras) at refreshing t h(ras-cas) t w(casl) at dram control 1 e at write cas output ras output r/w output ma 0 Cma 9 output cas output ras output cas output ras output column address test conditions ?vcc = 5 v 10 % ?output timing voltage : v ol = 0.8 v, v oh = 2.0 v ?d 0 Cd 15 input : v il = 0.8 v, v ih = 2.5 v
7721 group users manual 17C97 appendix 11. electrical characteristics appendix dmac switching characteristics (v cc = 5 v 10 %, v ss = 0 v, ta = C20 to 85 c, f(x in ) = 25 mhz, unless otherwise noted) note: the limits depend on f(x in ). table 6 lists calculation formulas for the limits. limits t su(drq- f 1 ) t w(drq) t d( f 1 Csti) t d( f 1 Cdak) t d(alCe) t d(eCdhq) t pxz(eCdhz) t d(amCe) t d(eCdlq) t pxz(eCdlz) t d(ahCe) t d(aleCe) t w(ale) t d(bheCe) t d(bleCe) t d(r/wCe) t h(eCal) t h(aleCam) t h(eCdhq) t pzx(eCdhz) t h(eCam) t h(aleCah) t h(eCdlq) t pzx(eCdlz) t h(eCbhe) t h(eCble) t h(eCr/w) t w(el) t d(data) t d( f 1 Ctc) t w(tc) t su(tc in ) t w(tc in ) ________ dmareqi input setup time ________ dmareqi input pulse width st0, st1 output delay time ________ dmaacki output delay time address low-order output delay time data high-order output delay time (byte = l) data high-order floating start delay time (byte = l) address middle-order output delay time data low-order output delay time data low-order floating start delay time address high-order output delay time ale output delay time ale pulse width ____ bhe output delay time ____ ble output delay time __ r/w output delay time address low-order hold time address middle-order hold time (byte = l) data high-order hold time (byte = l) data high-order floating release delay time (byte = l) address middle-order hold time (byte = h) address high-order hold time data low-order hold time data low-order floating release delay time ____ bhe hold time ____ ble hold time __ r/w hold time __ e pulse width copy delay time ___ tc output delay time ___ tc output pulse width ___ tc input setup time ___ tc input pulse width max. parameter symbol min. 60 80 15 15 4 22 20 20 20 18 9 18 20 18 9 18 20 18 18 18 55 50 50 60 80 unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 40 60 35 0 35 0 (note) (note) (note) (note) (note) (note) (note) (note) (note) (note) (note) (note) (note) (note) (note) (note) (note) (note) 50 note: figures 13 and 14 show the test circuits.
7721 group users manual 17C98 appendix appendix 11. electrical characteristics test conditions ?vcc = 5 v 10 % ?output timing voltage : v ol = 0.8 v, v oh = 2.0 v ?d 0 Cd 15 input : v il = 0.8 v, v ih = 2.5 v ?dmareqi input : v il = 0.8 v, v ih = 2.5 v at dma transfer ?burst transfer timing (external source dmareqi) t w(el) t su(drq- 1 ) address data ad- dress t w(drq) t d( 1 -sti) t d( 1 -dak) t d(al-e) t h(e-al) t d(am-e) t h(e-am) t h(ale-am) t d(e-dhq) t d(e-dlq) t d(ale-e) t w(ale) t d(bhe-e) t d(ble-e) t d(r/w-e) t d(ah-e) t h(ale-ah) t h(e-bhe) t h(e-ble) t h(e-r/w) 1 bhe output e ale output r/w output dmareqi st0 dmaacki a 0 Ca 7 output a 8 /d 8 Ca 15 /d 15 output (byte = l) a 8 /d 8 Ca 15 /d 15 output (byte = h) a 16 /d 0 Ca 23 /d 7 output ble output address address address address address address address data address address address address address address address address data data ad- dress ad- dress ad- dress
7721 group users manual 17C99 appendix 11. electrical characteristics appendix t w(el) t su(drq- 1 ) address data ad- dress t w(drq) t d( 1 -sti) t d( 1 -dak) t d(al-e) t h(e-al) t d(am-e) t h(e-am) t d(ale-e) t w(ale) t d(bhe-e) t d(ble-e) t d(r/w-e) t d(ah-e) t h(e-bhe) t h(e-ble) t d( 1 -dak) t d( 1 -sti) at dma transfer ?cycle-steal transfer timing (external source dmareqi) 1 bhe output e ale output r/w output st0 a 0 Ca 7 output a 8 /d 8 Ca 15 /d 15 output (byte = l) a 8 /d 8 Ca 15 /d 15 output (byte = h) a 16 /d 0 Ca 23 /d 7 output ble output test conditions ?vcc = 5 v 10 % ?output timing voltage : v ol = 0.8 v, v oh = 2.0 v ?d 0 Cd 15 input : v il = 0.8 v, v ih = 2.5 v ?dmareqi input : v il = 0.8 v, v ih = 2.5 v dmareqi dmaacki address address address address address address address address address address address address data address address address ad- dress ad- dress ad- dress
7721 group users manual 17C100 appendix appendix 11. electrical characteristics address t pzx(e-dhz) t h(e-al) t h(e-dh) t d(ale-e) t w(ale) t d(bhe-e) t d(ble-e) t d(r/w-e) t d( 1 -dak) t d( 1 -dak) t d(al-e) t pxz(e-dhz) t su(dh-e) data t h(e-bhe) t h(e-ble) t h(e-r/w) t d(data) t pzx(e-dlz) t h(e-al) t d(ale-e) t w(ale) t d(bhe-e) t d(ble-e) t d(r/w-e) t d( 1 -dak) t d( 1 -dak) t d(al-e) t h(e-bhe) t h(e-ble) t h(e-r/w) t pxz(e-dlz) t h(e-dl) t su(dl-e) t d(data) at dma transfer ?1-bus transfer timing 1 bhe output e ale output r/w output a 0 Ca 7 output a 8 /d 8 Ca 15 /d 15 output (byte = l) a 16 /d 0 Ca 23 /d 7 output ble output test conditions ?vcc = 5 v 10 % ?output timing voltage : v ol = 0.8 v, v oh = 2.0 v ?d 0 Cd 15 input : v il = 0.8 v, v ih = 2.5 v dmaacki d 0 Cd 15 input d 0 Cd 7 output ad- dress address data ad- dress ad- dress ad- dress
7721 group users manual 17C101 appendix 11. electrical characteristics appendix t d(ble-e) t w(tc) address t d( 1-dak) t h(e-al) t d(al-e) t h(e-bhe) t h(e-ble) t h(e-r/w) t d(bhe-e) t d( 1-sti) t h(e-am) t d(am-e) t d( 1-tc) data t h(e-dhq) t h(e-dlq) t d(ah-e) t d(r/w-e) at dma transfer ?transfer complete timing 1 bhe output e ale output r/w output a 0 Ca 7 output a 8 /d 8 Ca 15 /d 15 output (byte = l) a 16 /d 0 Ca 23 /d 7 output ble output test conditions ?vcc = 5 v 10 % ?output timing voltage : v ol = 0.8 v, v oh = 2.0 v ?d 0 Cd 15 input : v il = 0.8 v, v ih = 2.5 v dmaacki tc st0 a 8 /d 8 Ca 15 /d 15 output (byte = h) address address address address address address address address address address address data data data ad- dress ad- dress ad- dress ad- dress
7721 group users manual 17C102 appendix appendix 11. electrical characteristics destination address source address address data t d( 1-sti) t d(al-e) t d(am-e) t h(ale-am) t d(e-dhq) t d(e-dlq) t d(ale-e) t w(ale) t d(r/w-e) t d(ah-e) t h(ale-ah) t h(e-r/w) t su(tc in ) t d( 1-dak) t w(tc in ) t h(e-al) t h(e-am) when dma transfer is forcedly completed by tc input ?tc input timing 1 e ale output r/w output a 0 Ca 7 output a 8 /d 8 Ca 15 /d 15 output (byte = l) a 16 /d 0 Ca 23 /d 7 output test conditions ?vcc = 5 v 10 % ?output timing voltage : v ol = 0.8 v, v oh = 2.0 v ?d 0 Cd 15 input : v il = 0.8 v, v ih = 2.5 v ?tc input : v il = 0.8 v, v ih = 2.5 v dmaacki tc input st0 a 8 /d 8 Ca 15 /d 15 output (byte = h) destination address destination address destination address address address address data data data source address destination address source address destination address source address
7721 group users manual 17C103 appendix 11. electrical characteristics appendix table 3 calculation formulas for internal peripheral devices input/output timing depending on f(x in ) (vcc = 5 v 10 %, vss = 0 v, ta = C20 to 85 c) timer a input (gating input in timer mode) symbol t c(ta) t w(tah) t w(tal) calculation formula unit ns ns ns 4 5 10 9 f(x in ) 4 5 10 9 f(x in ) 8 5 10 9 f(x in ) symbol t c(ta) unit ns 4 5 10 9 f(x in ) timer a input (external trigger input in one-shot pulse mode) timer b input (pulse period measurement mode) timer b input (pulse width measurement mode) symbol t c(tb) t w(tbh) t w(tbl) unit ns ns ns 4 5 10 9 f(x in ) 4 5 10 9 f(x in ) 8 5 10 9 f(x in ) symbol t c(tb) t w(tbh) t w(tbl) unit ns ns ns 4 5 10 9 f(x in ) 4 5 10 9 f(x in ) 8 5 10 9 f(x in ) calculation formula calculation formula calculation formula
7721 group user?s manual 17e104 appendix appendix 11. electrical characteristics t d(alCe) t d(amCe) t d(ahCe) t d(amCale) t d(ahCale) t w(ale) t d(bleCe) t d(bheCe) t d(r/wCe) t h(eCal) t h(eCam) t h(eCdlq) t h(eCdhq) t pzx(eCdlz) t pzx(eCdhz) t h(eCble) t h(eCbhe) t h(eCr/w) t w(el) t su(aCdl) t su(aCdh) t su(aleCdl) t su(aleCdh) table 4 calculation formulas for bus timing depending on f(x in ) (vcc = 5 v 10 %, vss = 0 v, ta = C20 to 85 c) wait bit = 1 wait bit = 0 wait bit = 1 wait bit = 0 wait bit = 1 wait bit = 0 symbol unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns 1 5 10 9 f(x in ) 1 5 10 9 f(x in ) 1 5 10 9 f(x in ) 1 5 10 9 f(x in ) 1 5 10 9 f(x in ) 1 5 10 9 f(x in ) 1 5 10 9 f(x in ) 1 5 10 9 f(x in ) 2 5 10 9 f(x in ) 4 5 10 9 f(x in ) 3 5 10 9 f(x in ) 5 5 10 9 f(x in ) 3 5 10 9 f(x in ) 5 5 10 9 f(x in ) e 25 e 35 e 18 e 20 e 22 e 22 e 20 e 22 e 25 e 65 e 70 e 25 e 70 e 65 calculation formula
7721 group users manual 17C105 appendix 11. electrical characteristics appendix table 5 calculation formulas for dram control bus timing depending of f(x in ) (vcc = 5 v 10 %, vss = 0 v, ta = C20 to 85 c) read symbol t w(rasl) t w(casl) t w(rash) t d(rasCcas) t d(raCras) t h(rasCra) calculation formula unit ns ns ns ns ns ns 3 5 10 9 f(x in ) 4 5 10 9 f(x in ) 2 5 10 9 f(x in ) C 40 C 27.5 C 20 1 5 10 9 f(x in ) 1 5 10 9 f(x in ) 1 5 10 9 f(x in ) C 12 C 22 C 35 unit ns ns ns ns ns 1 5 10 9 f(x in ) 4 5 10 9 f(x in ) 1 5 10 9 f(x in ) C 60 C 22 C 22 1 5 10 9 f(x in ) + 25 symbol t h(casCca) t d(r/wCras) t h(casCr/w) t d(eCca) t d(eCcasl) calculation formula 1 5 10 9 f(x in ) + 37.5 write symbol t w(rasl) t w(casl) t w(rash) t d(rasCcas) t d(raCras) t h(rasCra) unit ns ns ns ns ns ns 2 5 10 9 f(x in ) 4 5 10 9 f(x in ) 2 5 10 9 f(x in ) C 40 C 25 C 20 1 5 10 9 f(x in ) 2 5 10 9 f(x in ) 1 5 10 9 f(x in ) C 20 C 22 C 35 unit ns ns ns ns ns 3 5 10 9 f(x in ) 1 5 10 9 f(x in ) 1 5 10 9 f(x in ) C 30 C 60 C 22 1 5 10 9 f(x in ) C 22 symbol t d(caCcas) t h(casCca) t d(r/wCras) t h(casCr/w) t d(eCcasl) calculation formula 2 5 10 9 f(x in ) + 35(0) ] ] the value within ( ) is for the minimum value. refresh symbol t w(rasl) t w(casl) unit ns ns 2 5 10 9 f(x in ) 4 5 10 9 f(x in ) C 40 unit ns ns 1 5 10 9 f(x in ) 1 5 10 9 f(x in ) symbol t d(casCras) t h(rasCcas) calculation formula C 25 calculation formula calculation formula C 22.5 C 22.5
7721 group users manual 17C106 appendix appendix 11. electrical characteristics fig. 13 test circuit for each pin ___ fig. 14 test circuit for tc output delay time and ___ tc output pulse width a 0 /ma 0 Ca 7 /ma 7 a 8 /d 8 Ca 15 /d 15 a 16 /d 0 Ca 23 /d 7 p4 p5 p6 p7 p8 p9 p10 e 1 100 pf 100 pf tc 3 k w table 6 calculation formulas for dma transfer bus timing depending on f(x in ) (vcc = 5 v 10 %, vss = 0 v, ta = C20 to 85 c) t d(alCe) t d(amCe) t d(ahCe) t w(ale) t d(bleCe) t d(bheCe) t d(r/wCe) t h(eCal) t h(eCam) t h(eCdlq) t h(eCdhq) t pzx(eCdlz) t pzx(eCdhz) t h(eCble) t h(eCbhe) t h(eCr/w) t w(el) t w(tc) symbol unit 1 5 10 9 f(x in ) 1 5 10 9 f(x in ) 1 5 10 9 f(x in ) 1 5 10 9 f(x in ) 1 5 10 9 f(x in ) 1 5 10 9 f(x in ) 2 5 10 9 f(x in ) 4 5 10 9 f(x in ) 2 5 10 9 f(x in ) C 25 C 18 C 20 C 22 C 22 C 25 C 22 C 20 C 25 C 30 ns ns ns ns ns ns ns ns ns ns f(x in ) 1 5 10 9 transfer source/transfer destination wait bit = 1 transfer source/transfer destination wait bit = 0 calculation formula
appendix 7721 group users manual 17C107 appendix 12. standard characteristics appendix 12. standard characteristics standard characteristics described below are just examples of the m37721s2bfps characteristics and are not guaranteed. for each parameters limits, refer to section appendix 11. electrical characteristics. 1. programmable i/o port (cmos output) standard characteristics (1) p-channel i oh Cv oh characteristics (2) n-channel i ol Cv ol characteristics 30.0 24.0 18.0 12.0 6.0 0 1.0 2.0 3.0 4.0 5.0 v ol [v] i ol [ma] ta = 25 ? ta = 85 ? 30.0 24.0 18.0 12.0 6.0 0 1.0 2.0 3.0 4.0 5.0 v oh [v] i oh [ma] ta = 25 ? ta = 85 ?
appendix appendix 12. standard characteristics 7721 group users manual 17C108 2. iccCf(x in ) standard characteristics (1) iccCf(x in ) characteristics on operating and at reset (2) wait mode 0 10 20 30 0 5 10 15 20 25 30 f(x in ) [mhz] icc [ma] measurement condition (vcc = 5.0 v, ta = 25 ?, f(x in ) : square waveform, microprocessor mode) at reset on operating 0 2 4 6 8 10 0 5 10 15 20 25 30 f(x in ) [mhz] icc [ma] measurement condition (vcc = 5.0 v, ta = 25 ?, f(x in ) : square waveform, microprocessor mode)
appendix 7721 group users manual 17C109 appendix 12. standard characteristics 3. a-d converter standard characteristics the lower lines of the graph indicate the absolute precision errors. these are expressed as the deviation from the ideal value when the output code changes. for example, the change in output code from 0 to 1 should occur at 10 mv, but the measured value is +2 mv. accordingly, the measured point of change is 10 + 2 = 12 mv. the upper lines of the graph indicate the input voltage width for which the output code is constant. for example, the measured input voltage width for which the output code is 15 is 24 mv, so that the differential non-linear error is 24 C 20 = 4 mv (0.2 lsb). [measurement conditions] ?vcc = 5 v, v ref = 5.12 v, f(x in ) = 25 mhz, ta = 25 c, f ad = f 2 divided by 2 30 0 20 30 10 0 1lsb width error [mv] [mv] step no. 20 10 0 C10 C20 C30 8 1624324048566472808896104112120128 30 128 20 30 10 0 1lsb width error step no. 20 10 0 C10 C20 C30 136 144 152 160 168 176 184 192 200 208 216 224 232 240 248 256 [mv] [mv]
appendix appendix 12. standard characteristics 7721 group users manual 17C110 memorandum
glossary
glossary 7721 group users manual 2 this section briefly explains the terms used in this users manual. the terms defined here apply to this manual only. term access access space access characteristics branch bus control signal countdown count source countup external area external bus external device internal area interrupt routine overflow read-modify-write instruction signal required for access to external device stop mode uart underflow wait mode meaning means performing read, write, or read and write. in dramc, also means performing dram refresh. an accessible memory space of up to 16 mbytes. means whether accessible or not. means moving the programs execution point (= address) to another location. __ __ ____ ____ ____ _____ _____ a generic name for ale, e , r/ w , ble , bhe , rdy , hold , hlda, byte, st0, and st1 signals. means decreasing by 1 and counting. a signal that is counted by timers a and b, the uarti baud rate register (brgi) and the watchdog timer. that is f 2 , f 16 , f 64 , f 512 selected by the count source select bits and others. means increasing by 1 and counting. an accessible area for external devices connected. it is up to 16- mbyte external area. a generic name for the external address bus and the external data bus. devices connected externally to the microcomputer. a generic name for a memory, an i/o device and a peripheral ic. an accessible internal area. a generic name for areas of the internal ram and the sfr. a routine that is automatically executed when an interrupt request is accepted. set the start address of this routine into the interrupt vector table. a state where the countup resultant is greater than the counter resolution. an instruction that reads the memory contents, modifies them and writes back to the same address. relevant instructions are the asl , asr , clb , dec , inc , lsr , rol , ror , seb instructions. a generic name for bus control, address bus, and data bus signals. a state where the oscillation circuit halts and the program execution is stopped. by executing the stp instruction, the microcomputer enters the stop mode. clock asynchronous serial i/o. when used to designate the name of a functional block, this term also means the serial i/o which can be switched to the cock synchronous serial i/o. a state where the countdown resultant is greater than the counter resolution. a state where the oscillation circuit is operating, however, the program execution is stopped. by executing the wit instruction, the microcomputer enters the wait mode. relevant term access access countup countdown internal area external area underflow countup bus control signal wait mode clock synchronous serial i/o overflow countdown stop mode
mitsubishi semiconductors users manual 7721 group sep. first edition 1997 editioned by committee of editing of mitsubishi semiconductor users manual published by mitsubishi electric corp., semiconductor marketing division this book, or parts thereof, may not be reproduced in any form without permission of mitsubishi electric corporation. ?1997 mitsubishi electric corporation
users manual 7721 group ? 1997 mitsubishi electric corporation. new publication, effective sep. 1997. specifications subject to change without notice.

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